From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D304A313E1F; Thu, 28 Aug 2025 14:01:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389665; cv=none; b=gQZCywYwQFE14pvGs6axxOYkAbC2uKlp1nGQ5LB0X2yJXIESU1aBLaccg8ByolVQOsxqBhBbNEB6EBm5U+Udry9RF4uVJmm4jrDymRXxF4jBhRfCICArJDXv8mt+dfaQHbK1ygPvKASD8zNOKGxmGDdJRuFQxVAE0THhR5Alam8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389665; c=relaxed/simple; bh=qqr07bOWFXFo1de483KKM0R6r/8XR8QBS/GymmOJMEY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Y8/tbARssS+DdReLIJQEVldCnPtUrOGnzYuAPhBlLl0r3A/dpWVm7jAN129I3Hy0Wu6FIQ2A/WaGz05frpeLmBDtaj3qptXa4AdbXuYpeYm82Hkm49srE1/sOdwioeIf233jfJbZKalBxmN3eYucbXDN4zs1kuH3jOBRcCWfTCU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=NecW1Km4; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="NecW1Km4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=CM hpxNJlxWk8k4Tu3vBM/b3KUER7t/n0NRgjW9FcPXU=; b=NecW1Km41cshUxLKXe WctpXqSxBrDDPToFwmljLKR5xsGsWxKA0HIcFuL8lJxBb6BQPWR9iyKl2LFNldf+ poWXcwGU4+aesdcmG27AJOJraplUCpFP65sH/ef4dZ8Fp/U4JaAp1pdnrvfAlTzU AuvTSv5KJIwPmWnI/RGuIF7Vs= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgAXBtYDYbBoN0ahAw--.5480S3; Thu, 28 Aug 2025 22:00:37 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 01/13] PCI: dwc: Add dw_pcie_*_dword() for register bit manipulation Date: Thu, 28 Aug 2025 21:59:39 +0800 Message-Id: <20250828135951.758100-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgAXBtYDYbBoN0ahAw--.5480S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7Zr18uF1DGw1DGw4rGrWkXrb_yoW8ZFyUpa yUtrW3CF47Aa1a9anxAan3ZryYy3Z3AF43CrZxG3W2qF17Aryqqa4rtFy5trn7GrWIqr17 Kr4Dt3yxWan8ArDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pK9av_UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOh23o2iwWw2TngAAsw Content-Type: text/plain; charset="utf-8" DesignWare PCIe controller drivers implement register bit manipulation through explicit read-modify-write sequences. These patterns appear repeatedly across multiple drivers with minor variations, creating code duplication and maintenance overhead. Implement dw_pcie_*_dword() helper to encapsulate atomic register modification. The function reads the current register value, clears specified bits, sets new bits, and writes back the result in a single operation. This abstraction hides bitwise manipulation details while ensuring consistent behavior across all usage sites. Centralizing this logic reduces future maintenance effort when modifying register access patterns and minimizes the risk of implementation divergence between drivers. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware.h | 23 ++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 00f52d472dcd..ae18b657938a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -702,6 +702,29 @@ static inline void dw_pcie_ep_writel_dbi2(struct dw_pc= ie_ep *ep, u8 func_no, dw_pcie_ep_write_dbi2(ep, func_no, reg, 0x4, val); } =20 +static inline void dw_pcie_clear_and_set_dword(struct dw_pcie *pci, int po= s, + u32 clear, u32 set) +{ + u32 val; + + val =3D dw_pcie_readl_dbi(pci, pos); + val &=3D ~clear; + val |=3D set; + dw_pcie_writel_dbi(pci, pos, val); +} + +static inline void dw_pcie_clear_dword(struct dw_pcie *pci, int pos, + u32 clear) +{ + dw_pcie_clear_and_set_dword(pci, pos, clear, 0); +} + +static inline void dw_pcie_set_dword(struct dw_pcie *pci, int pos, + u32 set) +{ + dw_pcie_clear_and_set_dword(pci, pos, 0, set); +} + static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) { u32 reg; --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0628013C8E8; Thu, 28 Aug 2025 14:00:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389661; cv=none; b=rC5WOB6+tfXsk39idZShQ7keBBBtSZxZJV0mvZJ8UnDd72J0BCVXeUJxXobhGdZTk2QZv817eeKjWV/Biawmqj22dVXjv2tC9pIMBzbrShvBxysB47hhMWTVsyWSJ9VNdj9mAq5K8gvkhDqfFWdGJ16o8Jz1o/p3o1H0Gp3sVuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389661; c=relaxed/simple; bh=cOXxouYpYuk+Do623nt2bL6E4GCUfvCfr1lLgnnFa40=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kpk8DW5WVSE2NWx34p0v6EL06PPqCJUcacn1eNxtM5LA1KLquewl1hxW23BMLl4GgMSaj2jlHeVmwyuQNm3qRrT2f35Cx12QVy+HKbU9xeMgUhAcBeAC5egbN8X2GYPgNW/5FVE8fYrPusqsrQl/+P/8FMAj9+nuhDpA2RzAYiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=XQL+eLbc; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="XQL+eLbc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=sw UmOCG3BXRSDD4bZYro9X3xvdGLXd9ngQpXNKUAoTg=; b=XQL+eLbcWgkKm7s/wO QVgGq/3GvXFDn2pdocMHKyqdj6FB4nKC60rP0dUTPbsDXP8YShJCmkaEyc6m9G+Q a1Sc3+I0HwydwxpcurLFGpgH7niswnZhP0a87yEEaWWVn7x/0hvlTOl65Fp9aD+k lYseCTC3mzlc+MHHmqP+5kIvA= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgAXBtYDYbBoN0ahAw--.5480S4; Thu, 28 Aug 2025 22:00:38 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 02/13] PCI: dwc: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:40 +0800 Message-Id: <20250828135951.758100-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgAXBtYDYbBoN0ahAw--.5480S4 X-Coremail-Antispam: 1Uf129KBjvAXoWfJrykCw18uFW5Zr4DGF1xXwb_yoW8Xry7uo Z3XF15W3W7JF10qFy8tasxKryUZrnFvFy5XFsFkw4jkay3A3W5A39agF13Zw4Y9w4xC34r Xa1kG3Z8Zr47Xr17n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4iD3kGUUUUU X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQwG3o2iwWuZ9YAADss Content-Type: text/plain; charset="utf-8" DesignWare core modules contain multiple instances of manual read-modify-write operations for register bit manipulation. These patterns duplicate functionality now provided by dw_pcie_*_dword(), particularly in debugfs, endpoint, host, and core initialization paths. Replace open-coded bit manipulation sequences with calls to dw_pcie_*_dword(). Affected areas include debugfs register control, endpoint capability configuration, host setup routines, and core link initialization logic. The changes simplify power management handling, capability masking, and feature configuration. Standardizing on the helper function reduces code duplication by ~140 lines across core modules while improving readability. The refactoring also ensures consistent error handling for register operations and provides a single point of control for future bit manipulation logic updates. Signed-off-by: Hans Zhang <18255117159@163.com> --- .../controller/dwc/pcie-designware-debugfs.c | 48 +++++------- .../pci/controller/dwc/pcie-designware-ep.c | 19 ++--- .../pci/controller/dwc/pcie-designware-host.c | 26 +++---- drivers/pci/controller/dwc/pcie-designware.c | 75 +++++++------------ drivers/pci/controller/dwc/pcie-designware.h | 16 +--- 5 files changed, 66 insertions(+), 118 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers= /pci/controller/dwc/pcie-designware-debugfs.c index 0fbf86c0b97e..652e7cf691aa 100644 --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -213,10 +213,8 @@ static ssize_t lane_detect_write(struct file *file, co= nst char __user *buf, if (val) return val; =20 - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_R= EG); - val &=3D ~(LANE_SELECT); - val |=3D FIELD_PREP(LANE_SELECT, lane); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val= ); + dw_pcie_clear_and_set_dword(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE= _REG, + LANE_SELECT, FIELD_PREP(LANE_SELECT, lane)); =20 return count; } @@ -415,10 +413,9 @@ static ssize_t counter_lane_write(struct file *file, c= onst char __user *buf, =20 mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); - val &=3D ~(EVENT_COUNTER_LANE_SELECT); - val |=3D FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + dw_pcie_clear_and_set_dword(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_CO= UNTER_CTRL_REG, + EVENT_COUNTER_LANE_SELECT, + FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane)); mutex_unlock(&rinfo->reg_event_lock); =20 return count; @@ -654,20 +651,15 @@ static int dw_pcie_ptm_check_capability(void *drvdata) static int dw_pcie_ptm_context_update_write(void *drvdata, u8 mode) { struct dw_pcie *pci =3D drvdata; - u32 val; =20 - if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_AUTO) { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val |=3D PTM_REQ_AUTO_UPDATE_ENABLED; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } else if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_MANUAL) { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val &=3D ~PTM_REQ_AUTO_UPDATE_ENABLED; - val |=3D PTM_REQ_START_UPDATE; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } else { + if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_AUTO) + dw_pcie_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + PTM_REQ_AUTO_UPDATE_ENABLED); + else if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_MANUAL) + dw_pcie_clear_and_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + PTM_REQ_AUTO_UPDATE_ENABLED, PTM_REQ_START_UPDATE); + else return -EINVAL; - } =20 return 0; } @@ -694,17 +686,13 @@ static int dw_pcie_ptm_context_update_read(void *drvd= ata, u8 *mode) static int dw_pcie_ptm_context_valid_write(void *drvdata, bool valid) { struct dw_pcie *pci =3D drvdata; - u32 val; =20 - if (valid) { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val |=3D PTM_RES_CCONTEXT_VALID; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } else { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val &=3D ~PTM_RES_CCONTEXT_VALID; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } + if (valid) + dw_pcie_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + PTM_RES_CCONTEXT_VALID); + else + dw_pcie_clear_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + PTM_RES_CCONTEXT_VALID); =20 return 0; } diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 0ae54a94809b..e5b59b2c2292 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -277,7 +277,7 @@ static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_= ep *ep, u8 func_no, int flags =3D epf_bar->flags; u32 reg =3D PCI_BASE_ADDRESS_0 + (4 * bar); unsigned int rebar_offset; - u32 rebar_cap, rebar_ctrl; + u32 rebar_cap; int ret; =20 rebar_offset =3D dw_pcie_ep_get_rebar_offset(pci, bar); @@ -310,9 +310,8 @@ static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_= ep *ep, u8 func_no, * 1 MB to 128 TB. Bits 31:16 in PCI_REBAR_CTRL define "supported sizes" * bits for sizes 256 TB to 8 EB. Disallow sizes 256 TB to 8 EB. */ - rebar_ctrl =3D dw_pcie_readl_dbi(pci, rebar_offset + PCI_REBAR_CTRL); - rebar_ctrl &=3D ~GENMASK(31, 16); - dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CTRL, rebar_ctrl); + dw_pcie_clear_dword(pci, rebar_offset + PCI_REBAR_CTRL, + GENMASK(31, 16)); =20 /* * The "selected size" (bits 13:8) in PCI_REBAR_CTRL are automatically @@ -925,7 +924,7 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) struct dw_pcie_ep_func *ep_func; struct device *dev =3D pci->dev; struct pci_epc *epc =3D ep->epc; - u32 ptm_cap_base, reg; + u32 ptm_cap_base; u8 hdr_type; u8 func_no; void *addr; @@ -1001,13 +1000,11 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) */ if (ptm_cap_base) { dw_pcie_dbi_ro_wr_en(pci); - reg =3D dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); - reg &=3D ~PCI_PTM_CAP_ROOT; - dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + dw_pcie_clear_dword(pci, ptm_cap_base + PCI_PTM_CAP, + PCI_PTM_CAP_ROOT); =20 - reg =3D dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); - reg &=3D ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK); - dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + dw_pcie_clear_dword(pci, ptm_cap_base + PCI_PTM_CAP, + PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK); dw_pcie_dbi_ro_wr_dis(pci); } =20 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 952f8594b501..ded18122f5a6 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -904,7 +904,6 @@ static void dw_pcie_config_presets(struct dw_pcie_rp *p= p) int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - u32 val; int ret; =20 /* @@ -922,23 +921,17 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); =20 /* Setup interrupt pins */ - val =3D dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); - val &=3D 0xffff00ff; - val |=3D 0x00000100; - dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); + dw_pcie_clear_and_set_dword(pci, PCI_INTERRUPT_LINE, + 0x0000ff00, 0x00000100); =20 /* Setup bus numbers */ - val =3D dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); - val &=3D 0xff000000; - val |=3D 0x00ff0100; - dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); + dw_pcie_clear_and_set_dword(pci, PCI_PRIMARY_BUS, + 0x00ffffff, 0x00ff0100); =20 /* Setup command register */ - val =3D dw_pcie_readl_dbi(pci, PCI_COMMAND); - val &=3D 0xffff0000; - val |=3D PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_clear_and_set_dword(pci, PCI_COMMAND, 0x0000ffff, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SERR); =20 dw_pcie_config_presets(pp); /* @@ -957,9 +950,8 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) /* Program correct class for RC */ dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); =20 - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_SPEED_CHANGE); =20 dw_pcie_dbi_ro_wr_dis(pci); =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 89aad5a08928..77b66af73ab3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -748,11 +748,8 @@ EXPORT_SYMBOL_GPL(dw_pcie_link_up); =20 void dw_pcie_upconfig_setup(struct dw_pcie *pci) { - u32 val; - - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); - val |=3D PORT_MLTI_UPCFG_SUPPORT; - dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); + dw_pcie_set_dword(pci, PCIE_PORT_MULTI_LANE_CTRL, + PORT_MLTI_UPCFG_SUPPORT); } EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); =20 @@ -813,21 +810,12 @@ int dw_pcie_link_get_max_link_width(struct dw_pcie *p= ci) =20 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_l= anes) { - u32 lnkcap, lwsc, plc; + u32 plc =3D 0; u8 cap; =20 if (!num_lanes) return; =20 - /* Set the number of lanes */ - plc =3D dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); - plc &=3D ~PORT_LINK_FAST_LINK_MODE; - plc &=3D ~PORT_LINK_MODE_MASK; - - /* Set link width speed control register */ - lwsc =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - lwsc &=3D ~PORT_LOGIC_LINK_WIDTH_MASK; - lwsc |=3D PORT_LOGIC_LINK_WIDTH_1_LANES; switch (num_lanes) { case 1: plc |=3D PORT_LINK_MODE_1_LANES; @@ -845,14 +833,20 @@ static void dw_pcie_link_set_max_link_width(struct dw= _pcie *pci, u32 num_lanes) dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); return; } - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); + /* Set the number of lanes */ + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_LINK_CONTROL, + PORT_LINK_FAST_LINK_MODE | PORT_LINK_MODE_MASK, + plc); + + /* Set link width speed control register */ + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_LINK_WIDTH_MASK, + PORT_LOGIC_LINK_WIDTH_1_LANES); =20 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); - lnkcap &=3D ~PCI_EXP_LNKCAP_MLW; - lnkcap |=3D FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes); - dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); + dw_pcie_clear_and_set_dword(pci, cap + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_MLW, + FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes)); } =20 void dw_pcie_iatu_detect(struct dw_pcie *pci) @@ -1141,38 +1135,27 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) =20 void dw_pcie_setup(struct dw_pcie *pci) { - u32 val; - dw_pcie_link_set_max_speed(pci); =20 /* Configure Gen1 N_FTS */ - if (pci->n_fts[0]) { - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); - val &=3D ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK); - val |=3D PORT_AFR_N_FTS(pci->n_fts[0]); - val |=3D PORT_AFR_CC_N_FTS(pci->n_fts[0]); - dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); - } + if (pci->n_fts[0]) + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_AFR, + PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK, + PORT_AFR_N_FTS(pci->n_fts[0]) | + PORT_AFR_CC_N_FTS(pci->n_fts[0])); =20 /* Configure Gen2+ N_FTS */ - if (pci->n_fts[1]) { - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val &=3D ~PORT_LOGIC_N_FTS_MASK; - val |=3D pci->n_fts[1]; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); - } + if (pci->n_fts[1]) + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_N_FTS_MASK, pci->n_fts[1]); =20 - if (dw_pcie_cap_is(pci, CDM_CHECK)) { - val =3D dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); - val |=3D PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | - PCIE_PL_CHK_REG_CHK_REG_START; - dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); - } + if (dw_pcie_cap_is(pci, CDM_CHECK)) + dw_pcie_set_dword(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, + PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | + PCIE_PL_CHK_REG_CHK_REG_START); =20 - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); - val &=3D ~PORT_LINK_FAST_LINK_MODE; - val |=3D PORT_LINK_DLL_LINK_EN; - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_LINK_CONTROL, + PORT_LINK_FAST_LINK_MODE, PORT_LINK_DLL_LINK_EN); =20 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index ae18b657938a..fadc8bcb06bc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -727,24 +727,12 @@ static inline void dw_pcie_set_dword(struct dw_pcie *= pci, int pos, =20 static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) { - u32 reg; - u32 val; - - reg =3D PCIE_MISC_CONTROL_1_OFF; - val =3D dw_pcie_readl_dbi(pci, reg); - val |=3D PCIE_DBI_RO_WR_EN; - dw_pcie_writel_dbi(pci, reg, val); + dw_pcie_set_dword(pci, PCIE_MISC_CONTROL_1_OFF, PCIE_DBI_RO_WR_EN); } =20 static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) { - u32 reg; - u32 val; - - reg =3D PCIE_MISC_CONTROL_1_OFF; - val =3D dw_pcie_readl_dbi(pci, reg); - val &=3D ~PCIE_DBI_RO_WR_EN; - dw_pcie_writel_dbi(pci, reg, val); + dw_pcie_clear_dword(pci, PCIE_MISC_CONTROL_1_OFF, PCIE_DBI_RO_WR_EN); } =20 static inline int dw_pcie_start_link(struct dw_pcie *pci) --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EA9881E832E; Thu, 28 Aug 2025 14:00:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389654; cv=none; b=qkDB8ObBqnSX9EX8+THZuK5OiS6kg2sK5CH+0IeTDJWApIyKw9jBgmPsIgpMzY4Brlv4McvyLFe0HQOuiRXU9teAEHmNq8A2lZIjphAmZDDu2dL3CIqgL9sijklFXXkcrpdhMMuRb7Y/OqY2X8gp814tTVnz8WnK/17xnp4nraw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389654; c=relaxed/simple; bh=0hsAwdZcPAE8109DLO0fnD5sMW8/O2GLi22R2B/RC90=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=j8Vnb9eqy9yff6alC2XggLTmFi2sDViUUe5vIPpfz5YyaPX20bRRkG8CxemKc87swZ/u87WPP3bPr8Fk7fzEXQecZaYTU1ttE+4FJ37sHckArYD8I03+1Yy9mkjow9hWJCaEzhclVZhgi1WAPZ5mViwWP8MPiAiy5rcsmrlbd8g= ARC-Authentication-Results: i=1; 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Thu, 28 Aug 2025 22:00:38 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 03/13] PCI: dra7xx: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:41 +0800 Message-Id: <20250828135951.758100-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgAXBtYDYbBoN0ahAw--.5480S5 X-Coremail-Antispam: 1Uf129KBjvJXoW7KrWkGrWkKr1xuFyrXF13Jwb_yoW8uFy8p3 9xCFZay3W7Jan5X3Wqv3Wku3WSva93ZrWUtan7Kw1fZF9Fyr9rArWFyryrtF4fuFWj9r1j va15tw1xJw4YyFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRcVyDUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQwS3o2iwWuaXkAAAsw Content-Type: text/plain; charset="utf-8" The dra7xx PCIe driver implements suspend/resume handling through direct register manipulation. The current approach uses explicit read-modify-write sequences to control the MEMORY enable bit in the PCI_COMMAND register, declaring local variables for temporary storage. Replace manual bit manipulation with dw_pcie_*_dword() during suspend and resume operations. This eliminates redundant variable declarations and simplifies the power management flow by handling bit operations within a single function call. Using the centralized helper improves code readability and aligns the driver with standard DesignWare register access patterns. The change also reduces the risk of bit manipulation errors in future modifications to the power management logic. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-dra7xx.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controll= er/dwc/pci-dra7xx.c index f97f5266d196..44fbd6751004 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -867,15 +867,12 @@ static int dra7xx_pcie_suspend(struct device *dev) { struct dra7xx_pcie *dra7xx =3D dev_get_drvdata(dev); struct dw_pcie *pci =3D dra7xx->pci; - u32 val; =20 if (dra7xx->mode !=3D DW_PCIE_RC_TYPE) return 0; =20 /* clear MSE */ - val =3D dw_pcie_readl_dbi(pci, PCI_COMMAND); - val &=3D ~PCI_COMMAND_MEMORY; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_clear_dword(pci, PCI_COMMAND, PCI_COMMAND_MEMORY); =20 return 0; } @@ -884,15 +881,12 @@ static int dra7xx_pcie_resume(struct device *dev) { struct dra7xx_pcie *dra7xx =3D dev_get_drvdata(dev); struct dw_pcie *pci =3D dra7xx->pci; - u32 val; =20 if (dra7xx->mode !=3D DW_PCIE_RC_TYPE) return 0; =20 /* set MSE */ - val =3D dw_pcie_readl_dbi(pci, PCI_COMMAND); - val |=3D PCI_COMMAND_MEMORY; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_set_dword(pci, PCI_COMMAND, PCI_COMMAND_MEMORY); =20 return 0; } --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D21192264A0; Thu, 28 Aug 2025 14:00:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389659; cv=none; b=ZxoHCcGDORLAvEmpghwSS+ixUCLJhVDzDcXMiqZU0cU9KflN5hT/IPIO0W5WkRmfoJs5czJTzc09rkMegYWAue5DkKSCRoObnWTU4OOxLBed6kaXl98CoWcUZJGQqSJL8Wk0p9SV3xBOiqQa4Pcp9RGN54ZH5rSI62CKJfurBbo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389659; c=relaxed/simple; bh=NzORvNhArs52OIES8vr4Q74uil4ev0AQJ1LMAaOqlCA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BkKIaO4o1wz1Bx2cLYPD/ZIoWJgCZUdxlxrma0LYjgWEe2gyfu3FYOhmFWfAzPYLlqYEmVjuP8k4YS+aPCzuJIzRJUfvRzCUU9n8PyvkZc2fdrd9dnUx4DVB9rG1iF81iV3LUkLj3SHVJrHdQy30pYVW02gcYKkltDewu4yBrdI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=PrYm4eZB; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="PrYm4eZB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Vx oG6OIzDAF+arc2fFT/fW9m8cN4HqpezvjjmB/kNYY=; b=PrYm4eZBq6l6x2wp0J 6LAtHF1+Sl+vJvy89+PdwCFH2xYrJ0EDJnwZ3vrKSVNiTlV5hk7RBWTZFyKfM0UF tmFEHFBuGcsiTH1CYCno/Ut+eWDocUk+TOHdGHuANlguChPg3weNlVGVuIXd1q2p lziCIg5t2NaV/2j9uKzurikAA= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgAXBtYDYbBoN0ahAw--.5480S6; Thu, 28 Aug 2025 22:00:39 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com>, Frank Li Subject: [PATCH v5 04/13] PCI: imx6: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:42 +0800 Message-Id: <20250828135951.758100-5-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgAXBtYDYbBoN0ahAw--.5480S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxJw4UCFyxtw18XF48Xr1fZwb_yoWrGFW5pa y2vrnayF4xJF4ruw4vyas5XF13t3Z3CF1DGanrKwnaqFy2yry7tayjy343tF4xGF4jyryj 9w1UJr43J3WYyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pinmR8UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQwS3o2iwWuaXpgAAsG Content-Type: text/plain; charset="utf-8" i.MX6 PCIe driver contains multiple read-modify-write sequences for link training and speed configuration. These operations manually handle bit masking and shifting to update specific fields in control registers, particularly for link capabilities and speed change initiation. Refactor link capability configuration and speed change handling using dw_pcie_*_dword(). The helper simplifies LNKCAP modification by encapsulating bit clear/set operations and eliminates intermediate variables. For speed change control, replace explicit bit manipulation with direct register updates through the helper. Adopting the standard interface reduces code complexity in link training paths and ensures consistent handling of speed-related bits. The change also prepares the driver for future enhancements to Gen3 link training by centralizing bit manipulation logic. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 80e48746bbaf..acd8e1b927c5 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -939,7 +939,6 @@ static int imx_pcie_start_link(struct dw_pcie *pci) struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); struct device *dev =3D pci->dev; u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u32 tmp; int ret; =20 if (!(imx_pcie->drvdata->flags & @@ -954,10 +953,9 @@ static int imx_pcie_start_link(struct dw_pcie *pci) * bus will not be detected at all. This happens with PCIe switches. */ dw_pcie_dbi_ro_wr_en(pci); - tmp =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - tmp &=3D ~PCI_EXP_LNKCAP_SLS; - tmp |=3D PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_SLS, + PCI_EXP_LNKCAP_SLS_2_5GB); dw_pcie_dbi_ro_wr_dis(pci); =20 /* Start LTSSM. */ @@ -970,18 +968,16 @@ static int imx_pcie_start_link(struct dw_pcie *pci) =20 /* Allow faster modes after the link is up */ dw_pcie_dbi_ro_wr_en(pci); - tmp =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - tmp &=3D ~PCI_EXP_LNKCAP_SLS; - tmp |=3D pci->max_link_speed; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_SLS, + pci->max_link_speed); =20 /* * Start Directed Speed Change so the best possible * speed both link partners support can be negotiated. */ - tmp =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - tmp |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); + dw_pcie_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_SPEED_CHANGE); dw_pcie_dbi_ro_wr_dis(pci); =20 ret =3D imx_pcie_wait_for_speed_change(imx_pcie); @@ -1302,7 +1298,6 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp= *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); - u32 val; =20 if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_8GT_ECN_ERR051586) { /* @@ -1317,9 +1312,8 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp= *pp) * to 0. */ dw_pcie_dbi_ro_wr_en(pci); - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL); dw_pcie_dbi_ro_wr_dis(pci); } } --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A997913C8E8; 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charset="utf-8" Meson PCIe driver implements payload size configuration through manual register manipulation. The current code reads device control registers, modifies specific bitfields for maximum payload and read request sizes, then writes back the updated values. This pattern repeats twice with similar logic but different bit masks. Replace explicit bit manipulation with dw_pcie_*_dword() for payload and read request size configuration. The helper consolidates read-clear-set-write operations into a single call, eliminating redundant register read operations and local variable usage. This refactoring reduces code duplication in size configuration logic and improves maintainability. By using the DesignWare helper, the driver aligns with standard PCIe controller programming patterns and simplifies future updates to device capability settings. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-meson.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controlle= r/dwc/pci-meson.c index 787469d1b396..e9375cfa6c8f 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -264,33 +264,27 @@ static int meson_size_to_payload(struct meson_pcie *m= p, int size) static void meson_set_max_payload(struct meson_pcie *mp, int size) { struct dw_pcie *pci =3D &mp->pci; - u32 val; u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int max_payload_size =3D meson_size_to_payload(mp, size); =20 - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val &=3D ~PCI_EXP_DEVCTL_PAYLOAD; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); + dw_pcie_clear_dword(pci, offset + PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_PAYLOAD); =20 - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val |=3D PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); + dw_pcie_set_dword(pci, offset + PCI_EXP_DEVCTL, + PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size)); } =20 static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) { struct dw_pcie *pci =3D &mp->pci; - u32 val; u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int max_rd_req_size =3D meson_size_to_payload(mp, size); =20 - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val &=3D ~PCI_EXP_DEVCTL_READRQ; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); + dw_pcie_clear_dword(pci, offset + PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_READRQ); =20 - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val |=3D PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); + dw_pcie_set_dword(pci, offset + PCI_EXP_DEVCTL, + PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size)); } =20 static int meson_pcie_start_link(struct dw_pcie *pci) --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B7C8223D298; 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arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="TrgOd+he" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Zy 0wvfRRI0LApPMuYe3zBdc3lkExdk1jM0KvRsbczRc=; b=TrgOd+hesp03+lMqYf lNgMRGE4PIW8ZG9UAcCiCMFnbtc4ooK9iVlmuSFK66NcgTVyXTX1r6nIO2xpykOi dtKHz0gd66pT+n9cjsim9vuVZUhN6Zw3biEssDyqMYBmDnXXthmC6yoccpewGnU+ dL39q/Z/XWWfOYaurQAvaV924= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgAXBtYDYbBoN0ahAw--.5480S8; Thu, 28 Aug 2025 22:00:41 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 06/13] PCI: armada8k: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:44 +0800 Message-Id: <20250828135951.758100-7-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgAXBtYDYbBoN0ahAw--.5480S8 X-Coremail-Antispam: 1Uf129KBjvJXoWxZFyrKFykJF1xKF1kCw48JFb_yoWrCFy3p3 s8AFyYyF1UJw48Z3ykCas7XFy3AFZxZFnxCan3Wr1vv3ZrCrZrW3yFvFySgr1SgFsFqrWY vw4rtry7Cr1rG3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pE-eOtUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQxe3o2iwWuaXtAABsG Content-Type: text/plain; charset="utf-8" Armada8k PCIe driver uses explicit bitwise operations for global control register configuration. The driver manually handles bit masking and shifting for multiple fields including device type, domain attributes, and interrupt masking. This approach requires repetitive read-modify-write sequences and temporary variables. Refactor global control setup, domain attribute configuration, and interrupt masking using dw_pcie_*_dword(). The helper replaces manual bit manipulation with declarative bit masks, directly specifying which bits to clear and set. This eliminates intermediate variables and reduces code complexity. Standardizing on the helper improves code clarity in initialization paths and ensures consistent handling of control register bits. The change also centralizes bit manipulation logic, reducing the risk of errors in future modifications to device configuration. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-armada8k.c | 43 ++++++++-------------- 1 file changed, 16 insertions(+), 27 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/contr= oller/dwc/pcie-armada8k.c index c2650fd0d458..1b2879f89c61 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -155,54 +155,43 @@ static bool armada8k_pcie_link_up(struct dw_pcie *pci) =20 static int armada8k_pcie_start_link(struct dw_pcie *pci) { - u32 reg; - /* Start LTSSM */ - reg =3D dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg |=3D PCIE_APP_LTSSM_EN; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_set_dword(pci, PCIE_GLOBAL_CONTROL_REG, PCIE_APP_LTSSM_EN); =20 return 0; } =20 static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) { - u32 reg; struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); =20 - if (!dw_pcie_link_up(pci)) { + if (!dw_pcie_link_up(pci)) /* Disable LTSSM state machine to enable configuration */ - reg =3D dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &=3D ~(PCIE_APP_LTSSM_EN); - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); - } + dw_pcie_clear_dword(pci, PCIE_GLOBAL_CONTROL_REG, + PCIE_APP_LTSSM_EN); =20 /* Set the device to root complex mode */ - reg =3D dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &=3D ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); - reg |=3D PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_clear_and_set_dword(pci, PCIE_GLOBAL_CONTROL_REG, + PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT, + PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT); =20 /* Set the PCIe master AxCache attributes */ dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); =20 /* Set the PCIe master AxDomain attributes */ - reg =3D dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); - reg &=3D ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); - reg |=3D DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); + dw_pcie_clear_and_set_dword(pci, PCIE_ARUSER_REG, + AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT, + DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT); =20 - reg =3D dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); - reg &=3D ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); - reg |=3D DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); + dw_pcie_clear_and_set_dword(pci, PCIE_AWUSER_REG, + AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT, + DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT); =20 /* Enable INT A-D interrupts */ - reg =3D dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); - reg |=3D PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | - PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); + dw_pcie_set_dword(pci, PCIE_GLOBAL_INT_MASK1_REG, + PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | + PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK); =20 return 0; } --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 42F251E51EA; Thu, 28 Aug 2025 14:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389661; cv=none; b=AyNfKqDH099ol9lRPvo2X/fkKykGjV6HHEN+JIQDhkvyPrSVWxxMqtlaOQK3zAKLI+wEyY7hQWYqe98R5D8P80vHvdzPzD2Rf5zDhIW856ciYdSo1p6AXAYKWShc7yRndupz+MvDQVmwTd4HVOA52fTPAy5xBY2mwe09kpJWnEA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389661; c=relaxed/simple; bh=0h/uAYXPWTodmK77bhv0kKWuNaJgts8GLgBTCzBTLOs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dbcTsF4LBPNqjAz3feqiQ/V5xJ31G20TGZN6hjMedwmcZTYNXJNvaEblH7py1OysozEtZhtZ/BSoZH7LrRa0jHQvxgSWgRpv5sFysilIOVzlGMRqqUlmICB/h+XDIY5VSG/CJ8EJ6MXM/pCewwuLyzKJj839OfiiyNRwLMJZi04= ARC-Authentication-Results: i=1; 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Thu, 28 Aug 2025 22:00:42 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 07/13] PCI: bt1: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:45 +0800 Message-Id: <20250828135951.758100-8-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgAXBtYDYbBoN0ahAw--.5480S9 X-Coremail-Antispam: 1Uf129KBjvJXoW7Zry8Xw4xCFy5Cw4DuFWDtwb_yoW8Ar4Upa 9IkF92kF1Iya15ua1jy3Z7uFy5Wan5Ca4jgrnFgw1IgF9Iyr9rWryrKFyYvrZxJr4Iqr1j 9w1UtFW7AanxZrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pinmR8UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwi3o2iwWlmkrgAAsW Content-Type: text/plain; charset="utf-8" Baikal-T1 PCIe driver contains a direct register write to initiate speed change during link training. The current implementation sets the PORT_LOGIC_SPEED_CHANGE bit via read-modify-write without using the standard bit manipulation helper. Replace manual bit set operation with dw_pcie_*_dword() to enable speed change. The helper clearly expresses the intent to modify a specific bit while preserving others, eliminating the need for explicit read-before-write. Using the standardized interface improves consistency with other DesignWare drivers and reduces the risk of unintended bit modifications. The change also simplifies future updates to link training logic. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-bt1.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-bt1.c b/drivers/pci/controller= /dwc/pcie-bt1.c index 1340edc18d12..0a9466827e2b 100644 --- a/drivers/pci/controller/dwc/pcie-bt1.c +++ b/drivers/pci/controller/dwc/pcie-bt1.c @@ -289,9 +289,8 @@ static int bt1_pcie_start_link(struct dw_pcie *pci) * attempt to reach a higher bus performance (up to Gen.3 - 8.0 GT/s). * This is required at least to get 8.0 GT/s speed. */ - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_SPEED_CHANGE); =20 ret =3D regmap_read_poll_timeout(btpci->sys_regs, BT1_CCU_PCIE_PMSC, val, BT1_CCU_PCIE_LTSSM_LINKUP(val), --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4EE4F22A4DB; Thu, 28 Aug 2025 14:00:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389660; cv=none; b=TyzZ2d+0fhwqavonX4PQqkhAInxHYMegfJPRUh5aGIlhrfMAPA8xjen6tjaXkNPoGZT7uZUVCyqCdV4SZqLgUapboUxNDh4O8hfMJ3XBDtjEGvgVYmZbA5Z0PwCKUgG36QVVUSgetge0ooJLkAyHVn+in6inTd+i9F6OlJokvq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389660; c=relaxed/simple; bh=uKX3u+7TAuRUgEMD94/9A98zZk0ula4Uf+ogFZSQO+s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SzBnJwDUgVejr8YVRj77ILE7zhDdztPMbxcqYzE0WtSPPBVOT8y9NZ2zP73iFVIIw8AEXidGjiPTrrlHfT77lAXZYJk8BaTO+FqWlm7BTLpJkN2VRo9Uim1fcOGOP8Gc0xbzH6KtWXCbUwN3L8vQ9qtmF5kZJIykKv/kfS7o3KA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=hqa9/Mk0; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="hqa9/Mk0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=St 4Y96243DO+FdBkAHidwX6lVuq6DmFHeHuVh5cyFz4=; b=hqa9/Mk0kVSxF+Iqf6 jU1kBpG9Ip97CKYJ8580ZDDHeNvL1POj5+X3bzZ2LPX9g/Q1mKf223rV4Hk+MqZZ 1SdRSluVoOE/DrBMnxwJQBjFmxUcZqACS2igBN/ucGo/P/eeP+EN2VgNSUilCzq6 8I4uJmtAH3mnSLesN1orQNaFM= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wAXJYwNYbBoRejWEw--.829S2; Thu, 28 Aug 2025 22:00:46 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 08/13] PCI: dw-rockchip: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:46 +0800 Message-Id: <20250828135951.758100-9-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAXJYwNYbBoRejWEw--.829S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7tw1rGr4Dtr1DJF1ruw18Grg_yoW8Cr1Dpa 9xAa4ayF4fJw4rua1DAa97ZFy5ta9xAFW7Jr9xGw1SqFy2k34DJ3WYkFy3tF1xGr42vF1Y 93yUt34UAF43AFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piKhFxUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxa3o2iwWlmlJwAAsA Content-Type: text/plain; charset="utf-8" Rockchip PCIe driver implements L0s capability enablement through explicit register read-modify-write. The current approach reads the LNKCAP register, modifies the ASPM_L0S bit, then writes back the value with DBI write protection handling. Refactor ASPM capability configuration using dw_pcie_*_dword(). The helper combines bit manipulation with DBI protection in a single call, replacing three-step manual operations. This simplifies the capability setup flow and reduces code complexity. Adopting the standard helper improves maintainability by eliminating local variables and explicit bitwise operations. The change also ensures consistent handling of DBI write protection across capability modification functions. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index b5f5eee5a50e..5ae923907531 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -196,15 +196,14 @@ static bool rockchip_pcie_link_up(struct dw_pcie *pci) =20 static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) { - u32 cap, lnkcap; + u32 cap; =20 /* Enable L0S capability for all SoCs */ cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); if (cap) { - lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); - lnkcap |=3D PCI_EXP_LNKCAP_ASPM_L0S; dw_pcie_dbi_ro_wr_en(pci); - dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); + dw_pcie_set_dword(pci, cap + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_ASPM_L0S); dw_pcie_dbi_ro_wr_dis(pci); } } --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4966622A4EB; Thu, 28 Aug 2025 14:00:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389660; cv=none; b=to1X+3XsDy5fHOQjzyJebhfjyhOiC+1BpgOYS1JalLOjdjBqUawa0GnAsOwgXFEWieOemX3hw6ZVtKzlcO27GAWg8XZiWUNzUjxk7vg9Ulriz1tYzAUoNfAhbjyYVxxxPMxLonCOVNBTdRGDvllFopIfq+CR1LGEwzZtnjH4qE4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389660; c=relaxed/simple; bh=cHDdqhva+6AIS0Y/Y6XwJUtXSPl0BO1JBvPsunU1LZU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lOShe2KoJiFVfCSbB9crB6wqJm8P9satMPp+uVhBwS8wVESnmb8LUGdyDnb7iiwIMdgbjxXlwFRbO5mJirU0NP2d90CM1huCmWA1qFTwNIO8YgvrCpDa157Uc4q7LQS6tIoiGKaQPJACG9WNXdVxem8Ee7al/2adYxotbsmyeyM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=IdmHwC/n; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="IdmHwC/n" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=KN 7TgaWF2kajUdYvrzUZkDw3BqSOqVca4BrK8wbWfaY=; b=IdmHwC/nh8hvGFOOSF oU5OOdNn30OFvEAGIrq43kTb5HXzo3Jii/4BPWOguNdDKGN58qNhR423l3BEySon qMFlCGdjzo9vqoOaHlE9APrbgl6Rcl+joBHM0uTz5GYke5bsdnb0+OEV+5bHRrRI /rOWbjpWSqSFTL/kdg5htvT30= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wAXJYwNYbBoRejWEw--.829S3; Thu, 28 Aug 2025 22:00:46 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 09/13] PCI: fu740: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:47 +0800 Message-Id: <20250828135951.758100-10-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAXJYwNYbBoRejWEw--.829S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7tF1DGrWDuryrAw1rWryUWrg_yoW8Wr48pa y2yrWrCF1Uta1rZa18A3WkZF1Yga93AFWUWan7Wwn29F9FyrWkWrWFqa4aqFyxGF4Iqr1a kw1Utay7X3WayFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pK9av_UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhC3o2iwWw2UmwAAs- Content-Type: text/plain; charset="utf-8" SiFive FU740 PCIe driver uses direct register write to initiate link speed change after setting target link capabilities. The current implementation sets PORT_LOGIC_SPEED_CHANGE bit via explicit read-modify-write sequence. Replace manual bit manipulation with dw_pcie_*_dword() for speed change initiation. The helper encapsulates read-modify-write operations while providing clear intent through "clear 0, set BIT" usage. This refactoring aligns the driver with standard DesignWare programming patterns and reduces code complexity. The change also ensures consistent handling of speed change initiation across all DesignWare base controllers. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-fu740.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controll= er/dwc/pcie-fu740.c index 66367252032b..5bb19da9e2b2 100644 --- a/drivers/pci/controller/dwc/pcie-fu740.c +++ b/drivers/pci/controller/dwc/pcie-fu740.c @@ -216,9 +216,8 @@ static int fu740_pcie_start_link(struct dw_pcie *pci) tmp |=3D orig; dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp); =20 - tmp =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - tmp |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); + dw_pcie_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_SPEED_CHANGE); =20 ret =3D dw_pcie_wait_for_link(pci); if (ret) { --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DBF49314A8B; Thu, 28 Aug 2025 14:01:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389668; cv=none; b=hS5xz+LY+T8hYdtMtD8qAju/AzDKAjGFJVUw6cOQN7Iwct0HX8MCdZGxdZ6flLBOuk/2Bwkv9oOZzizQE8W++Eiju0TlrRqBBsQ6XVaGkcEKMKEtnpX7EV/O7zXSno3d2ihCsSbZe90hIglOD7cHsr2/G8BxQJjocLpvT2wHcyY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389668; c=relaxed/simple; bh=uN0drnFLGHFFBfcUuEdBDC/ZBct1KNpo6/5Kpg9dR1s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Wd9X0t4d8+Vq8nHMUD89om4FNXYUYO55Kn7DUvEch9XC/jT9jc/mNpb8ehDJyQ29LgixRCFbfYedpgTKtNOk01vgF8lVHiD6EI4UxobmnZL1lrI2RKvlvv+RLtaVpydcSli9WqO7Ltyj46hYxyO5REXFv1CmXsoQd5oop/lYsyo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=j+rmkRlA; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="j+rmkRlA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=rK I7JtXjLg6JBO5xGv23pxIRhfzGIHc5RWwBJJ2bE6I=; b=j+rmkRlAe1vnPkEZ2F xgv0sNczJSpd/rmBpSAv/8JJ7fTKYPETyMmPKo+WgSbvlsVYkbuMCwiUbFFn1bc6 yfztIOXmaedic5fu3RUsKJgyKi/o2h4P/qXnG86EwDTrceAVvj87oYnIQXgNB5wH k33K3id1vzNu0wXorA7gcWSaU= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wAXJYwNYbBoRejWEw--.829S4; Thu, 28 Aug 2025 22:00:47 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 10/13] PCI: qcom: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:48 +0800 Message-Id: <20250828135951.758100-11-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAXJYwNYbBoRejWEw--.829S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxAryrXFyxtFWfKF1fJrW8JFb_yoW7JF1Upw 1Ikwn7JFn7AF409r98Aa1DWr1FkFWkur42k3W3tanF93Z7AF9Fga98t3ZxKF1xJFWIqFy5 G3yUAFW7GF1akrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zNjg48UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQwy3o2iwWuaYfQAAsa Content-Type: text/plain; charset="utf-8" Qcom PCIe common code contains complex bit manipulation for 16GT/s equalization and lane margining configuration. These functions use multiple read-modify-write sequences with manual bit masking and field preparation, leading to verbose and error-prone code. Refactor equalization and lane margining setup using dw_pcie_*_dword(). The helper simplifies multi-field configuration by combining clear and set operations in a single call. Initialize local variables to zero before field insertion to ensure unused bits are cleared appropriately. This change reduces code complexity by ~40% in affected functions while improving readability. Centralizing bit manipulation ensures consistent handling of register fields across Qcom PCIe implementations and provides a solid foundation for future 16GT/s enhancements. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-qcom-common.c | 62 +++++++++---------- 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/co= ntroller/dwc/pcie-qcom-common.c index 3aad19b56da8..f3a365daac8a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.c +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c @@ -19,30 +19,29 @@ void qcom_pcie_common_set_16gt_equalization(struct dw_p= cie *pci) * determines the data rate for which these equalization settings are * applied. */ - reg =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - reg &=3D ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - reg &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - reg |=3D FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, - GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT); - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); + reg =3D FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, + GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT); + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL | + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, + reg); =20 - reg =3D dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); - reg &=3D ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | - GEN3_EQ_FMDC_N_EVALS | - GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | - GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); - reg |=3D FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | - FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | - FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | - FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); - dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); + reg =3D FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | + FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); + dw_pcie_clear_and_set_dword(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, + GEN3_EQ_FMDC_T_MIN_PHASE23 | + GEN3_EQ_FMDC_N_EVALS | + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, + reg); =20 - reg =3D dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); - reg &=3D ~(GEN3_EQ_CONTROL_OFF_FB_MODE | - GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | - GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | - GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); + dw_pcie_clear_dword(pci, GEN3_EQ_CONTROL_OFF, + GEN3_EQ_CONTROL_OFF_FB_MODE | + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); } EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization); =20 @@ -50,16 +49,15 @@ void qcom_pcie_common_set_16gt_lane_margining(struct dw= _pcie *pci) { u32 reg; =20 - reg =3D dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF); - reg &=3D ~(MARGINING_MAX_VOLTAGE_OFFSET | - MARGINING_NUM_VOLTAGE_STEPS | - MARGINING_MAX_TIMING_OFFSET | - MARGINING_NUM_TIMING_STEPS); - reg |=3D FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) | - FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) | - FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) | - FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10); - dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg); + reg =3D FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) | + FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) | + FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) | + FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10); + dw_pcie_clear_and_set_dword(pci, GEN4_LANE_MARGINING_1_OFF, + MARGINING_MAX_VOLTAGE_OFFSET | + MARGINING_NUM_VOLTAGE_STEPS | + MARGINING_MAX_TIMING_OFFSET | + MARGINING_NUM_TIMING_STEPS, reg); =20 reg =3D dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF); reg |=3D MARGINING_IND_ERROR_SAMPLER | --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 28CC722F386; Thu, 28 Aug 2025 14:00:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389662; cv=none; b=rhV0wjfuQ2CxcgkV5b5lDREtQie8gyDEqJev3+ZaLmKINpJSmugyONk8QoUqO09zKguut+XrXdeALM6/HoM4g5Yz4dFTEzBedTOdILeHmwPUBK1YSrU6pfL5jh7txq5y6yBCPyK8tC6LjGLbYCxAt13PMT8cKTiwKmGUkVNjLpI= ARC-Message-Signature: i=1; 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d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=6R oicKHemQL4qB4DOeBZeDg8XqBSHJedP0pmE3ET/74=; b=mM+ZKc+WnavRvuXZnX 4zD+qtdjqvGnF1TTiYc25VRFd8gV+gZSMKGeDzZ3Qi7fEF3zToML9Oec15UuvMdW PQtn2bR85UraUfpMEQsyHo7NNxsri/TTf/Jnrw2M7BU6QKkrUKbr08xiALZXlA8j /EFvUSjyr/jp4EyRGHiGhHyPQ= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wAXJYwNYbBoRejWEw--.829S5; Thu, 28 Aug 2025 22:00:48 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 11/13] PCI: qcom-ep: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:49 +0800 Message-Id: <20250828135951.758100-12-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAXJYwNYbBoRejWEw--.829S5 X-Coremail-Antispam: 1Uf129KBjvJXoW7WF17Kr17ZF1UGr4rtrWUArb_yoW8tw4Dpr 9xXrn0kF1xJr4rur4vka1kZF15JFnxAFy3JFWDKw1avFy7CF9rtas0ya4aqFn7GrW2qr1j 9w1YqayrW3WYyFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zR0ks9UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxS3o2iwWlmlWgAAs- Content-Type: text/plain; charset="utf-8" Qcom PCIe endpoint driver implements L0s/L1 latency configuration through manual register manipulation. The current approach reads LNKCAP register, modifies specific latency fields, then writes back the value. This pattern repeats twice with similar logic but different bit masks. Replace explicit latency configuration with dw_pcie_*_dword(). The helper combines field clearing and setting in a single operation, replacing three-step manual sequences. Initialize the set value with FIELD_PREP() to clearly express the intended bitfield value. This refactoring reduces code duplication in latency configuration paths and improves maintainability. Using the standard helper ensures consistent handling of capability registers and simplifies future updates to ASPM settings. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index bf7c6ac0f3e3..c2b4f172385d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -475,17 +475,15 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *p= ci) =20 /* Set the L0s Exit Latency to 2us-4us =3D 0x6 */ offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - val &=3D ~PCI_EXP_LNKCAP_L0SEL; - val |=3D FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_L0SEL, + FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6)); =20 /* Set the L1 Exit Latency to be 32us-64 us =3D 0x6 */ offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - val &=3D ~PCI_EXP_LNKCAP_L1EL; - val |=3D FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_L1EL, + FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6)); =20 dw_pcie_dbi_ro_wr_dis(pci); =20 --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0F7623128C2; Thu, 28 Aug 2025 14:01:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389664; cv=none; b=nI8scv9toAuw7ECr7WWN+G/gm/+E+DHkvN+xwKwt+1nX2PxJJry6n+OjqkGj/sO+46602qTOOGKu9eJtgfL9dczeE9rrh6i07Q2Q/jsIx9MInBb6u7qwXPpTKMy0g3/8l3TN4xVoDvoFHcqWFdrcUvI4lVqLDmiS+oF3RtITduQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389664; c=relaxed/simple; bh=I3kiFpN5hU0JGnnLGtkwKKvrN2TxdKRl9JuJaqgpYUg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YtFBKBJoDTrtcNUXFBBcaoHExreUBd9cLiqIh/pj/LNHw+DEwQ8vfsN5YxUuDHhI+d/UcHH2AHmpY0SwCHtcWjkfx/X3zPYOJKWwYUbLosQKoWXwzEJqDpHQKXPVelVRuKBeTklIYhFp9eWuYT9GBsAOA/taX+SjqD8x4Uc27B4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=M9WTGrxI; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="M9WTGrxI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=rX r25upQbRLDCWYow996mEZMVoZsxtYisTv8mNbEQJU=; b=M9WTGrxIpDtIC56lLr 8OOh7yDVJcvX67JQfyHknBDnNe7EM5ZBTFfIYB0flvmWMhLjyC17vaNJbkqO9bG/ fcDufU0i0M03Vhxnv5aXt2OujaDrYUx8hdKRGeMSbFiRNPK68ooxp49vPZdF/1jG jSY4H8AgLC+Oe7UUMlIFiPTj8= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wAXJYwNYbBoRejWEw--.829S6; Thu, 28 Aug 2025 22:00:48 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 12/13] PCI: rcar-gen4: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:50 +0800 Message-Id: <20250828135951.758100-13-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAXJYwNYbBoRejWEw--.829S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxWFy3GFyxGr47Xw1xZw4rAFb_yoW5AFW3pa y7CFySkF1UAw4Y9F4jqaykWr15uan3C3Wjgwn7Gw1I9ay7ArW3X3y0y347tFWxGrs2qr45 Cw1UtFWUuF15ZFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pinmR8UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQw63o2iwWuaYpAAAsB Content-Type: text/plain; charset="utf-8" R-Car Gen4 PCIe driver contains multiple read-modify-write sequences for speed change control and lane configuration. The driver manually handles speed change initiation through bit set/clear operations and configures lane skew with explicit bit masking. Refactor speed change handling and lane skew configuration using dw_pcie_*_dword(). For speed change operations, replace manual bit toggling with clear-and-set sequences. For lane skew, use the helper to conditionally set bits based on lane count. Adopting the standard interface simplifies link training logic and reduces code complexity. The change also ensures consistent handling of control register bits and provides better documentation of intent through declarative bit masks. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 23 ++++++++------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 18055807a4f5..67be0aeaa7ec 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -107,13 +107,11 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie= *dw) u32 val; int i; =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); - val &=3D ~PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_clear_dword(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_SPEED_CHANGE); =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_set_dword(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_SPEED_CHANGE); =20 for (i =3D 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) { val =3D dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); @@ -565,11 +563,9 @@ static void rcar_gen4_pcie_additional_common_init(stru= ct rcar_gen4_pcie *rcar) struct dw_pcie *dw =3D &rcar->dw; u32 val; =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); - val &=3D ~PORT_LANE_SKEW_INSERT_MASK; - if (dw->num_lanes < 4) - val |=3D BIT(6); - dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); + dw_pcie_clear_and_set_dword(dw, PCIE_PORT_LANE_SKEW, + PORT_LANE_SKEW_INSERT_MASK, + (dw->num_lanes < 4) ? BIT(6) : 0); =20 val =3D readl(rcar->base + PCIEPWRMNGCTRL); val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN; @@ -680,9 +676,8 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen= 4_pcie *rcar, bool enable return 0; } =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_FORCE); - val |=3D PORT_FORCE_DO_DESKEW_FOR_SRIS; - dw_pcie_writel_dbi(dw, PCIE_PORT_FORCE, val); + dw_pcie_set_dword(dw, PCIE_PORT_FORCE, + PORT_FORCE_DO_DESKEW_FOR_SRIS); =20 val =3D readl(rcar->base + PCIEMSR0); val |=3D APP_SRIS_MODE; --=20 2.49.0 From nobody Tue Dec 16 07:31:45 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DE1A0314B6D; Thu, 28 Aug 2025 14:01:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389669; cv=none; b=h7CGXaUAKCsemnOiRqe09oNk/EQvzExwdk3q84TgbXgpw1RkU2wpVQ26Vb486CcoP0gmWZe/0Crx/tQ7Sqz3+S5Q6D8un1OuM2nkdDBJ7IbbTvjkKHX7+F/wEDga0li12NCCbNTHMmh2E67tGKIacANR+SJ3PkVTGyf15Iz0EWs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389669; c=relaxed/simple; bh=0HdXn0oWPQJLvm3LmIBrLtXwSSURIQZmY51cwVRT7JI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IR3KQOYBf/2rf+K7LZh6dffPDSYWreiEO060hdmyzi/RVq6GPhYE4Q5I7Fhsy5ao/jTLBdeer5yGuYtv62ejLVXBsfW1jDeMi1mdRR4eXw+QydOwVpbOJFqhAcWAniMP5MS8zQL0Rmo1UhfeFm+3m9Vx5+Zuy5UJrGdUIrkTW8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=gYk6nLn8; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="gYk6nLn8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Fn imcfeSmrx4hkmRg5SDhYi4VffXu8gWahR80/T54CQ=; b=gYk6nLn8N4ziDubYIv ZjUGd6XANFq2U/BzQ0PcxYNu0xrHEvefQmAO6sPk1AYmFh4VKMth+NjXBKCejRT2 MANYa8WiZbpXoUKJc/IMsYmDWLklqgxD7/2V67Bi5Th06JVr3i3V1U3JDgv3s6t8 WPDHZEpuUqysGpCYvBn5o2ey0= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wAXJYwNYbBoRejWEw--.829S7; Thu, 28 Aug 2025 22:00:49 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 13/13] PCI: tegra194: Refactor code by using dw_pcie_*_dword() Date: Thu, 28 Aug 2025 21:59:51 +0800 Message-Id: <20250828135951.758100-14-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250828135951.758100-1-18255117159@163.com> References: <20250828135951.758100-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAXJYwNYbBoRejWEw--.829S7 X-Coremail-Antispam: 1Uf129KBjvJXoW3ur47Xw15Gr1xXrWUKryfWFg_yoWDCF4xpF 1jy3sYyF1UJF1vvrZFya4kXF1YkrZI9r47WanxKrnava1kAry7XayvvasFqFn7GFWxtFW5 Kw40yFy7CFy5XrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pinmR8UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhu3o2iwWw2U9gAAsZ Content-Type: text/plain; charset="utf-8" Tegra194 PCIe driver contains extensive manual bit manipulation across interrupt handling, ASPM configuration, and controller initialization. The driver implements complex read-modify-write sequences with explicit bit masking, leading to verbose and hard-to-maintain code. Refactor interrupt handling, ASPM setup, capability configuration, and controller initialization using dw_pcie_*_dword(). Replace multi-step register modifications with single helper calls, eliminating intermediate variables and reducing code size by ~75 lines. For CDMA error handling, initialize the value variable to zero before setting status bits. This comprehensive refactoring significantly improves code readability and maintainability. Standardizing on the helper ensures consistent register access patterns across all driver components and reduces the risk of bit manipulation errors in this complex controller driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-tegra194.c | 122 ++++++++------------- 1 file changed, 47 insertions(+), 75 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 4f26086f25da..f89dde9071cd 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -378,9 +378,8 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, v= oid *arg) val |=3D APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; appl_writel(pcie, val, APPL_CAR_RESET_OVRD); =20 - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_SPEED_CHANGE); } } =20 @@ -610,20 +609,14 @@ static struct pci_ops tegra_pci_ops =3D { #if defined(CONFIG_PCIEASPM) static void disable_aspm_l11(struct tegra_pcie_dw *pcie) { - u32 val; - - val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); - val &=3D ~PCI_L1SS_CAP_ASPM_L1_1; - dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); + dw_pcie_clear_dword(&pcie->pci, pcie->cfg_link_cap_l1sub, + PCI_L1SS_CAP_ASPM_L1_1); } =20 static void disable_aspm_l12(struct tegra_pcie_dw *pcie) { - u32 val; - - val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); - val &=3D ~PCI_L1SS_CAP_ASPM_L1_2; - dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); + dw_pcie_clear_dword(&pcie->pci, pcie->cfg_link_cap_l1sub, + PCI_L1SS_CAP_ASPM_L1_2); } =20 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event) @@ -697,18 +690,18 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); =20 /* Program T_cmrt and T_pwr_on values */ - val =3D dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); - val &=3D ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE); - val |=3D (pcie->aspm_cmrt << 8); + val =3D (pcie->aspm_cmrt << 8); val |=3D (pcie->aspm_pwr_on_t << 19); - dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); + dw_pcie_clear_and_set_dword(pci, pcie->cfg_link_cap_l1sub, + PCI_L1SS_CAP_CM_RESTORE_TIME | + PCI_L1SS_CAP_P_PWR_ON_VALUE, + val); =20 /* Program L0s and L1 entrance latencies */ - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); - val &=3D ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; - val |=3D (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); + val =3D (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); val |=3D PORT_AFR_ENTER_ASPM; - dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_AFR, + PORT_AFR_L0S_ENTRANCE_LAT_MASK, val); } =20 static void init_debugfs(struct tegra_pcie_dw *pcie) @@ -860,9 +853,8 @@ static void config_gen3_gen4_eq_presets(struct tegra_pc= ie_dw *pcie) dw_pcie_writeb_dbi(pci, offset + i, val); } =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK); =20 val =3D dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); val &=3D ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC; @@ -870,10 +862,9 @@ static void config_gen3_gen4_eq_presets(struct tegra_p= cie_dw *pcie) val &=3D ~GEN3_EQ_CONTROL_OFF_FB_MODE; dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - val |=3D (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, + 0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); =20 val =3D dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); val &=3D ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC; @@ -882,17 +873,14 @@ static void config_gen3_gen4_eq_presets(struct tegra_= pcie_dw *pcie) val &=3D ~GEN3_EQ_CONTROL_OFF_FB_MODE; dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK); } =20 static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); - u32 val; - u16 val_16; =20 pp->bridge->ops =3D &tegra_pci_ops; =20 @@ -900,32 +888,25 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp = *pp) pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); =20 - val =3D dw_pcie_readl_dbi(pci, PCI_IO_BASE); - val &=3D ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); - dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); + dw_pcie_clear_dword(pci, PCI_IO_BASE, IO_BASE_IO_DECODE | + IO_BASE_IO_DECODE_BIT8); =20 - val =3D dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE); - val |=3D CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE; - val |=3D CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE; - dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val); + dw_pcie_set_dword(pci, PCI_PREF_MEMORY_BASE, + CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE | + CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE); =20 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); =20 /* Enable as 0xFFFF0001 response for RRS */ - val =3D dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); - val &=3D ~(AMBA_ERROR_RESPONSE_RRS_MASK << AMBA_ERROR_RESPONSE_RRS_SHIFT); - val |=3D (AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 << - AMBA_ERROR_RESPONSE_RRS_SHIFT); - dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); + dw_pcie_clear_and_set_dword(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, + AMBA_ERROR_RESPONSE_RRS_MASK << AMBA_ERROR_RESPONSE_RRS_SHIFT, + AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 << + AMBA_ERROR_RESPONSE_RRS_SHIFT); =20 /* Clear Slot Clock Configuration bit if SRNS configuration */ - if (pcie->enable_srns) { - val_16 =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + - PCI_EXP_LNKSTA); - val_16 &=3D ~PCI_EXP_LNKSTA_SLC; - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, - val_16); - } + if (pcie->enable_srns) + dw_pcie_clear_dword(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, + PCI_EXP_LNKSTA_SLC); =20 config_gen3_gen4_eq_presets(pcie); =20 @@ -937,17 +918,13 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp = *pp) disable_aspm_l12(pcie); } =20 - if (!pcie->of_data->has_l1ss_exit_fix) { - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); - } + if (!pcie->of_data->has_l1ss_exit_fix) + dw_pcie_clear_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL); =20 - if (pcie->update_fc_fixup) { - val =3D dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); - val |=3D 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; - dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); - } + if (pcie->update_fc_fixup) + dw_pcie_set_dword(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, + 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT); =20 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); =20 @@ -1018,9 +995,8 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pc= i) reset_control_deassert(pcie->core_rst); =20 offset =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF); - val =3D dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); - val &=3D ~PCI_DLF_EXCHANGE_ENABLE; - dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val); + dw_pcie_clear_dword(pci, offset + PCI_DLF_CAP, + PCI_DLF_EXCHANGE_ENABLE); =20 tegra_pcie_dw_host_init(pp); dw_pcie_setup_rc(pp); @@ -1847,11 +1823,9 @@ static void pex_ep_event_pex_rst_deassert(struct teg= ra_pcie_dw *pcie) =20 reset_control_deassert(pcie->core_rst); =20 - if (pcie->update_fc_fixup) { - val =3D dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); - val |=3D 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; - dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); - } + if (pcie->update_fc_fixup) + dw_pcie_set_dword(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, + 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT); =20 config_gen3_gen4_eq_presets(pcie); =20 @@ -1863,11 +1837,9 @@ static void pex_ep_event_pex_rst_deassert(struct teg= ra_pcie_dw *pcie) disable_aspm_l12(pcie); } =20 - if (!pcie->of_data->has_l1ss_exit_fix) { - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); - } + if (!pcie->of_data->has_l1ss_exit_fix) + dw_pcie_clear_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL); =20 pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); --=20 2.49.0