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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2025 10:28:19.9031 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a98a09d9-2003-4048-5e35-08dde61d9be5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000010.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5852 Content-Type: text/plain; charset="utf-8" Add I2C nodes for Tegra264. Signed-off-by: Kartik Rajput --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 225 +++++++++++++++++++++++ 1 file changed, 225 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index e02659efa233..872a69553e3c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -148,6 +148,36 @@ uart0: serial@c5f0000 { status =3D "disabled"; }; =20 + i2c2: i2c@c600000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x0 0x0c600000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_AON_I2C>, + <&bpmp TEGRA264_CLK_PLLAON>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_AON_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLAON>; + resets =3D <&bpmp TEGRA264_RESET_I2C2>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c3: i2c@c610000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x0 0x0c610000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_AON_I2C>, + <&bpmp TEGRA264_CLK_PLLAON>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_AON_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLAON>; + resets =3D <&bpmp TEGRA264_RESET_I2C3>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + pmc: pmc@c800000 { compatible =3D "nvidia,tegra264-pmc"; reg =3D <0x0 0x0c800000 0x0 0x100000>, @@ -272,6 +302,201 @@ smmu4: iommu@b000000 { dma-coherent; }; =20 + i2c14: i2c@c410000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c410000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C14>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c15: i2c@c420000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c420000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C15>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c16: i2c@c430000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c430000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C16>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c0: i2c@c630000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c630000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C0>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c1: i2c@c640000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c640000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C1>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c4: i2c@c650000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c650000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C4>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c6: i2c@c670000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c670000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C6>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c7: i2c@c680000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c680000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C7>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c8: i2c@c690000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c690000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C8>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c9: i2c@c6a0000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c6a0000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C9>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c10: i2c@c6b0000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c6b0000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C10>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c11: i2c@c6c0000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c6c0000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C11>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + + i2c12: i2c@c6d0000 { + compatible =3D "nvidia,tegra264-i2c"; + reg =3D <0x00 0x0c6d0000 0x0 0x10000>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names =3D "div-clk", "parent"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets =3D <&bpmp TEGRA264_RESET_I2C12>; + reset-names =3D "i2c"; + status =3D "disabled"; + }; + gic: interrupt-controller@46000000 { compatible =3D "arm,gic-v3"; reg =3D <0x00 0x46000000 0x0 0x010000>, /* GICD */ --=20 2.43.0