From nobody Fri Oct 3 15:37:44 2025 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1491B26F46F; Thu, 28 Aug 2025 09:48:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756374483; cv=none; b=NN/a0bBYg407fgnnG6azCaMbIgQhkqoILZ6IyVcPrxYELebj3T2wNGSeYIwpetKC3rWjp17cwfDS4U81/6i597Z+C91xsxB/188GZiHhunVkHcPR/T8Ijcf/4M5dLM38goDjPXB91VAUOINggQtZvpK6hsOgJcf0016kYVRof0Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756374483; c=relaxed/simple; bh=m3MMu0hhanBtX1e6y768SAytNhJDMFCxOd6xiN3X6/8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FvFLpUBWvfCP9u6ILuz9xQ/7uDPUNEpGkN29Bgs2STXgnRew6JFhSKEerLmm2APZ0Sq4jXLEc3HwVQlehhPfUnsaM23HAKagmyIqHu7BrHUcdvStVdCDuaZ7q9FZv8k4ZLpX/MPl95WsiImVYFeKIsktJQj+3LvZqrvOAHqOzTc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com; spf=pass smtp.mailfrom=ew.tq-group.com; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b=ll2yFRkc; dkim=fail (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b=XR8J/JzF reason="key not found in DNS"; arc=none smtp.client-ip=93.104.207.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b="ll2yFRkc"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="XR8J/JzF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1756374481; x=1787910481; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D8nQkRvpmKKt09UiqtWevDsmYEzF6a0SS4RoNlY4WkA=; b=ll2yFRkcZp7Qj4Pbgx+35xVL0Pq10+GQj9ysn3KmDYfJEdPXNSVKLplc qhGoTqzB9wk4NUdMzkTpceRtOB2ebp1dKzjbUbb84ab4nMYaq4UodsHZr ybe8eiR1l/KfkLkkhdORMb2sGdYY7CYL15odO5L7MKgJ5MMIceouQkoH4 oqi5FQREv6UNHcIkvf5+wFvQt22liXZNeF21FxSp0X63UvjJ6OiYme57O oFZqMKUjngkPFIqL/xIvJYQ3+NuVyfOh/9GOJiK87dzhL/hUBK+GM8Or3 /OAAtV228xf3VsCCLRqOv6Ld6UuiK0bb55FSoB5oZcvzmm2avJI7If9SL A==; X-CSE-ConnectionGUID: IVm/NR15SRWLvhrdJFb3YQ== X-CSE-MsgGUID: ESBlCGXxQ8arFe4RadziYQ== X-IronPort-AV: E=Sophos;i="6.18,217,1751234400"; d="scan'208";a="45953047" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 28 Aug 2025 11:47:58 +0200 X-CheckPoint: {68B025CE-17-299FBAB0-EF52EDE7} X-MAIL-CPID: FB74D8873684AD535BEE68EAC473F561_5 X-Control-Analysis: str=0001.0A002105.68B025CF.0078,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8949C16947D; Thu, 28 Aug 2025 11:47:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1756374474; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=D8nQkRvpmKKt09UiqtWevDsmYEzF6a0SS4RoNlY4WkA=; b=XR8J/JzFiqHhgaXBwzwPipx5NU14j83641gTXAIBTF8tzDAIK1TSFyiRx/bDc/CMPH7Efo i5pjIjfItVqw5El3oZQ9qWNXCTJqzJ7kJTPDQNDxaSz/ENmeEqSnfQIzSIflczG9O8vzUH QhD3YakaKt3RKfOv6kg/Ps1jRVfkeylOErtpABdSlSTqSpk/atyDQIEcv0DM0rmORjB/XJ pqbXcnmt40qzZy7whNZ4VRAc5OQErxBrOfAX/OJsJO8hEkwkJGWrg5VomRKmmW42lwrT2K +CkixEhLMb5GiLAoMb/fRvJ8fR9amC0bLmDrG3mXOBaBxd2LklyMd57oYO3VwQ== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Alexander Stein , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com Subject: [PATCH 1/2] dt-bindings: arm: fsl: add TQMa91xxLA SOM Date: Thu, 28 Aug 2025 11:47:42 +0200 Message-ID: <20250828094745.3733533-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250828094745.3733533-1-alexander.stein@ew.tq-group.com> References: <20250828094745.3733533-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" TQMa91xxLA is a SOM variant in the TQ-Systems GmbH TQMa91xx series using NXP i.MX91 CPU on an LGA type board. MBa91xxCA is a starterkit base board for TQMa91xxLA on an adapter board. Signed-off-by: Alexander Stein Reviewed-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index ebafa6ecbcb64..0843c5e9275be 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1433,6 +1433,24 @@ properties: - fsl,imxrt1170-evk # i.MXRT1170 EVK Board - const: fsl,imxrt1170 =20 + - description: + TQMa91xxLA and TQMa91xxCA are two series of feature compatible S= OM + using NXP i.MX91 SOC in 11x11 mm package. + TQMa91xxLA is designed to be soldered on different carrier board= s. + TQMa91xxCA is a compatible variant using board to board connecto= rs. + All SOM and CPU variants use the same device tree hence only one + compatible is needed. Bootloader disables all features not prese= nt + in the assembled SOC. + MBa91xxCA mainboard can be used as starterkit for the SOM + soldered on an adapter board or for the connector variant + MBa91xxLA mainboard is a single board computer using the soldera= ble + SOM variant + items: + - enum: + - tq,imx91-tqma9131-mba91xxca # TQ-Systems GmbH i.MX91 TQMa9= 1xxCA/LA SOM on MBa91xxCA + - const: tq,imx91-tqma9131 # TQ-Systems GmbH i.MX91 TQMa9= 1xxCA/LA SOM + - const: fsl,imx91 + - description: TQMa93xxLA and TQMa93xxCA are two series of feature compatible S= OM using NXP i.MX93 SOC in 11x11 mm package. --=20 2.43.0 From nobody Fri Oct 3 15:37:44 2025 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6CDB2ED141; Thu, 28 Aug 2025 09:48:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; 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X-CSE-ConnectionGUID: jL3W3PCdSxC2FnwgQuHGMg== X-CSE-MsgGUID: SccCeNYlQR+OyX13EDjsQQ== X-IronPort-AV: E=Sophos;i="6.18,217,1751234400"; d="scan'208";a="45953048" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 28 Aug 2025 11:48:04 +0200 X-CheckPoint: {68B025D4-2C-AD8F5F64-F0EACAA5} X-MAIL-CPID: DCBA5596B410D01D65AC702F1E9888EB_1 X-Control-Analysis: str=0001.0A00210B.68B026F8.0046,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F24C2169476; Thu, 28 Aug 2025 11:47:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1756374480; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=20f8TN6rUSbNfHjL+x4oeeyMAXKfnv1ChSbem98tBJg=; b=aI5b7UF55dyUNNUT7XyHG0rLlMLaINyc9Gbt/Ec5d4w5HQ/4tfmj+jkYsMfFwVP38D+UWX CyDZ9F+xzp/G/7ZhYPyB5VUHCgrRD0ShIUjV7c5fTL0qBn4YooRU+QShijyaEIEtqXsY6S C1IJdAOhuLqsLz5SAVy69xEofloHX+2Iw2O0wTFiwphWj1dgMNRVZJoZMLj7N1dTraVLzl ORNe4sMMO7WXnTUP039ANZfCnsYOzC6U5sKtFDGB/9Bh2Yq3/LPxXHHJ3ueAijJtePQ8IJ QEA0TcRkiEwznE9lFMS2w4pXbL/MVULODDPk2FsbcRI25O7MGqTlwY/88cjEqw== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Alexander Stein , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com Subject: [PATCH 2/2] arm64: dts: freescale: add initial device tree for TQMa91xxCA/MBa91xxCA Date: Thu, 28 Aug 2025 11:47:43 +0200 Message-ID: <20250828094745.3733533-3-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250828094745.3733533-1-alexander.stein@ew.tq-group.com> References: <20250828094745.3733533-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" This adds support for TQMa91xxCA module attached to MBa91xxCA board. TQMa91xx is a SOM using i.MX91 SOC. The SOM features PMIC, RAM, e-MMC and some optional peripherals like SPI-NOR, RTC, EEPROM, gyroscope and secure element. Signed-off-by: Alexander Stein --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx91-tqma9131-mba91xxca.dts | 737 ++++++++++++++++++ .../boot/dts/freescale/imx91-tqma9131.dtsi | 295 +++++++ 3 files changed, 1033 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.= dts create mode 100644 arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 947de7f125caf..3a937232d6f29 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -338,6 +338,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-tqma8xqps-mb-smarc-= 2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx91-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx91-tqma9131-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-9x9-qsb.dtb =20 imx93-9x9-qsb-i3c-dtbs +=3D imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts b/a= rch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts new file mode 100644 index 0000000000000..354cebf4a7c9e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts @@ -0,0 +1,737 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include "imx91-tqma9131.dtsi" + +/{ + model =3D "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa91xxCA starter k= it"; + compatible =3D "tq,imx91-tqma9131-mba91xxca", "tq,imx91-tqma9131", "fsl,i= mx91"; + chassis-type =3D "embedded"; + + chosen { + stdout-path =3D &lpuart1; + }; + + aliases { + eeprom0 =3D &eeprom0; + ethernet0 =3D &eqos; + ethernet1 =3D &fec; + gpio0 =3D &gpio1; + gpio1 =3D &gpio2; + gpio2 =3D &gpio3; + gpio3 =3D &gpio4; + i2c0 =3D &lpi2c1; + i2c1 =3D &lpi2c2; + i2c2 =3D &lpi2c3; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + rtc0 =3D &pcf85063; + rtc1 =3D &bbnsm_rtc; + serial0 =3D &lpuart1; + serial1 =3D &lpuart2; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&tpm2 2 5000000 0>; + brightness-levels =3D <0 4 8 16 32 64 128 255>; + default-brightness-level =3D <7>; + power-supply =3D <®_12v0>; + enable-gpios =3D <&expander2 2 GPIO_ACTIVE_HIGH>; + status =3D "disabled"; + }; + + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + power-supply =3D <®_3v3>; + enable-gpios =3D <&expander2 1 GPIO_ACTIVE_HIGH>; + backlight =3D <&backlight>; + status =3D "disabled"; + + port { + panel_in: endpoint { + }; + }; + }; + + fan0: gpio-fan { + compatible =3D "gpio-fan"; + gpios =3D <&expander2 4 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map =3D <0 0>, <10000 1>; + fan-supply =3D <®_12v0>; + #cooling-cells =3D <2>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + autorepeat; + + switch-a { + label =3D "switcha"; + linux,code =3D ; + gpios =3D <&expander0 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-b { + label =3D "switchb"; + linux,code =3D ; + gpios =3D <&expander0 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + + led-1 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&expander2 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "default-on"; + }; + + led-2 { + color =3D ; + function =3D LED_FUNCTION_HEARTBEAT; + gpios =3D <&expander2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + lvds_encoder: lvds-encoder { + compatible =3D "ti,sn75lvds83", "lvds-encoder"; + powerdown-gpios =3D <&expander2 3 GPIO_ACTIVE_LOW>; + power-supply =3D <®_3v3>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + lvds_encoder_input: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + lvds_encoder_output: endpoint { + }; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_MB"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_5V0_MB"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_12V"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + gpio =3D <&expander1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_1v5: regulator-mpcie-1v5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_1V5_MPCIE"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + gpio =3D <&expander0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mpcie_3v3: regulator-mpcie-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_MPCIE"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&expander0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&adc1 { + status =3D "okay"; +}; + +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy_eqos>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos_phy>; + reset-gpios =3D <&expander1 0 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <500000>; + reset-deassert-us =3D <50000>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <26 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel =3D ; + }; + }; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy_fec>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec_phy>; + reset-gpios =3D <&expander1 1 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <500000>; + reset-deassert-us =3D <50000>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <27 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel =3D ; + }; + }; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + xceiver-supply =3D <®_3v3>; + status =3D "okay"; +}; + +&gpio1 { + gpio-line-names =3D + /* 00 */ "", "", "", "PMIC_IRQ#", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#", + /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio2 { + gpio-line-names =3D + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio3 { + gpio-line-names =3D + /* 00 */ "SD2_CD#", "", "", "", + /* 04 */ "", "", "", "SD2_RST#", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#", + /* 28 */ "", "", "", ""; +}; + +&gpio4 { + gpio-line-names =3D + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&lpi2c3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_lpi2c3>; + pinctrl-1 =3D <&pinctrl_lpi2c3>; + status =3D "okay"; + + temperature-sensor@1c { + compatible =3D "nxp,se97b", "jedec,jc-42.4-temp"; + reg =3D <0x1c>; + }; + + ptn5110: usb-typec@50 { + compatible =3D "nxp,ptn5110", "tcpci"; + reg =3D <0x50>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_typec>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <10 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible =3D "usb-c-connector"; + label =3D "X17"; + power-role =3D "dual"; + data-role =3D "dual"; + try-power-role =3D "sink"; + typec-power-opmode =3D "default"; + pd-disable; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint =3D <&typec_hs>; + }; + }; + }; + }; + + eeprom2: eeprom@54 { + compatible =3D "nxp,se97b", "atmel,24c02"; + reg =3D <0x54>; + pagesize =3D <16>; + vcc-supply =3D <®_3v3>; + }; + + expander0: gpio@70 { + compatible =3D "nxp,pca9538"; + reg =3D <0x70>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pexp_irq>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <12 IRQ_TYPE_LEVEL_LOW>; + vcc-supply =3D <®_3v3>; + gpio-line-names =3D "TEMP_EVENT_MOD#", "MPCIE_WAKE#", + "MPCIE_1V5_EN", "MPCIE_3V3_EN", + "MPCIE_PERST#", "MPCIE_WDISABLE#", + "BUTTON_A#", "BUTTON_B#"; + + temp-event-mod-hog { + gpio-hog; + gpios =3D <0 GPIO_ACTIVE_LOW>; + input; + line-name =3D "TEMP_EVENT_MOD#"; + }; + + mpcie-wake-hog { + gpio-hog; + gpios =3D <1 GPIO_ACTIVE_LOW>; + input; + line-name =3D "MPCIE_WAKE#"; + }; + + /* + * Controls the mPCIE slot reset which is low active as + * reset signal. The output-low states, the signal is + * inactive, e.g. not in reset + */ + mpcie_rst_hog: mpcie-rst-hog { + gpio-hog; + gpios =3D <4 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "MPCIE_PERST#"; + }; + + /* + * Controls the mPCIE slot WDISABLE pin which is low active + * as disable signal. The output-low states, the signal is + * inactive, e.g. not disabled + */ + mpcie_wdisable_hog: mpcie-wdisable-hog { + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "MPCIE_WDISABLE#"; + }; + }; + + expander1: gpio@71 { + compatible =3D "nxp,pca9538"; + reg =3D <0x71>; + gpio-controller; + #gpio-cells =3D <2>; + vcc-supply =3D <®_3v3>; + gpio-line-names =3D "ENET1_RESET#", "ENET2_RESET#", + "USB_RESET#", "", + "WLAN_PD#", "WLAN_W_DISABLE#", + "WLAN_PERST#", "12V_EN"; + + /* + * Controls the WiFi card PD pin which is low active + * as power down signal. The output-low states, the signal + * is inactive, e.g. not power down + */ + wlan-pd-hog { + gpio-hog; + gpios =3D <4 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "WLAN_PD#"; + }; + + /* + * Controls the WiFi card disable pin which is low active + * as disable signal. The output-low states, the signal + * is inactive, e.g. not disabled + */ + wlan-wdisable-hog { + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "WLAN_W_DISABLE#"; + }; + + /* + * Controls the WiFi card reset pin which is low active + * as reset signal. The output-low states, the signal + * is inactive, e.g. not in reset + */ + wlan-perst-hog { + gpio-hog; + gpios =3D <6 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "WLAN_PERST#"; + }; + }; + + expander2: gpio@72 { + compatible =3D "nxp,pca9538"; + reg =3D <0x72>; + gpio-controller; + #gpio-cells =3D <2>; + vcc-supply =3D <®_3v3>; + gpio-line-names =3D "LCD_RESET#", "LCD_PWR_EN", + "LCD_BLT_EN", "LVDS_SHDN#", + "FAN_PWR_EN", "", + "USER_LED1", "USER_LED2"; + }; +}; + +&lpuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&lpuart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + status =3D "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# from SoM is connected on mainboard */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcf85063>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&se97_som { + /* TEMP_EVENT# from SoM is connected on mainboard */ + interrupt-parent =3D <&expander0>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; +}; + +&tpm2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tpm2>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + status =3D "okay"; + + port { + typec_hs: endpoint { + remote-endpoint =3D <&typec_con_hs>; + }; + }; +}; + +&usbotg2 { + dr_mode =3D "host"; + #address-cells =3D <1>; + #size-cells =3D <0>; + disable-over-current; + status =3D "okay"; + + hub_2_0: hub@1 { + compatible =3D "usb424,2517"; + reg =3D <1>; + reset-gpios =3D <&expander1 2 GPIO_ACTIVE_LOW>; + vdd-supply =3D <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + no-sdio; + no-mmc; + disable-wp; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins =3D /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X4 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X3 */ + ; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins =3D /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X4 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X3 */ + ; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins =3D /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D /* HYS | PU | FSEL_0 | DSE no drive */ + , + /* PU | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_jtag: jtaggrp { + fsl,pins =3D , + , + , + ; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins =3D /* SION | HYS | OD | FSEL_3 | DSE X4 */ + , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins =3D ; + }; + + pinctrl_pexp_irq: pexpirqgrp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_rgbdisp: rgbdispgrp { + fsl,pins =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_touch: touchgrp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_tpm2: tpm2grp { + fsl,pins =3D ; + }; + + pinctrl_typec: typecgrp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D /* HYS | FSEL_0 | No DSE */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins =3D /* PD | FSEL_3 | DSE X5 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + /* HYS | PU | FSEL_3 | DSE X3 */ + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins =3D /* PD | FSEL_3 | DSE X6 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi b/arch/arm64= /boot/dts/freescale/imx91-tqma9131.dtsi new file mode 100644 index 0000000000000..a92bc2000367f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ + +#include "imx91.dtsi" + +/{ + model =3D "TQ-Systems i.MX91 TQMa91xxCA / TQMa91xxLA SOM"; + compatible =3D "tq,imx91-tqma9131", "fsl,imx91"; + + memory@80000000 { + device_type =3D "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg =3D <0x00000000 0x80000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* default CMA, must not exceed assembled memory */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + alloc-ranges =3D <0 0x80000000 0 0x40000000>; + size =3D <0 0x10000000>; + linux,cma-default; + }; + + /* EdgeLock secure enclave */ + ele_reserved: ele-reserved@a4120000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + /* SD2 RST# via PMIC SW_EN */ + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&buck4>; + gpio =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + vref-supply =3D <&buck5>; +}; + +&flexspi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexspi1>; + status =3D "okay"; + + flash0: flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + /* + * no DQS, RXCLKSRC internal loop back, max 66 MHz + * clk framework uses CLK_DIVIDER_ROUND_CLOSEST + * selected value together with root from + * IMX91_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to + * respect the maximum value. + */ + spi-max-frequency =3D <62000000>; + spi-tx-bus-width =3D <4>; + spi-rx-bus-width =3D <4>; + vcc-supply =3D <&buck5>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + }; +}; + +&lpi2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_lpi2c1>; + pinctrl-1 =3D <&pinctrl_lpi2c1>; + status =3D "okay"; + + se97_som: temperature-sensor@1b { + compatible =3D "nxp,se97b", "jedec,jc-42.4-temp"; + reg =3D <0x1b>; + }; + + pca9451a: pmic@25 { + compatible =3D "nxp,pca9451a"; + reg =3D <0x25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pca9451>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */ + buck1: BUCK1 { + regulator-name =3D "BUCK1"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + /* V_DDRQ - 1.1 V for LPDDR4 */ + buck2: BUCK2 { + regulator-name =3D "BUCK2"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + /* V_3V3 - EEPROM, RTC, ... */ + buck4: BUCK4 { + regulator-name =3D "BUCK4"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 - SPI NOR, eMMC, RAM VDD1... */ + buck5: BUCK5 { + regulator-name =3D "BUCK5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 - RAM VDD2*/ + buck6: BUCK6 { + regulator-name =3D "BUCK6"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_BBSM, fix 1.8 */ + ldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_ANA */ + ldo4: LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_SD2 - 3.3/1.8V USDHC2 io Voltage */ + ldo5: LDO5 { + regulator-name =3D "LDO5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcf85063: rtc@51 { + compatible =3D "nxp,pcf85063a"; + reg =3D <0x51>; + quartz-load-femtofarads =3D <7000>; + }; + + eeprom0: eeprom@53 { + compatible =3D "nxp,se97b", "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <16>; + read-only; + vcc-supply =3D <&buck4>; + }; + + eeprom1: eeprom@57 { + compatible =3D "atmel,24c64"; + reg =3D <0x57>; + pagesize =3D <32>; + vcc-supply =3D <&buck4>; + }; + + /* protectable identification memory (part of M24C64-D @57) */ + eeprom@5f { + compatible =3D "atmel,24c64d-wl"; + reg =3D <0x5f>; + vcc-supply =3D <&buck4>; + }; + + imu@6a { + compatible =3D "st,ism330dhcx"; + reg =3D <0x6a>; + vdd-supply =3D <&buck4>; + vddio-supply =3D <&buck4>; + }; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1>; + pinctrl-2 =3D <&pinctrl_usdhc1>; + vmmc-supply =3D <&buck4>; + vqmmc-supply =3D <&buck5>; + bus-width =3D <8>; + non-removable; + no-sdio; + no-sd; + status =3D "okay"; +}; + +&wdog3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins =3D /* FSEL 3 | DSE X6 */ + , + , + /* HYS | PU | FSEL 3 | DSE X6 */ + , + , + /* HYS | FSEL 3 | DSE X6 (external PU) */ + , + ; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D /* SION | OD | FSEL 3 | DSE X4 */ + , + ; + }; + + pinctrl_pca9451: pca9451grp { + fsl,pins =3D /* HYS | PU */ + ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D /* FSEL 2 | DSE X2 */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D /* PD | FSEL 3 | DSE X5 */ + , + /* HYS | FSEL 0 | no drive */ + , + /* HYS | FSEL 3 | X5 */ + , + /* HYS | FSEL 3 | X4 */ + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D /* PU | FSEL 1 | DSE X4 */ + ; + }; +}; --=20 2.43.0