From nobody Fri Oct 3 15:33:18 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B832922F74D; Thu, 28 Aug 2025 09:35:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756373731; cv=none; b=Rdg3nOPjMrssaWl+KVSGzak4flUeHbf6kBgB3ZTpdQpiOLnbScWqpc+Kp3pOJCH6Dpf5EfVSjbFSQJpRObweGE7AMhI8ErRSMqlI7HR94QCDPnIJZFfX60338G57wXZa1JYuUwnWiQO9Xur6IrXhbb4pR1S4M2T6HK8tl3/IWmM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756373731; c=relaxed/simple; bh=DGN16H4IRg8rut2+1xYh5AWMXaZkabwUNnbhnl/apG4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YdhoW3Zd5KHgO2fm4h20H3is5hz0p0xXpZbkSN+uwkuww3OhSIrjrE4fE/tJ/1LtnXlSTzVMfOQyTJx01D5dXo3syADuFj9AujFOfnUHj/C172qRLdlkaKSJZwDOJodpA8DdIAckPLoQLB16VU1gOGBmw991Zm5TCghcr3DM3WU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=KECyoKtF; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="KECyoKtF" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57S5V6aS027635; Thu, 28 Aug 2025 09:35:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= PDhUYR3sEIfa/680HsEZglzFXFg/RoJHufmml9cCY1I=; b=KECyoKtFUdWnjypG BE1oQzOq0DERh9b7eS2UUew1+xULf9FWY2eCqvKLjx+Si35jIgjbwaUZTtY7Os7k wdYygsrlQxEs3DmqnoXkNOSBe98xJX7FPoFwE2SEsZTrqHaLQNjownh4hLkxCecO NxfTaSZnHPnWsPYcSfsGCra4MGJVT9khoTJ6kVzG3u1uM8m4fvc9C58uL/+hfGG1 E73idZuMH+fIw2IjrYMdhAMuFyPnEWE9Vi49dTz/gj6IUYJIweOEig0au7HRdjoH tVZB+bhevH53z0Quv+hM/k+FQxt9yjNxtEpySGJgvK66kfQjiYaG2vPFuwGyg+yB +Ter+Q== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48se16xqx3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Aug 2025 09:35:18 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57S9ZFit024856 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Aug 2025 09:35:15 GMT Received: from haixcui1-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Thu, 28 Aug 2025 02:35:11 -0700 From: Haixu Cui To: , , , , , , , , , , , CC: , Subject: [PATCH v9 1/3] virtio: Add ID for virtio SPI Date: Thu, 28 Aug 2025 17:34:49 +0800 Message-ID: <20250828093451.2401448-2-quic_haixcui@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250828093451.2401448-1-quic_haixcui@quicinc.com> References: <20250828093451.2401448-1-quic_haixcui@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: tFGuqXjx6WurPJXiOdV0BWdafFtvj1lM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODI2MDEyMCBTYWx0ZWRfXz9QeY24ok9II Z7jA/L6Y3NJY/bNnNy6zDIAIjvV2i2fT4T8tsH441OM6w/NfWL5uduDIByKrVqtboQ5uLfIVn+g F+tUYgUbq3w+i9bGGDgR3mVXjC+YWl+6t1fcT7kzO/ymHrGSbeMQuFGvjrLH+YmPgVWtuYTSQvq raySOaZ9UcooklZ7Z0Xg5dSP6BAT7JcDgtm2ZgUUAEi/Ex6LVl3yV+EGeyLF52YbTqSwwfdilyf XD84QNnY9UEDYtj1hyXSn9W3c7WF0/xVopdhSWT2S40Km3CzmCzYBXleoMRYkRbg4Ixg73UAC8+ NnI90VWJ1qTuz+fPBiubQdPeRLNOYk5ZHbuxoN67A0PcMOa6GNYuK9Ji1teK1qxR4/aIVwMSSvv 019ttCRy X-Proofpoint-ORIG-GUID: tFGuqXjx6WurPJXiOdV0BWdafFtvj1lM X-Authority-Analysis: v=2.4 cv=CNYqXQrD c=1 sm=1 tr=0 ts=68b022d6 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=KqJd8QcNxZFF0aacHC0A:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-28_02,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 priorityscore=1501 adultscore=0 spamscore=0 phishscore=0 suspectscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508260120 Content-Type: text/plain; charset="utf-8" Add VIRTIO_ID_SPI definition for virtio SPI. Signed-off-by: Haixu Cui Reviewed-by: Viresh Kumar Reviewed-by: Alex Benn=C3=A9e --- include/uapi/linux/virtio_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/virtio_ids.h b/include/uapi/linux/virtio_id= s.h index 7aa2eb766205..6c12db16faa3 100644 --- a/include/uapi/linux/virtio_ids.h +++ b/include/uapi/linux/virtio_ids.h @@ -68,6 +68,7 @@ #define VIRTIO_ID_AUDIO_POLICY 39 /* virtio audio policy */ #define VIRTIO_ID_BT 40 /* virtio bluetooth */ #define VIRTIO_ID_GPIO 41 /* virtio gpio */ +#define VIRTIO_ID_SPI 45 /* virtio spi */ =20 /* * Virtio Transitional IDs --=20 2.34.1 From nobody Fri Oct 3 15:33:18 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DA872BD5BF; Thu, 28 Aug 2025 09:35:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756373742; cv=none; b=rv87r1SbmCLdgBx9ec19I0g2zFhdoyUMSs0RLdt46g/H1PMeXAmT+Npd0MChBJozDJZuD8l4IQoPUxsrTuRF1LZ/Y1VYsnXTHGOI20hMyxS0iT1drk99UObLvApWJ862EAXuxRILiq3HYs4lI/7alcx3oPhSu8ZgX+MiQDK+We8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756373742; c=relaxed/simple; bh=OZkDAmkv2aNrak69K0oTeLgSiGUso6xoQd6W1xtrgm4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QLgB/P2DtNfv9xaM/oRZmYnjRbesOf8J3jZngWBfPmZ7eDz+rtPZx+WRUeQmzpJOixbDj7jm4OkwikID1IbOB86VywVU0xjc9lpZVn+LiIjWFILm82j8z1O8YAvFApn3mpzv0UlvHy5LayiLNJxdIxm4ZnzlzRTxzvaMJC5Tt20= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ZpDrCFrY; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ZpDrCFrY" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57S5nuLo015950; Thu, 28 Aug 2025 09:35:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= bcuw++0VBS+yA70Y39SUs9cF76+4nMyln0GJ6PA4R9s=; b=ZpDrCFrYOYB514hu Mg1nt2YY8kTfZRhwRxsBUk3YQaRgPcYDRY0zudAcN6dtZrPMiXHA4BuFpAYO9VqP jcF/frPaZWGF0FpDpemHBu09UI+OtdsYkTQsNY1p2+C/jvCD1Wev9Nftr2fSjRdj wsrupBOy/J6C2syrZFH44VGUqy36liCQeIF/urEbJdRVnipRH07CPaPwELR96zEz kpEtIHnRLtMYCLsRL30TdT6toN5NdSry5ac97hgOj0KCA3gerXHEQLErg23j+oPB KWDIlMKzWS/TkWxa5gACgQMX9aAWpRNse6rsE97APMVXDZbq3uYFPYUNS2lQiJcE Rc0ojQ== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48rtpf214k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Aug 2025 09:35:22 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57S9ZKrC011149 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Aug 2025 09:35:20 GMT Received: from haixcui1-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Thu, 28 Aug 2025 02:35:17 -0700 From: Haixu Cui To: , , , , , , , , , , , CC: , Subject: [PATCH v9 2/3] virtio-spi: Add virtio-spi.h Date: Thu, 28 Aug 2025 17:34:50 +0800 Message-ID: <20250828093451.2401448-3-quic_haixcui@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250828093451.2401448-1-quic_haixcui@quicinc.com> References: <20250828093451.2401448-1-quic_haixcui@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5HluWi42TYG0ldcaA65Y3Rk1vefwJxaa X-Proofpoint-ORIG-GUID: 5HluWi42TYG0ldcaA65Y3Rk1vefwJxaa X-Authority-Analysis: v=2.4 cv=Hd8UTjE8 c=1 sm=1 tr=0 ts=68b022da cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=Z4Rwk6OoAAAA:8 a=VwQbUJbxAAAA:8 a=rqJjEXyH_1KH1bkhQPcA:9 a=TjNXssC_j7lpFel5tvFf:22 a=HkZW87K1Qel5hWWM3VKY:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODI1MDE0MiBTYWx0ZWRfX201JJ5mIk1Vw HVRI6aVvtRpVWZ27sopt/8rspFxUIU+k/0arz3X9fdJbnS7R/NtfFt+xOIlPMp7Cz4Ze21aGHCY qWFYGOI88Jghhm1cHXazc/n1ELW/lcFPii0E74A+GYdyueRrqUtlF7DhPokUwSxBoTP/F5aaWNR os3U0PXmtPY4ukO4cU4zHtUW9++8mCBTHzaHCAzav9LSZK0lzmWrbmQhv7IHh/HKinGDDPRBxQY o+LKZmWzHd+Bi2FCgvQgZCmQ0efAf7/GqwTlRP4Sznq+i8S634tQBN65rgF1etkBoqy4FVkVMY+ CYeku31Wyy3pOhiBc7pYiek9KWbM23vyQkYc1GTdcnSMXaV7sB6n2TOplNTNLXjxycWO23OVtQo eK6ieTWz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-28_02,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 clxscore=1011 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508250142 Content-Type: text/plain; charset="utf-8" Add virtio-spi.h header for virtio SPI. Signed-off-by: Haixu Cui Reviewed-by: Alex Benn=C3=A9e --- MAINTAINERS | 6 ++ include/uapi/linux/virtio_spi.h | 181 ++++++++++++++++++++++++++++++++ 2 files changed, 187 insertions(+) create mode 100644 include/uapi/linux/virtio_spi.h diff --git a/MAINTAINERS b/MAINTAINERS index fed6cd812d79..af98e411138d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26790,6 +26790,12 @@ S: Maintained F: include/uapi/linux/virtio_snd.h F: sound/virtio/* =20 +VIRTIO SPI DRIVER +M: Haixu Cui +L: virtualization@lists.linux-foundation.org +S: Maintained +F: include/uapi/linux/virtio_spi.h + VIRTUAL BOX GUEST DEVICE DRIVER M: Hans de Goede M: Arnd Bergmann diff --git a/include/uapi/linux/virtio_spi.h b/include/uapi/linux/virtio_sp= i.h new file mode 100644 index 000000000000..8ab3c970cdd3 --- /dev/null +++ b/include/uapi/linux/virtio_spi.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2023 OpenSynergy GmbH + * Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef _LINUX_VIRTIO_VIRTIO_SPI_H +#define _LINUX_VIRTIO_VIRTIO_SPI_H + +#include +#include +#include +#include + +/* Sample data on trailing clock edge */ +#define VIRTIO_SPI_CPHA _BITUL(0) +/* Clock is high when IDLE */ +#define VIRTIO_SPI_CPOL _BITUL(1) +/* Chip Select is active high */ +#define VIRTIO_SPI_CS_HIGH _BITUL(2) +/* Transmit LSB first */ +#define VIRTIO_SPI_MODE_LSB_FIRST _BITUL(3) +/* Loopback mode */ +#define VIRTIO_SPI_MODE_LOOP _BITUL(4) + +/** + * struct virtio_spi_config - All config fields are read-only for the + * Virtio SPI driver + * @cs_max_number: maximum number of chipselect the host SPI controller + * supports. + * @cs_change_supported: indicates if the host SPI controller supports to = toggle + * chipselect after each transfer in one message: + * 0: unsupported, chipselect will be kept in active state throughout the + * message transaction; + * 1: supported. + * Note: Message here contains a sequence of SPI transfers. + * @tx_nbits_supported: indicates the supported number of bit for writing: + * bit 0: DUAL (2-bit transfer), 1 for supported + * bit 1: QUAD (4-bit transfer), 1 for supported + * bit 2: OCTAL (8-bit transfer), 1 for supported + * other bits are reserved as 0, 1-bit transfer is always supported. + * @rx_nbits_supported: indicates the supported number of bit for reading: + * bit 0: DUAL (2-bit transfer), 1 for supported + * bit 1: QUAD (4-bit transfer), 1 for supported + * bit 2: OCTAL (8-bit transfer), 1 for supported + * other bits are reserved as 0, 1-bit transfer is always supported. + * @bits_per_word_mask: mask indicating which values of bits_per_word are + * supported. If not set, no limitation for bits_per_word. + * @mode_func_supported: indicates the following features are supported or= not: + * bit 0-1: CPHA feature + * 0b00: invalid, should support as least one CPHA setting + * 0b01: supports CPHA=3D0 only + * 0b10: supports CPHA=3D1 only + * 0b11: supports CPHA=3D0 and CPHA=3D1. + * bit 2-3: CPOL feature + * 0b00: invalid, should support as least one CPOL setting + * 0b01: supports CPOL=3D0 only + * 0b10: supports CPOL=3D1 only + * 0b11: supports CPOL=3D0 and CPOL=3D1. + * bit 4: chipselect active high feature, 0 for unsupported and 1 for + * supported, chipselect active low is supported by default. + * bit 5: LSB first feature, 0 for unsupported and 1 for supported, + * MSB first is supported by default. + * bit 6: loopback mode feature, 0 for unsupported and 1 for supported, + * normal mode is supported by default. + * @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no + * limitation for transfer speed. + * @max_word_delay_ns: the maximum word delay supported, in nanoseconds. + * A value of 0 indicates that word delay is unsupported. + * Each transfer may consist of a sequence of words. + * @max_cs_setup_ns: the maximum delay supported after chipselect is asser= ted, + * in ns unit, 0 means delay is not supported to introduce after chipsel= ect is + * asserted. + * @max_cs_hold_ns: the maximum delay supported before chipselect is deass= erted, + * in ns unit, 0 means delay is not supported to introduce before chipse= lect + * is deasserted. + * @max_cs_incative_ns: maximum delay supported after chipselect is deasse= rted, + * in ns unit, 0 means delay is not supported to introduce after chipsel= ect is + * deasserted. + */ +struct virtio_spi_config { + __u8 cs_max_number; + __u8 cs_change_supported; +#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL _BITUL(0) +#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD _BITUL(1) +#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL _BITUL(2) + __u8 tx_nbits_supported; + __u8 rx_nbits_supported; + __le32 bits_per_word_mask; +#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 _BITUL(0) +#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 _BITUL(1) +#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 _BITUL(2) +#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 _BITUL(3) +#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH _BITUL(4) +#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST _BITUL(5) +#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK _BITUL(6) + __le32 mode_func_supported; + __le32 max_freq_hz; + __le32 max_word_delay_ns; + __le32 max_cs_setup_ns; + __le32 max_cs_hold_ns; + __le32 max_cs_inactive_ns; +}; + +/** + * struct spi_transfer_head - virtio SPI transfer descriptor + * @chip_select_id: chipselect index the SPI transfer used. + * @bits_per_word: the number of bits in each SPI transfer word. + * @cs_change: whether to deselect device after finishing this transfer + * before starting the next transfer, 0 means cs keep asserted and + * 1 means cs deasserted then asserted again. + * @tx_nbits: bus width for write transfer. + * 0,1: bus width is 1, also known as SINGLE + * 2 : bus width is 2, also known as DUAL + * 4 : bus width is 4, also known as QUAD + * 8 : bus width is 8, also known as OCTAL + * other values are invalid. + * @rx_nbits: bus width for read transfer. + * 0,1: bus width is 1, also known as SINGLE + * 2 : bus width is 2, also known as DUAL + * 4 : bus width is 4, also known as QUAD + * 8 : bus width is 8, also known as OCTAL + * other values are invalid. + * @reserved: for future use. + * @mode: SPI transfer mode. + * bit 0: CPHA, determines the timing (i.e. phase) of the data + * bits relative to the clock pulses.For CPHA=3D0, the + * "out" side changes the data on the trailing edge of the + * preceding clock cycle, while the "in" side captures the data + * on (or shortly after) the leading edge of the clock cycle. + * For CPHA=3D1, the "out" side changes the data on the leading + * edge of the current clock cycle, while the "in" side + * captures the data on (or shortly after) the trailing edge of + * the clock cycle. + * bit 1: CPOL, determines the polarity of the clock. CPOL=3D0 is a + * clock which idles at 0, and each cycle consists of a pulse + * of 1. CPOL=3D1 is a clock which idles at 1, and each cycle + * consists of a pulse of 0. + * bit 2: CS_HIGH, if 1, chip select active high, else active low. + * bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB + * first, else LSB first. + * bit 4: LOOP, loopback mode. + * @freq: the transfer speed in Hz. + * @word_delay_ns: delay to be inserted between consecutive words of a + * transfer, in ns unit. + * @cs_setup_ns: delay to be introduced after CS is asserted, in ns + * unit. + * @cs_delay_hold_ns: delay to be introduced before CS is deasserted + * for each transfer, in ns unit. + * @cs_change_delay_inactive_ns: delay to be introduced after CS is + * deasserted and before next asserted, in ns unit. + */ +struct spi_transfer_head { + __u8 chip_select_id; + __u8 bits_per_word; + __u8 cs_change; + __u8 tx_nbits; + __u8 rx_nbits; + __u8 reserved[3]; + __le32 mode; + __le32 freq; + __le32 word_delay_ns; + __le32 cs_setup_ns; + __le32 cs_delay_hold_ns; + __le32 cs_change_delay_inactive_ns; +}; + +/** + * struct spi_transfer_result - virtio SPI transfer result + * @result: Transfer result code. + * VIRTIO_SPI_TRANS_OK: Transfer successful. + * VIRTIO_SPI_PARAM_ERR: Parameter error. + * VIRTIO_SPI_TRANS_ERR: Transfer error. + */ +struct spi_transfer_result { +#define VIRTIO_SPI_TRANS_OK 0 +#define VIRTIO_SPI_PARAM_ERR 1 +#define VIRTIO_SPI_TRANS_ERR 2 + __u8 result; +}; + +#endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */ --=20 2.34.1 From nobody Fri Oct 3 15:33:18 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FCA12D877F; Thu, 28 Aug 2025 09:35:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756373745; cv=none; b=fqoQXp4wn5dk+7oVjGJ2YRZj3kQ3RRLf+xLUJgGm1bFjLXEtEw1+kn6ftIytbHi2BYa+8DQXQFPIbO2QcIcIxqBoWiUEk42VMpgFYzgIGNvbXORZ1RD3EnDPmRbKSJvTGLid0hY2HFhoMZz0ARJy0yTeI3kF/u137aVHkfp6g2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756373745; c=relaxed/simple; bh=/s4A4rTfDO+KWhROfqm/xuLGbfO7JTjRpseI5o/+9gI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SMQCPTXcikBaje0IIxuz12M/p7ZTKdoNzBQBh186flGNGhraG9uS9yWiEE7YHkKIIYMHw6ouYSdaseC8PXI6yCw2635Yub9fHr+Zm0+S2NpGuKbyGwrP9S5LD/L9LRdWJ3Q6nPACRFpb9AkgikVWpxny/pcu8SkbfuFE6vbWXQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=op8sPd/n; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="op8sPd/n" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57S6RlqN016081; Thu, 28 Aug 2025 09:35:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 4vjnwYbSkppv9Ff+FwWfNQ+hVlRbdRoGy5Fw8wQJcEo=; b=op8sPd/n4czFfAAm tIzy2UU6j3Dzo4NGpRU6/MH+LxWzGXfq9rFWz2k8IkqpB7SN/aK/6Yz2uHfbY4KH gNN8esg/RrLC1erxOXNDSdU04+lHT2Vlbsm9IDsriczRexqG7RaJTSLP4TRI12y+ i3MLd7U/Rd0OjbrAgJ2wuyM8WmQ5hAkIE+GWi2x+gwX0o+eio2T258Jc87tuus9K XpLgvbAD7rVYn4ciyvR33/7n8ccFhdn8UOtj3rP5W55AWk7iFQ6/iQw8+5mpkCEF fbHnyGvQiyBWJWXukebMpsBdWWcJpb94arf/p7mmF6De/JGgh7om1m5xH7/nSneT wopXcg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48rtpf214s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Aug 2025 09:35:26 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57S9ZPT8023012 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Aug 2025 09:35:25 GMT Received: from haixcui1-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Thu, 28 Aug 2025 02:35:21 -0700 From: Haixu Cui To: , , , , , , , , , , , CC: , Subject: [PATCH v9 3/3] SPI: Add virtio SPI driver Date: Thu, 28 Aug 2025 17:34:51 +0800 Message-ID: <20250828093451.2401448-4-quic_haixcui@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250828093451.2401448-1-quic_haixcui@quicinc.com> References: <20250828093451.2401448-1-quic_haixcui@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LqXntYiFScYqG80d44WoxHK18P8gpJaD X-Proofpoint-ORIG-GUID: LqXntYiFScYqG80d44WoxHK18P8gpJaD X-Authority-Analysis: v=2.4 cv=Hd8UTjE8 c=1 sm=1 tr=0 ts=68b022de cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=Z4Rwk6OoAAAA:8 a=2J7eYuecm8DdnBpSFfgA:9 a=TjNXssC_j7lpFel5tvFf:22 a=HkZW87K1Qel5hWWM3VKY:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODI1MDE0MiBTYWx0ZWRfX/MWYWQzj2H8l KUnXJc4XRvL3M2kGmMjeSDvl+b7AxWCDI3IP6qrnzOKIMrBZBrvP8AhHfDi+m16uLJ+mkOI7XjX 1ti+XOkXuJH6PTG7gMXr2zpbS28mrCJRdeL2I4dtXCV84+34GyAqdhmdEN3Xoxo5u1XrHUYmsF9 r4y+x5lD6goD37NSK7k0mO0zpgxoKYsF0dXbpSzT8LVyhpryYkO26EhVdrfDB9wYw37eu+1k/3k T9z1QzPlp20g9DoMu1OmUySTpKXuZ2cpOuXt3Ol1eyRwnUPya/DIjLgeGQJo1SaB0vTBlpNy0oV 4Cs/jakgwRwKjJysejjO652TqYLf5yl40H8zxmWWN2K+afi5XUDyk4OQPjCvwe+3JPIdywrF/aA TMHvihhf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-28_02,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 clxscore=1015 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508250142 Content-Type: text/plain; charset="utf-8" This is the virtio SPI Linux kernel driver. Signed-off-by: Haixu Cui --- MAINTAINERS | 1 + drivers/spi/Kconfig | 11 + drivers/spi/Makefile | 1 + drivers/spi/spi-virtio.c | 438 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 451 insertions(+) create mode 100644 drivers/spi/spi-virtio.c diff --git a/MAINTAINERS b/MAINTAINERS index af98e411138d..50f77c0c9d3f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26794,6 +26794,7 @@ VIRTIO SPI DRIVER M: Haixu Cui L: virtualization@lists.linux-foundation.org S: Maintained +F: drivers/spi/spi-virtio.c F: include/uapi/linux/virtio_spi.h =20 VIRTUAL BOX GUEST DEVICE DRIVER diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 891729c9c564..7b609013fb05 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -1224,6 +1224,17 @@ config SPI_UNIPHIER =20 If your SoC supports SCSSI, say Y here. =20 +config SPI_VIRTIO + tristate "Virtio SPI Controller" + depends on SPI_MASTER && VIRTIO + help + If you say yes to this option, support will be included for the virtio + SPI controller driver. The hardware can be emulated by any device model + software according to the virtio protocol. + + This driver can also be built as a module. If so, the module + will be called spi-virtio. + config SPI_XCOMM tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver" depends on I2C diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 062c85989c8c..27a7cf68d55d 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -158,6 +158,7 @@ spi-thunderx-objs :=3D spi-cavium.o spi-cavium-thunde= rx.o obj-$(CONFIG_SPI_THUNDERX) +=3D spi-thunderx.o obj-$(CONFIG_SPI_TOPCLIFF_PCH) +=3D spi-topcliff-pch.o obj-$(CONFIG_SPI_UNIPHIER) +=3D spi-uniphier.o +obj-$(CONFIG_SPI_VIRTIO) +=3D spi-virtio.o obj-$(CONFIG_SPI_XCOMM) +=3D spi-xcomm.o obj-$(CONFIG_SPI_XILINX) +=3D spi-xilinx.o obj-$(CONFIG_SPI_XLP) +=3D spi-xlp.o diff --git a/drivers/spi/spi-virtio.c b/drivers/spi/spi-virtio.c new file mode 100644 index 000000000000..ed0a071e760c --- /dev/null +++ b/drivers/spi/spi-virtio.c @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SPI bus driver for the Virtio SPI controller + * Copyright (C) 2023 OpenSynergy GmbH + * Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VIRTIO_SPI_MODE_MASK \ + (SPI_MODE_X_MASK | SPI_CS_HIGH | SPI_LSB_FIRST) + +struct virtio_spi_req { + struct completion completion; + const u8 *tx_buf; + u8 *rx_buf; + struct spi_transfer_head transfer_head ____cacheline_aligned; + struct spi_transfer_result result; +}; + +struct virtio_spi_priv { + /* The virtio device we're associated with */ + struct virtio_device *vdev; + /* Pointer to the virtqueue */ + struct virtqueue *vq; + /* Copy of config space mode_func_supported */ + u32 mode_func_supported; + /* Copy of config space max_freq_hz */ + u32 max_freq_hz; +}; + +static void virtio_spi_msg_done(struct virtqueue *vq) +{ + struct virtio_spi_req *req; + unsigned int len; + + while ((req =3D virtqueue_get_buf(vq, &len))) + complete(&req->completion); +} + +/* + * virtio_spi_set_delays - Set delay parameters for SPI transfer + * + * This function sets various delay parameters for SPI transfer, + * including delay after CS asserted, timing intervals between + * adjacent words within a transfer, delay before and after CS + * deasserted. It converts these delay parameters to nanoseconds + * using spi_delay_to_ns and stores the results in spi_transfer_head + * structure. + * If the conversion fails, the function logs a warning message and + * returns an error code. + * . . . . . . . . . . + * Delay + A + + B + + C + D + E + F + A + + * . . . . . . . . . . + * ___. . . . . . .___.___. . + * CS# |___.______.____.____.___.___| . |___._____________ + * . . . . . . . . . . + * . . . . . . . . . . + * SCLK__.___.___NNN_____NNN__.___.___.___.___.___.___NNN_______ + * + * NOTE: 1st transfer has two words, the delay between these two words are + * 'B' in the diagram. + * + * A =3D> struct spi_device -> cs_setup + * B =3D> max{struct spi_transfer -> word_delay, struct spi_device -> word= _delay} + * Note: spi_device and spi_transfer both have word_delay, Linux + * choose the bigger one, refer to _spi_xfer_word_delay_update fun= ction + * C =3D> struct spi_transfer -> delay + * D =3D> struct spi_device -> cs_hold + * E =3D> struct spi_device -> cs_inactive + * F =3D> struct spi_transfer -> cs_change_delay + * + * So the corresponding relationship: + * A <=3D=3D=3D> cs_setup_ns (after CS asserted) + * B <=3D=3D=3D> word_delay_ns (delay between adjacent words within a tr= ansfer) + * C+D <=3D=3D=3D> cs_delay_hold_ns (before CS deasserted) + * E+F <=3D=3D=3D> cs_change_delay_inactive_ns (after CS deasserted, these= two + * values are also recommended in the Linux driver to be added up) + */ +static int virtio_spi_set_delays(struct spi_transfer_head *th, + struct spi_device *spi, + struct spi_transfer *xfer) +{ + int cs_setup; + int cs_word_delay_xfer; + int cs_word_delay_spi; + int delay; + int cs_hold; + int cs_inactive; + int cs_change_delay; + + cs_setup =3D spi_delay_to_ns(&spi->cs_setup, xfer); + if (cs_setup < 0) { + dev_warn(&spi->dev, "Cannot convert cs_setup\n"); + return cs_setup; + } + th->cs_setup_ns =3D cpu_to_le32(cs_setup); + + cs_word_delay_xfer =3D spi_delay_to_ns(&xfer->word_delay, xfer); + if (cs_word_delay_xfer < 0) { + dev_warn(&spi->dev, "Cannot convert cs_word_delay_xfer\n"); + return cs_word_delay_xfer; + } + cs_word_delay_spi =3D spi_delay_to_ns(&spi->word_delay, xfer); + if (cs_word_delay_spi < 0) { + dev_warn(&spi->dev, "Cannot convert cs_word_delay_spi\n"); + return cs_word_delay_spi; + } + + th->word_delay_ns =3D cpu_to_le32(max(cs_word_delay_spi, cs_word_delay_xf= er)); + + delay =3D spi_delay_to_ns(&xfer->delay, xfer); + if (delay < 0) { + dev_warn(&spi->dev, "Cannot convert delay\n"); + return delay; + } + cs_hold =3D spi_delay_to_ns(&spi->cs_hold, xfer); + if (cs_hold < 0) { + dev_warn(&spi->dev, "Cannot convert cs_hold\n"); + return cs_hold; + } + th->cs_delay_hold_ns =3D cpu_to_le32(delay + cs_hold); + + cs_inactive =3D spi_delay_to_ns(&spi->cs_inactive, xfer); + if (cs_inactive < 0) { + dev_warn(&spi->dev, "Cannot convert cs_inactive\n"); + return cs_inactive; + } + cs_change_delay =3D spi_delay_to_ns(&xfer->cs_change_delay, xfer); + if (cs_change_delay < 0) { + dev_warn(&spi->dev, "Cannot convert cs_change_delay\n"); + return cs_change_delay; + } + th->cs_change_delay_inactive_ns =3D + cpu_to_le32(cs_inactive + cs_change_delay); + + return 0; +} + +static int virtio_spi_transfer_one(struct spi_controller *ctrl, + struct spi_device *spi, + struct spi_transfer *xfer) +{ + struct virtio_spi_priv *priv =3D spi_controller_get_devdata(ctrl); + struct virtio_spi_req *spi_req __free(kfree); + struct spi_transfer_head *th; + struct scatterlist sg_out_head, sg_out_payload; + struct scatterlist sg_in_result, sg_in_payload; + struct scatterlist *sgs[4]; + unsigned int outcnt =3D 0; + unsigned int incnt =3D 0; + int ret; + + spi_req =3D kzalloc(sizeof(*spi_req), GFP_KERNEL); + if (!spi_req) + return -ENOMEM; + + init_completion(&spi_req->completion); + + th =3D &spi_req->transfer_head; + + /* Fill struct spi_transfer_head */ + th->chip_select_id =3D spi_get_chipselect(spi, 0); + th->bits_per_word =3D spi->bits_per_word; + th->cs_change =3D xfer->cs_change; + th->tx_nbits =3D xfer->tx_nbits; + th->rx_nbits =3D xfer->rx_nbits; + th->reserved[0] =3D 0; + th->reserved[1] =3D 0; + th->reserved[2] =3D 0; + + static_assert(VIRTIO_SPI_CPHA =3D=3D SPI_CPHA, + "VIRTIO_SPI_CPHA must match SPI_CPHA"); + static_assert(VIRTIO_SPI_CPOL =3D=3D SPI_CPOL, + "VIRTIO_SPI_CPOL must match SPI_CPOL"); + static_assert(VIRTIO_SPI_CS_HIGH =3D=3D SPI_CS_HIGH, + "VIRTIO_SPI_CS_HIGH must match SPI_CS_HIGH"); + static_assert(VIRTIO_SPI_MODE_LSB_FIRST =3D=3D SPI_LSB_FIRST, + "VIRTIO_SPI_MODE_LSB_FIRST must match SPI_LSB_FIRST"); + + th->mode =3D cpu_to_le32(spi->mode & VIRTIO_SPI_MODE_MASK); + if (spi->mode & SPI_LOOP) + th->mode |=3D cpu_to_le32(VIRTIO_SPI_MODE_LOOP); + + th->freq =3D cpu_to_le32(xfer->speed_hz); + + ret =3D virtio_spi_set_delays(th, spi, xfer); + if (ret) + goto msg_done; + + /* Set buffers */ + spi_req->tx_buf =3D xfer->tx_buf; + spi_req->rx_buf =3D xfer->rx_buf; + + /* Prepare sending of virtio message */ + init_completion(&spi_req->completion); + + sg_init_one(&sg_out_head, th, sizeof(*th)); + sgs[outcnt] =3D &sg_out_head; + outcnt++; + + if (spi_req->tx_buf) { + sg_init_one(&sg_out_payload, spi_req->tx_buf, xfer->len); + sgs[outcnt] =3D &sg_out_payload; + outcnt++; + } + + if (spi_req->rx_buf) { + sg_init_one(&sg_in_payload, spi_req->rx_buf, xfer->len); + sgs[outcnt] =3D &sg_in_payload; + incnt++; + } + + sg_init_one(&sg_in_result, &spi_req->result, + sizeof(struct spi_transfer_result)); + sgs[outcnt + incnt] =3D &sg_in_result; + incnt++; + + ret =3D virtqueue_add_sgs(priv->vq, sgs, outcnt, incnt, spi_req, + GFP_KERNEL); + if (ret) + goto msg_done; + + /* Simple implementation: There can be only one transfer in flight */ + virtqueue_kick(priv->vq); + + wait_for_completion(&spi_req->completion); + + /* Read result from message and translate return code */ + switch (spi_req->result.result) { + case VIRTIO_SPI_TRANS_OK: + break; + case VIRTIO_SPI_PARAM_ERR: + ret =3D -EINVAL; + break; + case VIRTIO_SPI_TRANS_ERR: + ret =3D -EIO; + break; + default: + ret =3D -EIO; + break; + } + +msg_done: + if (ret) + ctrl->cur_msg->status =3D ret; + + return ret; +} + +static void virtio_spi_read_config(struct virtio_device *vdev) +{ + struct spi_controller *ctrl =3D dev_get_drvdata(&vdev->dev); + struct virtio_spi_priv *priv =3D vdev->priv; + u8 cs_max_number; + u8 tx_nbits_supported; + u8 rx_nbits_supported; + + cs_max_number =3D virtio_cread8(vdev, offsetof(struct virtio_spi_config, + cs_max_number)); + ctrl->num_chipselect =3D cs_max_number; + + /* Set the mode bits which are understood by this driver */ + priv->mode_func_supported =3D + virtio_cread32(vdev, offsetof(struct virtio_spi_config, + mode_func_supported)); + ctrl->mode_bits =3D priv->mode_func_supported & + (VIRTIO_SPI_CS_HIGH | VIRTIO_SPI_MODE_LSB_FIRST); + if (priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_CPHA_1) + ctrl->mode_bits |=3D VIRTIO_SPI_CPHA; + if (priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_CPOL_1) + ctrl->mode_bits |=3D VIRTIO_SPI_CPOL; + if (priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_LSB_FIRST) + ctrl->mode_bits |=3D SPI_LSB_FIRST; + if (priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_LOOPBACK) + ctrl->mode_bits |=3D SPI_LOOP; + tx_nbits_supported =3D + virtio_cread8(vdev, offsetof(struct virtio_spi_config, + tx_nbits_supported)); + if (tx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_DUAL) + ctrl->mode_bits |=3D SPI_TX_DUAL; + if (tx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_QUAD) + ctrl->mode_bits |=3D SPI_TX_QUAD; + if (tx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_OCTAL) + ctrl->mode_bits |=3D SPI_TX_OCTAL; + rx_nbits_supported =3D + virtio_cread8(vdev, offsetof(struct virtio_spi_config, + rx_nbits_supported)); + if (rx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_DUAL) + ctrl->mode_bits |=3D SPI_RX_DUAL; + if (rx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_QUAD) + ctrl->mode_bits |=3D SPI_RX_QUAD; + if (rx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_OCTAL) + ctrl->mode_bits |=3D SPI_RX_OCTAL; + + ctrl->bits_per_word_mask =3D + virtio_cread32(vdev, offsetof(struct virtio_spi_config, + bits_per_word_mask)); + + priv->max_freq_hz =3D + virtio_cread32(vdev, offsetof(struct virtio_spi_config, + max_freq_hz)); +} + +static int virtio_spi_find_vqs(struct virtio_spi_priv *priv) +{ + struct virtqueue *vq; + + vq =3D virtio_find_single_vq(priv->vdev, virtio_spi_msg_done, "spi-rq"); + if (IS_ERR(vq)) + return PTR_ERR(vq); + priv->vq =3D vq; + return 0; +} + +/* Function must not be called before virtio_spi_find_vqs() has been run */ +static void virtio_spi_del_vq(void *data) +{ + struct virtio_device *vdev =3D data; + + virtio_reset_device(vdev); + vdev->config->del_vqs(vdev); +} + +static int virtio_spi_probe(struct virtio_device *vdev) +{ + struct virtio_spi_priv *priv; + struct spi_controller *ctrl; + int ret; + u32 bus_num; + + ctrl =3D devm_spi_alloc_host(&vdev->dev, sizeof(*priv)); + if (!ctrl) + return -ENOMEM; + + priv =3D spi_controller_get_devdata(ctrl); + priv->vdev =3D vdev; + vdev->priv =3D priv; + + device_set_node(&ctrl->dev, dev_fwnode(&vdev->dev)); + + dev_set_drvdata(&vdev->dev, ctrl); + + ret =3D device_property_read_u32(&vdev->dev, "spi,bus-num", &bus_num); + if (ret || bus_num > S16_MAX) + ctrl->bus_num =3D -1; + else + ctrl->bus_num =3D bus_num; + + virtio_spi_read_config(vdev); + + ctrl->transfer_one =3D virtio_spi_transfer_one; + + ret =3D virtio_spi_find_vqs(priv); + if (ret) + return dev_err_probe(&vdev->dev, ret, "Cannot setup virtqueues\n"); + + /* Register cleanup for virtqueues using devm */ + ret =3D devm_add_action_or_reset(&vdev->dev, virtio_spi_del_vq, vdev); + if (ret) + return dev_err_probe(&vdev->dev, ret, "Cannot register virtqueue cleanup= \n"); + + /* Use devm version to register controller */ + ret =3D devm_spi_register_controller(&vdev->dev, ctrl); + if (ret) + return dev_err_probe(&vdev->dev, ret, "Cannot register controller\n"); + + return 0; +} + +static int virtio_spi_freeze(struct device *dev) +{ + struct spi_controller *ctrl =3D dev_get_drvdata(dev); + struct virtio_device *vdev =3D dev_to_virtio(dev); + int ret; + + ret =3D spi_controller_suspend(ctrl); + if (ret) { + dev_warn(dev, "cannot suspend controller (%d)\n", ret); + return ret; + } + + virtio_spi_del_vq(vdev); + return 0; +} + +static int virtio_spi_restore(struct device *dev) +{ + struct spi_controller *ctrl =3D dev_get_drvdata(dev); + struct virtio_device *vdev =3D dev_to_virtio(dev); + int ret; + + ret =3D virtio_spi_find_vqs(vdev->priv); + if (ret) { + dev_err(dev, "problem starting vqueue (%d)\n", ret); + return ret; + } + + ret =3D spi_controller_resume(ctrl); + if (ret) + dev_err(dev, "problem resuming controller (%d)\n", ret); + + return ret; +} + +static struct virtio_device_id virtio_spi_id_table[] =3D { + { VIRTIO_ID_SPI, VIRTIO_DEV_ANY_ID }, + {} +}; +MODULE_DEVICE_TABLE(virtio, virtio_spi_id_table); + +static const struct dev_pm_ops virtio_spi_pm_ops =3D { + .freeze =3D pm_sleep_ptr(virtio_spi_freeze), + .restore =3D pm_sleep_ptr(virtio_spi_restore), +}; + +static struct virtio_driver virtio_spi_driver =3D { + .driver =3D { + .name =3D KBUILD_MODNAME, + .pm =3D &virtio_spi_pm_ops, + }, + .id_table =3D virtio_spi_id_table, + .probe =3D virtio_spi_probe, +}; +module_virtio_driver(virtio_spi_driver); + +MODULE_AUTHOR("OpenSynergy GmbH"); +MODULE_AUTHOR("Haixu Cui "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Virtio SPI bus driver"); --=20 2.34.1