From nobody Fri Oct 3 18:02:33 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1246F283C90; Thu, 28 Aug 2025 08:09:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756368557; cv=none; b=NQiDqSumADKuwckG9IFhLj4rjF16GulJRNz9aRyEagJOZ+4MC97E2RKNksCsGsAQCrTeg+TmyqzsRTQYqX8kNqfgdKX3cH38ycrpGl1SlZ881DXr84qkXFDOv4SfSbN6LDYByuUv+Uhl4OSCyWfiE+KCBheVCUjDmevjfsLYLJQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756368557; c=relaxed/simple; bh=Mmb1QytaNv3D//4/rAiKFulLEUdrSvtYGwxBhEBX41I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Aj0H34EjA0kBdQGDzfVlkFqy4Tzvj5Q5lFz91CPKDiD4NCCIIs+TR2ChPuG3dg/bPXzf/myoyzbWBH4xtaP+Ef563HhVQTuM3JktxBLc9s6mi+Jkeunjw7zUXUqXAwIJITcIaMzUxTeS12qa6ZyuM1eByIqd99vrmX7lFpvXo4M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=sa7vJycf; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="sa7vJycf" X-UUID: 43cef0c883e611f0b33aeb1e7f16c2b6-20250828 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=M6gmJzsdJUvVF4bx9MOU4xf8vGZe8xcFkwSgo8UXAAk=; b=sa7vJycfq7anLPxEZKeEFc9QEW1Uc938LilIwxhdmI2VBzm5FznRqeM3wbzH2BpNbFDuwFYTs2lAUNg3s9llImtIDXu9285XhCfqkV5fDwDbx6Vyyl78E2lpImkv8mJe7uQ2vR9x7lEqSSPSvTyP/ah9LU/HJAWEJ+QtYxFczAY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:6a9c6680-0816-4cbd-89e4-331196f34d07,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:f1326cf,CLOUDID:489bb36d-c2f4-47a6-876f-59a53e9ecc6e,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 43cef0c883e611f0b33aeb1e7f16c2b6-20250828 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 352571798; Thu, 28 Aug 2025 16:09:05 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 28 Aug 2025 16:09:03 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 28 Aug 2025 16:09:04 +0800 From: Paul Chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 07/19] soc: mediatek: add mmsys support for MT8196 Date: Thu, 28 Aug 2025 16:07:02 +0800 Message-ID: <20250828080855.3502514-8-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> References: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nancy Lin Add driver data for MT8196 and add the routing table for each mmsys. Signed-off-by: Nancy Lin Signed-off-by: Paul-pl Chen --- drivers/soc/mediatek/mt8196-mmsys.h | 396 +++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 54 ++++ include/linux/soc/mediatek/mtk-mmsys.h | 52 ++++ 3 files changed, 502 insertions(+) create mode 100644 drivers/soc/mediatek/mt8196-mmsys.h diff --git a/drivers/soc/mediatek/mt8196-mmsys.h b/drivers/soc/mediatek/mt8= 196-mmsys.h new file mode 100644 index 000000000000..63b14b446d08 --- /dev/null +++ b/drivers/soc/mediatek/mt8196-mmsys.h @@ -0,0 +1,396 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Nancy Lin + */ + +#ifndef __SOC_MEDIATEK_MT8196_MMSYS_H +#define __SOC_MEDIATEK_MT8196_MMSYS_H + +/* DISPSYS1 */ +#define MT8196_COMP_OUT_CB6_MOUT_EN 0xd30 +#define MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB0 BIT(0) +#define MT8196_COMP_OUT_CB7_MOUT_EN 0xd38 +#define MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB1 BIT(1) +#define MT8196_COMP_OUT_CB8_MOUT_EN 0xd40 +#define MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2 BIT(2) +#define MT8196_MERGE_OUT_CB0_MOUT_EN 0xdcc +#define MT8196_DISP_COMP_OUT_CB_TO_DVO0 BIT(9) +#define MT8196_MERGE_OUT_CB1_MOUT_EN 0xdd4 +#define MT8196_MERGE_OUT_CB2_MOUT_EN 0xddc +#define MT8196_DISP_COMP_OUT_CB_TO_DSI0 BIT(0) +#define MT8196_DISP_COMP_OUT_CB_TO_DP_INTF0 BIT(10) +#define MT8196_DISP_COMP_OUT_CB_TO_DP_INTF1 BIT(11) +#define MT8196_SPLITTER_IN_CB1_MOUT_EN 0xeac +#define MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB9 BIT(5) +#define MT8196_SPLITTER_IN_CB2_MOUT_EN 0xeb4 +#define MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB10 BIT(6) +#define MT8196_SPLITTER_IN_CB3_MOUT_EN 0xebc +#define MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11 BIT(7) +#define MT8196_SPLITTER_OUT_CB9_MOUT_EN 0xf64 +#define MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB6 BIT(10) +#define MT8196_SPLITTER_OUT_CB10_MOUT_EN 0xf6c +#define MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB7 BIT(11) +#define MT8196_SPLITTER_OUT_CB11_MOUT_EN 0xf74 +#define MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8 BIT(12) +#define MT8196_OVL_RSZ_IN_CB2_MOUT_EN 0xf70 +#define MT8196_DISP_OVL_EXDMA2_1_TO_OVL_EXDMA_OUT_CB3 BIT(1) + +/* OVLSYS */ +#define MT8196_OVL_BLENDER_OUT_CB4_MOUT_EN 0xe10 +#define MT8196_OVL_BLENDER_OUT_CB8_MOUT_EN 0xe20 +#define MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC0 BIT(0) +#define MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC1 BIT(1) +#define MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC2 BIT(2) +#define MT8196_OVL_EXDMA_OUT_CB2_MOUT_EN 0xe60 +#define MT8196_OVL_EXDMA_OUT_CB3_MOUT_EN 0xe68 +#define MT8196_OVL_EXDMA_OUT_CB4_MOUT_EN 0xe70 +#define MT8196_OVL_EXDMA_OUT_CB5_MOUT_EN 0xe78 +#define MT8196_OVL_EXDMA_OUT_CB6_MOUT_EN 0xe80 +#define MT8196_OVL_EXDMA_OUT_CB7_MOUT_EN 0xe88 +#define MT8196_OVL_EXDMA_OUT_CB8_MOUT_EN 0xe90 +#define MT8196_OVL_EXDMA_OUT_CB9_MOUT_EN 0xe98 +#define MT8196_OVL_EXDMA_OUT_CB10_MOUT_EN 0xea0 +#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER1 BIT(2) +#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER2 BIT(3) +#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER3 BIT(4) +#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER4 BIT(5) +#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER5 BIT(6) +#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER6 BIT(7) +#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER7 BIT(8) +#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER8 BIT(9) +#define MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER9 BIT(10) +#define MT8196_OVL_OUTPROC_OUT_CB0_MOUT_EN 0xf10 +#define MT8196_OVL_OUTPROC_OUT_CB1_MOUT_EN 0xf14 +#define MT8196_OVL_OUTPROC_OUT_CB2_MOUT_EN 0xf18 +#define MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY5 BIT(0) +#define MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY6 BIT(1) +#define MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY7 BIT(2) + +/* DISPSYS0 */ +#define MT8196_PANEL_COMP_OUT_CB1_MOUT_EN 0xd84 +#define MT8196_DISP_TO_DLO_RELAY1 BIT(1) +#define MT8196_PANEL_COMP_OUT_CB2_MOUT_EN 0xd88 +#define MT8196_DISP_TO_DLO_RELAY2 BIT(2) +#define MT8196_PANEL_COMP_OUT_CB3_MOUT_EN 0xd8c +#define MT8196_DISP_TO_DLO_RELAY3 BIT(3) +#define MT8196_PQ_IN_CB0_MOUT_EN 0xdd0 +#define MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6 BIT(2) + +#define MT8196_PQ_IN_CB1_MOUT_EN 0xdd4 +#define MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7 BIT(3) +#define MT8196_PQ_IN_CB8_MOUT_EN 0xdf0 +#define MT8196_PQ_IN_CB8_TO_PQ_OUT_CB_8 BIT(4) +#define MT8196_PQ_OUT_CB6_MOUT_EN 0xe54 +#define MT8196_PQ_OUT_CB6_TO_PANEL0_COMP_OUT_CB1 BIT(1) +#define MT8196_PQ_OUT_CB7_MOUT_EN 0xe58 +#define MT8196_PQ_OUT_CB7_TO_PANEL0_COMP_OUT_CB2 BIT(2) +#define MT8196_PQ_OUT_CB8_MOUT_EN 0xe5c +#define MT8196_PQ_OUT_CB8_TO_PANEL0_COMP_OUT_CB3 BIT(3) + +/* OVLSYS config */ +#define MT8196_OVL_INT_MERGE 0x008 +#define MT8196_OVL_DL_OUT_RELAY5_SIZE 0x29c +#define MT8196_OVL_DL_OUT_RELAY6_SIZE 0x2a0 +#define MT8196_OVLSYS_GCE_EVENT_SEL 0x408 +#define MT8196_OVLSYS_BYPASS_MUX_SHADOW 0xca0 +#define MT8196_OVLSYS_CB_CON 0xcac +#define MT8196_CB_BYPASS_MUX_SHADOW (0xff << 16) +#define MT8196_EVENT_GCE_EN (BIT(0) | BIT(1)) + +/* DISPSYS config */ +#define MT8196_DISP0_DLI_RELAY0 0x200 +#define MT8196_DISP0_DLI_RELAY1 0x204 +#define MT8196_DISP0_DLI_RELAY8 0x220 +#define MT8196_DISP0_DLO_RELAY1 0x268 +#define MT8196_DISP0_DLO_RELAY2 0x26c +#define MT8196_DISP0_DLO_RELAY3 0x270 +#define MT8196_DLI_RELAY_1T2P BIT(30) +#define MT8196_DISP0_BYPASS_MUX_SHADOW 0xc30 +#define MT8196_BYPASS_MUX_SHADOW BIT(0) +#define MT8196_OVLSYS_CB_BYPASS_MUX_SHADOW (0xff << 16) + +/* DISPSYS1 config */ +#define MT8196_DISP1_INT_MERGE 0x008 +#define MT8196_DISP1_DLI_RELAY21 0x204 +#define MT8196_DISP1_DLI_RELAY22 0x208 +#define MT8196_DISP1_DLI_RELAY23 0x20c +#define MT8196_DISP1_GCE_FRAME_DONE_SEL0 0xa10 +#define MT8196_DISP1_GCE_FRAME_DONE_SEL1 0xa14 +#define MT8196_FRAME_DONE_DVO 25 +#define MT8196_FRAME_DONE_DP_INTF0 41 +#define MT8196_DISP1_BYPASS_MUX_SHADOW 0xcf8 + +/* VDISP_AO config */ +#define MT8196_VDISP_AO_REG_INTEN 0x000 +#define MT8196_CPU_INTEN BIT(0) +#define MT8196_CPU_INT_MERGE BIT(4) +#define MT8196_VDISP_AO_REG_INT_SEL_G0 0x020 +#define MT8196_VDISP_AO_REG_INT_SEL_G1 0x024 +#define MT8196_VDISP_AO_REG_INT_SEL_G2 0x028 +#define MT8196_VDISP_AO_REG_INT_SEL_G3 0x02c +#define MT8196_VDISP_AO_REG_INT_SEL_G4 0x030 +#define MT8196_VDISP_AO_REG_INT_SEL_G5 0x034 +#define MT8196_VDISP_AO_REG_INT_SEL_G6 0x038 +#define MT8196_IRQ_TABLE_OVL0_OUTPROC0 (0xa6) /* GIC 450 */ +#define MT8196_IRQ_TABLE_OVL0_OUTPROC1 (0xa7) /* GIC 451 */ +#define MT8196_IRQ_TABLE_OVL1_OUTPROC0 (0xd6) /* GIC 452 */ +#define MT8196_IRQ_TABLE_DSI0 (0x35) /* GIC 453 */ + +static const struct mtk_mmsys_async_info mmsys_mt8196_ovl0_async_comp_tabl= e[] =3D { + {DDP_COMPONENT_OVL0_DLO_ASYNC5, 0, MT8196_OVL_DL_OUT_RELAY5_SIZE, GENMASK= (29, 0)}, + {DDP_COMPONENT_OVL0_DLO_ASYNC6, 1, MT8196_OVL_DL_OUT_RELAY6_SIZE, GENMASK= (29, 0)}, +}; + +static const struct mtk_mmsys_async_info mmsys_mt8196_ovl1_async_comp_tabl= e[] =3D { + {DDP_COMPONENT_OVL1_DLO_ASYNC5, 0, MT8196_OVL_DL_OUT_RELAY5_SIZE, GENMASK= (29, 0)}, + {DDP_COMPONENT_OVL1_DLO_ASYNC6, 1, MT8196_OVL_DL_OUT_RELAY6_SIZE, GENMASK= (29, 0)}, +}; + +static const struct mtk_mmsys_async_info mmsys_mt8196_disp0_async_comp_tab= le[] =3D { + {DDP_COMPONENT_DLI_ASYNC0, 0, MT8196_DISP0_DLI_RELAY0, GENMASK(29, 0)}, + {DDP_COMPONENT_DLI_ASYNC1, 1, MT8196_DISP0_DLI_RELAY1, GENMASK(29, 0)}, + {DDP_COMPONENT_DLI_ASYNC8, 2, MT8196_DISP0_DLI_RELAY8, GENMASK(29, 0)}, + {DDP_COMPONENT_DLO_ASYNC1, 3, MT8196_DISP0_DLO_RELAY1, GENMASK(29, 0)}, + {DDP_COMPONENT_DLO_ASYNC2, 4, MT8196_DISP0_DLO_RELAY2, GENMASK(29, 0)}, + {DDP_COMPONENT_DLO_ASYNC3, 5, MT8196_DISP0_DLO_RELAY3, GENMASK(29, 0)}, +}; + +static const struct mtk_mmsys_async_info mmsys_mt8196_disp1_async_comp_tab= le[] =3D { + {DDP_COMPONENT_DLI_ASYNC21, 0, MT8196_DISP1_DLI_RELAY21, GENMASK(29, 0)}, + {DDP_COMPONENT_DLI_ASYNC22, 1, MT8196_DISP1_DLI_RELAY22, GENMASK(29, 0)}, + {DDP_COMPONENT_DLI_ASYNC23, 2, MT8196_DISP1_DLI_RELAY23, GENMASK(29, 0)}, +}; + +static const struct mtk_mmsys_default mmsys_mt8196_vdisp_ao_default_table[= ] =3D { + {MT8196_VDISP_AO_REG_INTEN, MT8196_CPU_INTEN, MT8196_CPU_INT_MERGE | MT81= 96_CPU_INTEN}, + {MT8196_VDISP_AO_REG_INT_SEL_G0, MT8196_IRQ_TABLE_OVL0_OUTPROC0, GENMASK(= 7, 0)}, + {MT8196_VDISP_AO_REG_INT_SEL_G0, MT8196_IRQ_TABLE_OVL0_OUTPROC1 << 8, GEN= MASK(15, 8)}, + {MT8196_VDISP_AO_REG_INT_SEL_G0, MT8196_IRQ_TABLE_OVL1_OUTPROC0 << 16, GE= NMASK(23, 16)}, + {MT8196_VDISP_AO_REG_INT_SEL_G0, MT8196_IRQ_TABLE_DSI0 << 24, GENMASK(31,= 24)} +}; + +static const struct mtk_mmsys_default mmsys_mt8196_ovl0_default_table[] = =3D { + {MT8196_OVLSYS_GCE_EVENT_SEL, MT8196_EVENT_GCE_EN, GENMASK(1, 0)}, + {MT8196_OVL_INT_MERGE, 0, BIT(0)}, + {MT8196_OVLSYS_BYPASS_MUX_SHADOW, + MT8196_BYPASS_MUX_SHADOW, MT8196_BYPASS_MUX_SHADOW}, + {MT8196_OVLSYS_CB_CON, MT8196_OVLSYS_CB_BYPASS_MUX_SHADOW, + MT8196_OVLSYS_CB_BYPASS_MUX_SHADOW}, +}; + +static const struct mtk_mmsys_default mmsys_mt8196_disp0_default_table[] = =3D { + {MT8196_OVLSYS_GCE_EVENT_SEL, MT8196_EVENT_GCE_EN, GENMASK(1, 0)}, + {MT8196_DISP0_BYPASS_MUX_SHADOW, + MT8196_CB_BYPASS_MUX_SHADOW | MT8196_BYPASS_MUX_SHADOW, + MT8196_CB_BYPASS_MUX_SHADOW | MT8196_BYPASS_MUX_SHADOW}, + {MT8196_DISP0_DLI_RELAY0, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)}, + {MT8196_DISP0_DLI_RELAY1, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)}, + {MT8196_DISP0_DLI_RELAY8, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)}, + {MT8196_DISP0_DLO_RELAY1, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)}, + {MT8196_DISP0_DLO_RELAY2, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)}, + {MT8196_DISP0_DLO_RELAY3, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)}, +}; + +static const struct mtk_mmsys_default mmsys_mt8196_disp1_default_table[] = =3D { + {MT8196_OVLSYS_GCE_EVENT_SEL, MT8196_EVENT_GCE_EN, GENMASK(1, 0)}, + {MT8196_DISP1_INT_MERGE, 0, BIT(0)}, + {MT8196_DISP1_BYPASS_MUX_SHADOW, + MT8196_CB_BYPASS_MUX_SHADOW | MT8196_BYPASS_MUX_SHADOW, + MT8196_CB_BYPASS_MUX_SHADOW | MT8196_BYPASS_MUX_SHADOW}, + {MT8196_DISP1_DLI_RELAY21, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)}, + {MT8196_DISP1_DLI_RELAY22, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)}, + {MT8196_DISP1_DLI_RELAY23, MT8196_DLI_RELAY_1T2P, GENMASK(31, 30)}, + {MT8196_DISP1_GCE_FRAME_DONE_SEL0, MT8196_FRAME_DONE_DVO, GENMASK(5, 0)}, + {MT8196_DISP1_GCE_FRAME_DONE_SEL1, MT8196_FRAME_DONE_DP_INTF0, GENMASK(5,= 0)}, +}; + +static const struct mtk_mmsys_routes mmsys_mt8196_ovl0_routing_table[] =3D= { + MMSYS_ROUTE(OVL0_EXDMA2, OVL0_BLENDER1, + MT8196_OVL_RSZ_IN_CB2_MOUT_EN, MT8196_DISP_OVL_EXDMA2_1_TO_OVL_EXDMA= _OUT_CB3, + MT8196_DISP_OVL_EXDMA2_1_TO_OVL_EXDMA_OUT_CB3), + MMSYS_ROUTE(OVL0_EXDMA2, OVL0_BLENDER1, + MT8196_OVL_EXDMA_OUT_CB3_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER1, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER1), + MMSYS_ROUTE(OVL0_EXDMA3, OVL0_BLENDER2, + MT8196_OVL_EXDMA_OUT_CB4_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER2, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER2), + MMSYS_ROUTE(OVL0_EXDMA4, OVL0_BLENDER3, + MT8196_OVL_EXDMA_OUT_CB5_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER3, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER3), + MMSYS_ROUTE(OVL0_EXDMA5, OVL0_BLENDER4, + MT8196_OVL_EXDMA_OUT_CB6_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER4, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER4), + MMSYS_ROUTE(OVL0_EXDMA6, OVL0_BLENDER5, + MT8196_OVL_EXDMA_OUT_CB7_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER5, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER5), + MMSYS_ROUTE(OVL0_EXDMA7, OVL0_BLENDER6, + MT8196_OVL_EXDMA_OUT_CB8_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER6, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER6), + MMSYS_ROUTE(OVL0_EXDMA8, OVL0_BLENDER7, + MT8196_OVL_EXDMA_OUT_CB9_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER7, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER7), + MMSYS_ROUTE(OVL0_EXDMA9, OVL0_BLENDER8, + MT8196_OVL_EXDMA_OUT_CB10_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_O= VL_BLENDER8, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER8), + MMSYS_ROUTE(OVL0_BLENDER4, OVL0_OUTPROC0, + MT8196_OVL_BLENDER_OUT_CB4_MOUT_EN, MT8196_DISP_OUT_BLENDER_CB_TO_OV= L_OUTPROC0, + MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC0), + MMSYS_ROUTE(OVL0_BLENDER8, OVL0_OUTPROC1, + MT8196_OVL_BLENDER_OUT_CB8_MOUT_EN, MT8196_DISP_OUT_BLENDER_CB_TO_OV= L_OUTPROC1, + MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC1), + MMSYS_ROUTE(OVL0_OUTPROC0, OVL0_DLO_ASYNC5, + MT8196_OVL_OUTPROC_OUT_CB0_MOUT_EN, + MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY5, + MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY5), + MMSYS_ROUTE(OVL0_OUTPROC1, OVL0_DLO_ASYNC6, + MT8196_OVL_OUTPROC_OUT_CB1_MOUT_EN, + MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY6, + MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY6) +}; + +static const struct mtk_mmsys_routes mmsys_mt8196_ovl1_routing_table[] =3D= { + MMSYS_ROUTE(OVL1_EXDMA2, OVL1_BLENDER1, + MT8196_OVL_RSZ_IN_CB2_MOUT_EN, MT8196_DISP_OVL_EXDMA2_1_TO_OVL_EXDMA= _OUT_CB3, + MT8196_DISP_OVL_EXDMA2_1_TO_OVL_EXDMA_OUT_CB3), + MMSYS_ROUTE(OVL1_EXDMA2, OVL1_BLENDER1, + MT8196_OVL_EXDMA_OUT_CB3_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER1, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER1), + MMSYS_ROUTE(OVL1_EXDMA3, OVL1_BLENDER2, + MT8196_OVL_EXDMA_OUT_CB4_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER2, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER2), + MMSYS_ROUTE(OVL1_EXDMA4, OVL1_BLENDER3, + MT8196_OVL_EXDMA_OUT_CB5_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER3, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER3), + MMSYS_ROUTE(OVL1_EXDMA5, OVL1_BLENDER4, + MT8196_OVL_EXDMA_OUT_CB6_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER4, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER4), + MMSYS_ROUTE(OVL1_EXDMA6, OVL1_BLENDER5, + MT8196_OVL_EXDMA_OUT_CB7_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER5, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER5), + MMSYS_ROUTE(OVL1_EXDMA7, OVL1_BLENDER6, + MT8196_OVL_EXDMA_OUT_CB8_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER6, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER6), + MMSYS_ROUTE(OVL1_EXDMA8, OVL1_BLENDER7, + MT8196_OVL_EXDMA_OUT_CB9_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OV= L_BLENDER7, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER7), + MMSYS_ROUTE(OVL1_EXDMA9, OVL1_BLENDER8, + MT8196_OVL_EXDMA_OUT_CB10_MOUT_EN, MT8196_DISP_OVL_EXDMA_OUT_CB_TO_O= VL_BLENDER8, + MT8196_DISP_OVL_EXDMA_OUT_CB_TO_OVL_BLENDER8), + MMSYS_ROUTE(OVL1_BLENDER4, OVL1_OUTPROC0, + MT8196_OVL_BLENDER_OUT_CB4_MOUT_EN, MT8196_DISP_OUT_BLENDER_CB_TO_OV= L_OUTPROC0, + MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC0), + MMSYS_ROUTE(OVL1_BLENDER8, OVL1_OUTPROC1, + MT8196_OVL_BLENDER_OUT_CB8_MOUT_EN, MT8196_DISP_OUT_BLENDER_CB_TO_OV= L_OUTPROC1, + MT8196_DISP_OUT_BLENDER_CB_TO_OVL_OUTPROC1), + MMSYS_ROUTE(OVL1_OUTPROC0, OVL1_DLO_ASYNC5, + MT8196_OVL_OUTPROC_OUT_CB0_MOUT_EN, + MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY5, + MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY5), + MMSYS_ROUTE(OVL1_OUTPROC1, OVL1_DLO_ASYNC6, + MT8196_OVL_OUTPROC_OUT_CB1_MOUT_EN, + MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY6, + MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY6) +}; + +/* + * main: DLI_ASYNC0-> PQ_IN_CB0 -> PQ_OUT_CB6 -> PANEL_COMP_OUT_CB1 -> DLO= _ASYNC1 + * ext: DLI_ASYNC1-> PQ_IN_CB1 -> PQ_OUT_CB7 -> PANEL_COMP_OUT_CB2 -> DLO= _ASYNC2 + */ +static const struct mtk_mmsys_routes mmsys_mt8196_disp0_routing_table[] = =3D { + MMSYS_ROUTE(DLI_ASYNC0, DLO_ASYNC1, + MT8196_PQ_IN_CB0_MOUT_EN, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6, + MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6), + MMSYS_ROUTE(DLI_ASYNC0, DLO_ASYNC1, + MT8196_PQ_OUT_CB6_MOUT_EN, MT8196_PQ_OUT_CB6_TO_PANEL0_COMP_OUT_CB1, + MT8196_PQ_OUT_CB6_TO_PANEL0_COMP_OUT_CB1), + MMSYS_ROUTE(DLI_ASYNC0, DLO_ASYNC1, + MT8196_PANEL_COMP_OUT_CB1_MOUT_EN, MT8196_DISP_TO_DLO_RELAY1, + MT8196_DISP_TO_DLO_RELAY1), + MMSYS_ROUTE(DLI_ASYNC1, DLO_ASYNC2, + MT8196_PQ_IN_CB1_MOUT_EN, MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7, + MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7), + MMSYS_ROUTE(DLI_ASYNC1, DLO_ASYNC2, + MT8196_PQ_OUT_CB7_MOUT_EN, MT8196_PQ_OUT_CB7_TO_PANEL0_COMP_OUT_CB2, + MT8196_PQ_OUT_CB7_TO_PANEL0_COMP_OUT_CB2), + MMSYS_ROUTE(DLI_ASYNC1, DLO_ASYNC2, + MT8196_PANEL_COMP_OUT_CB2_MOUT_EN, MT8196_DISP_TO_DLO_RELAY2, + MT8196_DISP_TO_DLO_RELAY2), + MMSYS_ROUTE(DLI_ASYNC8, DLO_ASYNC3, + MT8196_PQ_IN_CB8_MOUT_EN, MT8196_PQ_IN_CB8_TO_PQ_OUT_CB_8, + MT8196_PQ_IN_CB8_TO_PQ_OUT_CB_8), + MMSYS_ROUTE(DLI_ASYNC8, DLO_ASYNC3, + MT8196_PQ_OUT_CB8_MOUT_EN, MT8196_PQ_OUT_CB8_TO_PANEL0_COMP_OUT_CB3, + MT8196_PQ_OUT_CB8_TO_PANEL0_COMP_OUT_CB3), + MMSYS_ROUTE(DLI_ASYNC8, DLO_ASYNC3, + MT8196_PANEL_COMP_OUT_CB3_MOUT_EN, MT8196_DISP_TO_DLO_RELAY3, + MT8196_DISP_TO_DLO_RELAY3) +}; + +/* + * main: DLI_ASYNC21-> SPLITTER_IN_CB1-> SPLITTER_OUT_CB9-> COMP_OUT_CB6->= MERGE_OUT_CB0 -> DVO + * ext: DLI_ASYNC22-> SPLITTER_IN_CB2-> SPLITTER_OUT_CB10-> COMP_OUT_CB7->= MERGE_OUT_CB1 -> DP_INTF0 + */ +static const struct mtk_mmsys_routes mmsys_mt8196_disp1_routing_table[] = =3D { + MMSYS_ROUTE(DLI_ASYNC21, DVO0, + MT8196_SPLITTER_IN_CB1_MOUT_EN, MT8196_DISP_DLI_RELAY_TO_SPLITTER_OU= T_CB9, + MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB9), + MMSYS_ROUTE(DLI_ASYNC21, DVO0, + MT8196_SPLITTER_OUT_CB9_MOUT_EN, MT8196_DISP_SPLITTER_IN_CB_TO_COMP_= OUT_CB6, + MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB6), + MMSYS_ROUTE(DLI_ASYNC21, DVO0, + MT8196_COMP_OUT_CB6_MOUT_EN, MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OU= T_CB0, + MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB0), + MMSYS_ROUTE(DLI_ASYNC21, DVO0, + MT8196_MERGE_OUT_CB0_MOUT_EN, MT8196_DISP_COMP_OUT_CB_TO_DVO0, + MT8196_DISP_COMP_OUT_CB_TO_DVO0), + MMSYS_ROUTE(DLI_ASYNC22, DP_INTF0, + MT8196_SPLITTER_IN_CB2_MOUT_EN, MT8196_DISP_DLI_RELAY_TO_SPLITTER_OU= T_CB10, + MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB10), + MMSYS_ROUTE(DLI_ASYNC22, DP_INTF0, + MT8196_SPLITTER_OUT_CB10_MOUT_EN, MT8196_DISP_SPLITTER_IN_CB_TO_COMP= _OUT_CB7, + MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB7), + MMSYS_ROUTE(DLI_ASYNC22, DP_INTF0, + MT8196_COMP_OUT_CB7_MOUT_EN, MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OU= T_CB1, + MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB1), + MMSYS_ROUTE(DLI_ASYNC22, DP_INTF0, + MT8196_MERGE_OUT_CB1_MOUT_EN, MT8196_DISP_COMP_OUT_CB_TO_DP_INTF0, + MT8196_DISP_COMP_OUT_CB_TO_DP_INTF0), + MMSYS_ROUTE(DLI_ASYNC23, DVO0, + MT8196_SPLITTER_IN_CB3_MOUT_EN, MT8196_DISP_DLI_RELAY_TO_SPLITTER_OU= T_CB11, + MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11), + MMSYS_ROUTE(DLI_ASYNC23, DVO0, + MT8196_SPLITTER_OUT_CB11_MOUT_EN, MT8196_DISP_SPLITTER_IN_CB_TO_COMP= _OUT_CB8, + MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8), + MMSYS_ROUTE(DLI_ASYNC23, DVO0, + MT8196_COMP_OUT_CB8_MOUT_EN, MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OU= T_CB2, + MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2), + MMSYS_ROUTE(DLI_ASYNC23, DVO0, + MT8196_MERGE_OUT_CB2_MOUT_EN, MT8196_DISP_COMP_OUT_CB_TO_DVO0, + MT8196_DISP_COMP_OUT_CB_TO_DVO0), + MMSYS_ROUTE(DLI_ASYNC23, DP_INTF1, + MT8196_SPLITTER_IN_CB3_MOUT_EN, MT8196_DISP_DLI_RELAY_TO_SPLITTER_OU= T_CB11, + MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11), + MMSYS_ROUTE(DLI_ASYNC23, DP_INTF1, + MT8196_SPLITTER_OUT_CB11_MOUT_EN, MT8196_DISP_SPLITTER_IN_CB_TO_COMP= _OUT_CB8, + MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8), + MMSYS_ROUTE(DLI_ASYNC23, DP_INTF1, + MT8196_COMP_OUT_CB8_MOUT_EN, MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OU= T_CB2, + MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2), + MMSYS_ROUTE(DLI_ASYNC23, DP_INTF1, + MT8196_MERGE_OUT_CB2_MOUT_EN, MT8196_DISP_COMP_OUT_CB_TO_DP_INTF1, + MT8196_DISP_COMP_OUT_CB_TO_DP_INTF1), + MMSYS_ROUTE(DLI_ASYNC23, DSI0, + MT8196_SPLITTER_IN_CB3_MOUT_EN, MT8196_DISP_DLI_RELAY_TO_SPLITTER_OU= T_CB11, + MT8196_DISP_DLI_RELAY_TO_SPLITTER_OUT_CB11), + MMSYS_ROUTE(DLI_ASYNC23, DSI0, + MT8196_SPLITTER_OUT_CB11_MOUT_EN, MT8196_DISP_SPLITTER_IN_CB_TO_COMP= _OUT_CB8, + MT8196_DISP_SPLITTER_IN_CB_TO_COMP_OUT_CB8), + MMSYS_ROUTE(DLI_ASYNC23, DSI0, + MT8196_COMP_OUT_CB8_MOUT_EN, MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OU= T_CB2, + MT8196_DISP_SPLITTER_OUT_CB_TO_MERGE_OUT_CB2), + MMSYS_ROUTE(DLI_ASYNC23, DSI0, + MT8196_MERGE_OUT_CB2_MOUT_EN, MT8196_DISP_COMP_OUT_CB_TO_DSI0, + MT8196_DISP_COMP_OUT_CB_TO_DSI0) +}; +#endif /* __SOC_MEDIATEK_MT8196_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index f448cc09ce19..3b490b993549 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -24,6 +24,7 @@ #include "mt8188-mmsys.h" #include "mt8192-mmsys.h" #include "mt8195-mmsys.h" +#include "mt8196-mmsys.h" #include "mt8365-mmsys.h" =20 #define MMSYS_SW_RESET_PER_REG 32 @@ -147,6 +148,54 @@ static const struct mtk_mmsys_driver_data mt8195_vppsy= s1_driver_data =3D { .is_vppsys =3D true, }; =20 +static const struct mtk_mmsys_driver_data mt8196_dispsys0_driver_data =3D { + .clk_driver =3D "clk-mt8196-disp0", + .routes =3D mmsys_mt8196_disp0_routing_table, + .num_routes =3D ARRAY_SIZE(mmsys_mt8196_disp0_routing_table), + .async_info =3D mmsys_mt8196_disp0_async_comp_table, + .num_async_info =3D ARRAY_SIZE(mmsys_mt8196_disp0_async_comp_table), + .def_config =3D mmsys_mt8196_disp0_default_table, + .num_def_config =3D ARRAY_SIZE(mmsys_mt8196_disp0_default_table), + .num_top_clk =3D 1, +}; + +static const struct mtk_mmsys_driver_data mt8196_dispsys1_driver_data =3D { + .clk_driver =3D "clk-mt8196-disp1", + .routes =3D mmsys_mt8196_disp1_routing_table, + .num_routes =3D ARRAY_SIZE(mmsys_mt8196_disp1_routing_table), + .async_info =3D mmsys_mt8196_disp1_async_comp_table, + .num_async_info =3D ARRAY_SIZE(mmsys_mt8196_disp1_async_comp_table), + .def_config =3D mmsys_mt8196_disp1_default_table, + .num_def_config =3D ARRAY_SIZE(mmsys_mt8196_disp1_default_table), + .num_top_clk =3D 1, +}; + +static const struct mtk_mmsys_driver_data mt8196_ovlsys0_driver_data =3D { + .clk_driver =3D "clk-mt8196-ovl0", + .routes =3D mmsys_mt8196_ovl0_routing_table, + .num_routes =3D ARRAY_SIZE(mmsys_mt8196_ovl0_routing_table), + .async_info =3D mmsys_mt8196_ovl0_async_comp_table, + .num_async_info =3D ARRAY_SIZE(mmsys_mt8196_ovl0_async_comp_table), + .def_config =3D mmsys_mt8196_ovl0_default_table, + .num_def_config =3D ARRAY_SIZE(mmsys_mt8196_ovl0_default_table), +}; + +static const struct mtk_mmsys_driver_data mt8196_ovlsys1_driver_data =3D { + .clk_driver =3D "clk-mt8196-ovl1", + .routes =3D mmsys_mt8196_ovl1_routing_table, + .num_routes =3D ARRAY_SIZE(mmsys_mt8196_ovl1_routing_table), + .async_info =3D mmsys_mt8196_ovl1_async_comp_table, + .num_async_info =3D ARRAY_SIZE(mmsys_mt8196_ovl1_async_comp_table), + .def_config =3D mmsys_mt8196_ovl0_default_table, + .num_def_config =3D ARRAY_SIZE(mmsys_mt8196_ovl0_default_table), +}; + +static const struct mtk_mmsys_driver_data mt8196_vdisp_ao_driver_data =3D { + .clk_driver =3D "clk-mt8196-vdisp_ao", + .def_config =3D mmsys_mt8196_vdisp_ao_default_table, + .num_def_config =3D ARRAY_SIZE(mmsys_mt8196_vdisp_ao_default_table), +}; + static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data =3D { .clk_driver =3D "clk-mt8365-mm", .routes =3D mt8365_mmsys_routing_table, @@ -626,6 +675,11 @@ static const struct of_device_id of_match_mtk_mmsys[] = =3D { { .compatible =3D "mediatek,mt8195-vdosys1", .data =3D &mt8195_vdosys1_dr= iver_data }, { .compatible =3D "mediatek,mt8195-vppsys0", .data =3D &mt8195_vppsys0_dr= iver_data }, { .compatible =3D "mediatek,mt8195-vppsys1", .data =3D &mt8195_vppsys1_dr= iver_data }, + { .compatible =3D "mediatek,mt8196-dispsys0", .data =3D &mt8196_dispsys0_= driver_data }, + { .compatible =3D "mediatek,mt8196-dispsys1", .data =3D &mt8196_dispsys1_= driver_data }, + { .compatible =3D "mediatek,mt8196-ovlsys0", .data =3D &mt8196_ovlsys0_dr= iver_data }, + { .compatible =3D "mediatek,mt8196-ovlsys1", .data =3D &mt8196_ovlsys1_dr= iver_data }, + { .compatible =3D "mediatek,mt8196-vdisp-ao", .data =3D &mt8196_vdisp_ao_= driver_data }, { .compatible =3D "mediatek,mt8365-mmsys", .data =3D &mt8365_mmsys_driver= _data }, { /* sentinel */ } }; diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index f50f626e1840..4a0b10567581 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -29,6 +29,15 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_COLOR1, DDP_COMPONENT_DITHER0, DDP_COMPONENT_DITHER1, + DDP_COMPONENT_DLI_ASYNC0, + DDP_COMPONENT_DLI_ASYNC1, + DDP_COMPONENT_DLI_ASYNC8, + DDP_COMPONENT_DLI_ASYNC21, + DDP_COMPONENT_DLI_ASYNC22, + DDP_COMPONENT_DLI_ASYNC23, + DDP_COMPONENT_DLO_ASYNC1, + DDP_COMPONENT_DLO_ASYNC2, + DDP_COMPONENT_DLO_ASYNC3, DDP_COMPONENT_DP_INTF0, DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DPI0, @@ -39,6 +48,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, DDP_COMPONENT_DSI3, + DDP_COMPONENT_DVO0, DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_GAMMA, DDP_COMPONENT_MDP_RDMA0, @@ -58,10 +68,52 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OD0, DDP_COMPONENT_OD1, DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL0_BLENDER1, + DDP_COMPONENT_OVL0_BLENDER2, + DDP_COMPONENT_OVL0_BLENDER3, + DDP_COMPONENT_OVL0_BLENDER4, + DDP_COMPONENT_OVL0_BLENDER5, + DDP_COMPONENT_OVL0_BLENDER6, + DDP_COMPONENT_OVL0_BLENDER7, + DDP_COMPONENT_OVL0_BLENDER8, + DDP_COMPONENT_OVL0_BLENDER9, + DDP_COMPONENT_OVL0_DLO_ASYNC5, + DDP_COMPONENT_OVL0_DLO_ASYNC6, + DDP_COMPONENT_OVL0_EXDMA2, + DDP_COMPONENT_OVL0_EXDMA3, + DDP_COMPONENT_OVL0_EXDMA4, + DDP_COMPONENT_OVL0_EXDMA5, + DDP_COMPONENT_OVL0_EXDMA6, + DDP_COMPONENT_OVL0_EXDMA7, + DDP_COMPONENT_OVL0_EXDMA8, + DDP_COMPONENT_OVL0_EXDMA9, + DDP_COMPONENT_OVL0_OUTPROC0, + DDP_COMPONENT_OVL0_OUTPROC1, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_OVL1_BLENDER1, + DDP_COMPONENT_OVL1_BLENDER2, + DDP_COMPONENT_OVL1_BLENDER3, + DDP_COMPONENT_OVL1_BLENDER4, + DDP_COMPONENT_OVL1_BLENDER5, + DDP_COMPONENT_OVL1_BLENDER6, + DDP_COMPONENT_OVL1_BLENDER7, + DDP_COMPONENT_OVL1_BLENDER8, + DDP_COMPONENT_OVL1_BLENDER9, + DDP_COMPONENT_OVL1_DLO_ASYNC5, + DDP_COMPONENT_OVL1_DLO_ASYNC6, + DDP_COMPONENT_OVL1_EXDMA2, + DDP_COMPONENT_OVL1_EXDMA3, + DDP_COMPONENT_OVL1_EXDMA4, + DDP_COMPONENT_OVL1_EXDMA5, + DDP_COMPONENT_OVL1_EXDMA6, + DDP_COMPONENT_OVL1_EXDMA7, + DDP_COMPONENT_OVL1_EXDMA8, + DDP_COMPONENT_OVL1_EXDMA9, + DDP_COMPONENT_OVL1_OUTPROC0, + DDP_COMPONENT_OVL1_OUTPROC1, DDP_COMPONENT_PADDING0, DDP_COMPONENT_PADDING1, DDP_COMPONENT_PADDING2, --=20 2.45.2