From nobody Fri Oct 3 18:03:46 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A7D32D94B6; Thu, 28 Aug 2025 08:09:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756368557; cv=none; b=DDKvnh1ubfN96VPS4oHygRefiffZsw//SAYesSpSqsJJ3MaPvuAbA1NOUZ5FrjZm7W3+G2vmyNC6anRuOMksjiT/bcS5VRWeZsOC022BY+fP92QY+lrA/Qz6sihNpDbRA5HTQLDPRXyahXyg26XYdmM+EOJG9bnxAK2eoLeUPLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756368557; c=relaxed/simple; bh=oV2k5JlWJuaT0IU8FIZocOo8PrxSk7z006gmvg/fJEc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=axDS74DwOXzwy9k+grah/F9GLcvXSm2NWVXODNI/Opr3ILJNSMpjcwCa33LHESqI6uEZ9WyczobTKtiQSGjWD6fyayEJCs4s8eGHfObugUPFADa4bdzVayXwnhqqrhgZYWkvrvKwtqmYlevFcG6IwcobYsvcTibENkhBunkm1nE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=VH+qz5Hb; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="VH+qz5Hb" X-UUID: 4417e77e83e611f0b33aeb1e7f16c2b6-20250828 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=YVXhHHEXSGwqnu+r3AHVgz0i2SOhikDJ3D3rLoZ1wH8=; b=VH+qz5HbPFOafrSgpi2nz3RPDQC/X2F+Of7Zg30azgWPtls76dE7gmtvPNVtZ8vUu1nt7YPIwJP4GJvyI65oqpZyc6RxqbV49TbBjev023IrM2wrqyWkgpNYKL1pm78WSLaf9DkFQNQeKR/ifIN7J/Rwf50+bZo00IblXIUSdAk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:bec6d82f-d586-497d-a190-a13a52410634,IP:0,UR L:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:20 X-CID-META: VersionHash:f1326cf,CLOUDID:02719d7a-966c-41bd-96b5-7d0b3c22e782,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:11|97|99|83|106|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,CO L:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 4417e77e83e611f0b33aeb1e7f16c2b6-20250828 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1122390017; Thu, 28 Aug 2025 16:09:05 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 28 Aug 2025 16:09:03 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 28 Aug 2025 16:09:03 +0800 From: Paul Chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 05/19] dt-bindings: display: mediatek: add OUTPROC yaml for MT8196 Date: Thu, 28 Aug 2025 16:07:00 +0800 Message-ID: <20250828080855.3502514-6-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> References: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paul-pl Chen Add mediate,outproc.yaml to support OUTPROC for MT8196. MediaTek display overlap output processor, namely OVL_OUTPROC or OUTPROC,handles the post-stage of pixel processing in the overlapping procedure. Signed-off-by: Paul-pl Chen --- .../display/mediatek/mediatek,outproc.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,outproc.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ou= tproc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ou= tproc.yaml new file mode 100644 index 000000000000..7c884749dd7a --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.y= aml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,outproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display overlap output processor + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: + MediaTek display overlap output processor, namely OVL_OUTPROC or OUTPROC, + handles the post-stage of pixel processing in the overlapping procedure. + OVL_OUTPROC manages pixels for gamma correction and ensures that pixel + values are within the correct range. + +properties: + compatible: + const: mediatek,mt8196-outproc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + outproc@32970000 { + compatible =3D "mediatek,mt8196-outproc"; + reg =3D <0 0x32970000 0 0x1000>; + clocks =3D <&ovlsys_config_clk 49>; + interrupts =3D ; + }; + }; --=20 2.45.2