From nobody Fri Oct 3 18:03:46 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DC7F2E06EA; Thu, 28 Aug 2025 08:09:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756368559; cv=none; b=CriC1Mm3wDPPdWYoIpS37QpC20+JKNN+1IGs6TWExWxzRrCb5FEhqyK7X6dCv1ruTZlPFMqtiUbYKHxll1nrc3F8212t2kNzhZ/MNXFmR6hb9TiHhLB3PLh2IGH5m+Sm5Ygc9I6HRSNy1hVhgf8dPrv0rC+iQw/85hk9tQQIvsc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756368559; c=relaxed/simple; bh=6zgmK+eaMjsDMtzm9E1svhtusEus8v2j4DuB+lOmeo4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qk02wL7JvdQP2x0gxiMbU30R7XaauN49tsc/SYgp6vJSOGv2rVPT1LxkQVDzqapVNbSvkmLdaLqzhF9eSgu+h58lL4htqrTR+Jdnagk8kaOIwQSbMaLR7bs6rQekEjzfYcRKU7SPgNcVI6TOhIP3oTUcaHzmheKwMbXOqSKFLks= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=oNq5VIK7; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="oNq5VIK7" X-UUID: 44ca64b283e611f0b33aeb1e7f16c2b6-20250828 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=91unXKrGbTDeKulmVuy2IpfFgxjMO7TgUgeAB/op83w=; b=oNq5VIK73QozqL1gB+UyH1oF6am1nUwWDvyrQRhIYaK/bSl+vWg+UWYGmuqim9t9iPfC5OCYy0kBXzSLVJf0myh2Yb1dIrYG3Jw59NC9IIFAWhhFBsIVZAVCg2ZyN/x0mSe9/6PmRVSYhHwFaNmbUnDbWXjQmPJeMs1yit0zlXI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:889ad49d-bacb-454f-852e-a041dcb38528,IP:0,UR L:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:-5 X-CID-META: VersionHash:f1326cf,CLOUDID:1f1bf544-18c5-4075-a135-4c0afe29f9d6,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 44ca64b283e611f0b33aeb1e7f16c2b6-20250828 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1029624847; Thu, 28 Aug 2025 16:09:06 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 28 Aug 2025 16:09:05 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 28 Aug 2025 16:09:05 +0800 From: Paul Chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 13/19] drm/mediatek: Export OVL Blend function Date: Thu, 28 Aug 2025 16:07:08 +0800 Message-ID: <20250828080855.3502514-14-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> References: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paul-pl Chen For the new BLENDER component, the OVL ignore pixel alpha logic should be exported as a function and reused it. Signed-off-by: Nancy Lin Signed-off-by: Paul-pl Chen --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 68 +++++++++++++++++-------- drivers/gpu/drm/mediatek/mtk_disp_ovl.h | 8 +++ 2 files changed, 56 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index e3ee3f60f4ba..7cd3978beb98 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -228,6 +228,23 @@ void mtk_ovl_disable_vblank(struct device *dev) writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } =20 +bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state, unsigned= int blend_mode) +{ + if (!state->base.fb) + return false; + + /* + * Although the alpha channel can be ignored, CONST_BLD must be enabled + * for XRGB format, otherwise OVL will still read the value from memory. + * For RGB888 related formats, whether CONST_BLD is enabled or not won't + * affect the result. Therefore we use !has_alpha as the condition. + */ + if (blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->forma= t->has_alpha) + return true; + + return false; +} + u32 mtk_ovl_get_blend_modes(struct device *dev) { struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); @@ -414,6 +431,29 @@ void mtk_ovl_layer_off(struct device *dev, unsigned in= t idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 +unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state, unsigne= d int blend_modes) +{ + unsigned int blend_mode =3D DRM_MODE_BLEND_COVERAGE; + + /* + * For the platforms where OVL_CON_CLRFMT_MAN is defined in the hardware = data sheet + * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB= 888 + * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB= 8888. + * + * Check blend_modes in the driver data to see if premultiplied mode is s= upported. + * If not, use coverage mode instead to set it to the supported color for= mats. + * + * Current DRM assumption is that alpha is default premultiplied, so the = bitmask of + * blend_modes must include BIT(DRM_MODE_BLEND_PREMULTI). Otherwise, mtk_= plane_init() + * will get an error return from drm_plane_create_blend_mode_property() a= nd + * state->base.pixel_blend_mode should not be used. + */ + if (blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) + blend_mode =3D state->base.pixel_blend_mode; + + return blend_mode; +} + unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode, bool fmt_rgb565_is_0, bool color_convert, u8 clrfmt_shift, u32 clrfmt_man, u32 byte_swap, u32 rgb_swap) @@ -541,7 +581,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, unsigned int rotation =3D pending->rotation; unsigned int offset =3D (pending->y << 16) | pending->x; unsigned int src_size =3D (pending->height << 16) | pending->width; - unsigned int blend_mode =3D state->base.pixel_blend_mode; + unsigned int blend_mode =3D mtk_ovl_get_blend_mode(state, ovl->data->blen= d_modes); unsigned int ignore_pixel_alpha =3D 0; unsigned int con; =20 @@ -566,17 +606,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, * For blend_modes supported SoCs, always enable alpha blending. * For blend_modes unsupported SoCs, enable alpha blending when has_alph= a is set. */ - if (blend_mode || state->base.fb->format->has_alpha) + if (state->base.pixel_blend_mode || state->base.fb->format->has_alpha) con |=3D OVL_CON_AEN; - - /* - * Although the alpha channel can be ignored, CONST_BLD must be enabled - * for XRGB format, otherwise OVL will still read the value from memory. - * For RGB888 related formats, whether CONST_BLD is enabled or not won't - * affect the result. Therefore we use !has_alpha as the condition. - */ - if (blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->form= at->has_alpha) - ignore_pixel_alpha =3D OVL_CONST_BLEND; } =20 /* @@ -602,6 +633,9 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, =20 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); + + if (mtk_ovl_is_ignore_pixel_alpha(state, blend_mode)) + ignore_pixel_alpha =3D OVL_CONST_BLEND; mtk_ddp_write_relaxed(cmdq_pkt, pitch_lsb | ignore_pixel_alpha, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, @@ -751,9 +785,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, - .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE) | - BIT(DRM_MODE_BLEND_PIXEL_NONE), + .blend_modes =3D MTK_OVL_SUPPORT_BLEND_MODES, .formats =3D mt8173_ovl_formats, .num_formats =3D mt8173_ovl_formats_len, }; @@ -764,9 +796,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_dri= ver_data =3D { .layer_nr =3D 2, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, - .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE) | - BIT(DRM_MODE_BLEND_PIXEL_NONE), + .blend_modes =3D MTK_OVL_SUPPORT_BLEND_MODES, .formats =3D mt8173_ovl_formats, .num_formats =3D mt8173_ovl_formats_len, }; @@ -778,9 +808,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .supports_afbc =3D true, - .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE) | - BIT(DRM_MODE_BLEND_PIXEL_NONE), + .blend_modes =3D MTK_OVL_SUPPORT_BLEND_MODES, .formats =3D mt8195_ovl_formats, .num_formats =3D mt8195_ovl_formats_len, .supports_clrfmt_ext =3D true, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.h index 4f446d2e0712..431567538eb5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h @@ -6,14 +6,22 @@ #ifndef __MTK_DISP_OVL_H__ #define __MTK_DISP_OVL_H__ =20 +#include #include =20 +#define MTK_OVL_SUPPORT_BLEND_MODES \ + (BIT(DRM_MODE_BLEND_PREMULTI) | \ + BIT(DRM_MODE_BLEND_COVERAGE) | \ + BIT(DRM_MODE_BLEND_PIXEL_NONE)) + extern const u32 mt8173_ovl_formats[]; extern const size_t mt8173_ovl_formats_len; extern const u32 mt8195_ovl_formats[]; extern const size_t mt8195_ovl_formats_len; =20 bool mtk_ovl_is_10bit_rgb(unsigned int fmt); +bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state, unsigned= int blend_mode); +unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state, unsigne= d int blend_modes); unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode, bool fmt_rgb565_is_0, bool color_convert, u8 clrfmt_shift, u32 clrfmt_man, u32 byte_swap, u32 rgb_swap); --=20 2.45.2