From nobody Fri Oct 3 16:47:19 2025 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2062.outbound.protection.outlook.com [40.107.100.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77639278161; Thu, 28 Aug 2025 06:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.100.62 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756360802; cv=fail; b=uHNcYsVPKnyvSGpAXFyDEgL9VU/w8depX8ODDpfQEySeP+xc9HXdoFMi5nlRVDk4c37SQBnjUz1BOHtH7Br0/cg8PxRhJE2A6W3ZLv6ne3xK7V32WBpCAfqkqP222NMUc+8wqqEeaeonLKFxKMRXD38vjsrrbRPOqsq4pqUDn2o= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756360802; c=relaxed/simple; bh=AKHZUl9sirmivCeMeD42IsCP9VXkiPMBTSJhdolaETI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gGSnTqj/sNsEotvcvbJoYqw7SmvIHRBUn+y9WI/M2c1OA/sVErVNqzxfLaoTHq1zRo1X3nKiHhV9FK2s5UqwIlfgR7azEMk+QypMZ+pqntt8HtRDolB8Z7EyXzL7UqYImdAPbu+732Y1XX/s5DZR789ued9SCgWj9fHv6WwhCj0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=FMRBPvVg; arc=fail smtp.client-ip=40.107.100.62 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="FMRBPvVg" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CpwLlZ9p/fitOyzLvchz6uKLs3JoeDrzHoyAuVLbmsTmMfUjXzhMHqjHbJntSuk5RSNB8wH/QmzOX5nimOJrz2zhjGGqQlUs7l8nbtnEF4sie3X7Nk1Rt6dBq7r8xi1pmZjc4ke9pDZbOYbGsEOV28E+deJC8mzuhq6hquZDCtyRUpLg8Dgmb07vMasHqbmFhDgNDk18ywjfmU+frF6IKQYbVluZ2Pi9WINNgmBPnTvlg3LuevxbKCfdRQ3huNUtFcEkjpBZBIiweOH3txWLRfzdVRkPwcrascbD1hVcjyTfgxfLwclnJ/GG6PbvjaoI4yxXp6BEYr8VvhuKUYi12w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=wTZs20+4R+gm/l7JPhnmf43JXxQ28ckK+YHlpU2QDyI=; b=kLrE27RX5nLvUNevWdtNu//VAT9RbSqEqql6ex2bPjnVapTc1QwzD7MF3Lwyoxy/w1X8FWk2Th7BkOKGxd7NWNqhb3w8rqD6hqT7o0H7C7rOa6AFMdIqnqVFlOdKSF6fGACnbfMT0VffsS1TeSCoYkRc5gu2EkqeWLmZ1UM+bvuSBLZUe2apMO3PTPcT4n/jXdeksL2WL57naOAevhscqrFl8VYD/ik4/lpEzE3aU4EKDMBzv3UGKPIA1TZH/JmuZg8pTF5LtT3p3HT/ti/8kF6BKhBdKr0OSnoi453NjLOD+nZZkPSpETJeXTtfNa09rFjCpPnRHnt+FnfOnPGn2g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wTZs20+4R+gm/l7JPhnmf43JXxQ28ckK+YHlpU2QDyI=; b=FMRBPvVgdD2Ck5f08B/Nu7vKzJAc3QkBg5JCPkZP143b8cF6RWUg5XSaQ/8gNe3LfqLO1xugBehQP2qLeLgfrUOxO3NSv7joTTKXFLaWez+FovGxpmGlpHMpgxjoJWRE2cLWAnXElZxzj/VdZrtFXXxe4CmBL3QGvP/nOxxhTINammOYO4siXdS0w9JfENEZqCpZciTWemC7utOKLAQVoKIZ8m318HXxKeBlwZ09VKLxwqyf9meAGSrnpuzNu6ihLCkO1YiLEQS2ITHFz4E/uDZ9ApC1nMEfZpieMd4pCtrs8NAInZWth4FdRtv6Gf0MEBlZcDE79z2z45Bp6+/HvA== Received: from SJ0PR03CA0005.namprd03.prod.outlook.com (2603:10b6:a03:33a::10) by PH7PR12MB6740.namprd12.prod.outlook.com (2603:10b6:510:1ab::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9052.21; Thu, 28 Aug 2025 05:59:55 +0000 Received: from SJ5PEPF000001CD.namprd05.prod.outlook.com (2603:10b6:a03:33a:cafe::98) by SJ0PR03CA0005.outlook.office365.com (2603:10b6:a03:33a::10) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9073.16 via Frontend Transport; Thu, 28 Aug 2025 05:59:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ5PEPF000001CD.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9073.11 via Frontend Transport; Thu, 28 Aug 2025 05:59:55 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 27 Aug 2025 22:59:45 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 27 Aug 2025 22:59:45 -0700 Received: from kkartik-desktop.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 27 Aug 2025 22:59:41 -0700 From: Kartik Rajput To: , , , , , , , , , , , , CC: , Conor Dooley Subject: [PATCH v6 1/5] dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C Date: Thu, 28 Aug 2025 11:29:29 +0530 Message-ID: <20250828055933.496548-2-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250828055933.496548-1-kkartik@nvidia.com> References: <20250828055933.496548-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CD:EE_|PH7PR12MB6740:EE_ X-MS-Office365-Filtering-Correlation-Id: 61207d84-112f-463c-0b0b-08dde5f81ce9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?l6ZoL8ssSxMNO5O8MIPxb2WExH4n3nXGJpxrmJZ2E6rMTaw7OVmrS8JzbfPs?= =?us-ascii?Q?lfHE41AEOZWvMqkT042W6MRZXd3EL3JoAnzJ3cEdqrZha7RSSjZoxgRoBLk3?= =?us-ascii?Q?QCPD8MwboNX9un07JFXjuM9O0W/icl8GFzsQlVrhxYtM8menM7OY1DaIADJc?= =?us-ascii?Q?IUbRnxAoOI1WxfhVm4uLrU5XuKfsyBwbd0VAnjC4DUIMFqplafEwMyyymdzm?= =?us-ascii?Q?86xJTwXhk14sq8/pobecgEweKo2nrhZa1HUCg/8wVbQYXJUxruPClBnwbTwM?= =?us-ascii?Q?jyOrDKHLmtPaoE6jhLCgANrzJbt5HtJplpyz8nZ1cIpl/Pb7GX7DU//DAQ9r?= =?us-ascii?Q?IbvNA9xlBzj85SfeDySao4nDESE/ceOmOIsf5vILo/GO9vUk4TQdPFzlHrgU?= =?us-ascii?Q?piC2xpaPQL4Gmk7l7/ueyhjWqFtCq+Ablt1qAaHrxVVvN9hpfGgHoBW+92d8?= =?us-ascii?Q?jTOFx5/S/8xXhbpt2jm0ivvi0gSSTa3w5k9qHepcSmYmpaV+VK7MhEheHaB+?= =?us-ascii?Q?uOqLnJFalRLRW1AlDPgvZWF19P6Bw5F/xZc6uxCQN1ykpWL9n0hTOOr2Hh4z?= =?us-ascii?Q?hmu3TWW+qvVWxJmEKDCtkpA2cWifsbrDjEOXOpfn7dsOCK8PEne1StpjObMr?= =?us-ascii?Q?pLuRpuV3xeVFU6yBYytxa8eMQ2+DegCaC6HpUmsOhlzuicPmefPfGuUcTzg4?= =?us-ascii?Q?2XEbzwaJ0H4gGmUYV1l0K83bf5oTGvK744Pmdny1LsADCuliJqw3jJXw28x+?= =?us-ascii?Q?ICBKrE8W8NcLdIpza193qySPZ23PVbDvai2AOL7HFh30nE5SBS3uMtwdpXqD?= =?us-ascii?Q?jfCDX4R2OP+xd/Qh95jaKnk2OtOvmumJSb+Q1houUBtZ06q4UoQMqsYGCIt4?= =?us-ascii?Q?HrdNOgQezj8Co0D/m5KJkO38hcQWqbyyyd4TjBqNueIpsKFU6IazOinBuw3w?= =?us-ascii?Q?Veemua+zyHMuX522+zIP6cI9RbV3sESWzJdrRvTDdF6y+7AoYtmTwIfx7nM9?= =?us-ascii?Q?Ex0FcZWKifICG+c4VmwKGar33a7xiITVROMZMCXhtOn2x09tGsXURxPwxzo/?= =?us-ascii?Q?v1jlAbuXoWAYQdxyHI4cAOSuFUInPuMpmjokL3pAix76/f6ku5DRfS6Owrx1?= =?us-ascii?Q?hJXZlgpUBOyPiKoL2o3z+BNH30Pfyu6M1baCjVSAcubJROZ61i0QkNCsblI5?= =?us-ascii?Q?alxioPlXlnJuiS+/PbYoP4AIaZKKDQvVcsWVmiarj4uBRCvWDf0+h6kG72nY?= =?us-ascii?Q?/VMjnLS+j2gTHM0KLMVa9NgGUGsD1B7lR66PkSy2uOYWaeHQ0A4aKPSNZ46n?= =?us-ascii?Q?WgY7wS5fzDGAn0CQi1SMnLjn+/846duq27PpUdc78b/qPoN3zx8PyJpi5dar?= =?us-ascii?Q?Em1d87c8hjLmUOOpYYOtzAzKFkZna25W7ocn5soMdUvrnWUjPhDDzGkKtOOo?= =?us-ascii?Q?TdWH3O0Mob9oVNqoc+abwofC8AypE6thdooC1nNPCNPUwXVz1+cHiWfNHzdO?= =?us-ascii?Q?Emrf4SOV56bwSaB6HOTN7fCShIYR3z2eZZASBUO1IL7bLHOOZDeTCCRgkg?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(36860700013)(1800799024)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2025 05:59:55.2893 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61207d84-112f-463c-0b0b-08dde5f81ce9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6740 Content-Type: text/plain; charset="utf-8" Tegra264 has 17 generic I2C controllers, two of which are in always-on partition of the SoC. In addition to the features supported by Tegra194 it also supports a SW mutex register to allow sharing the same I2C instance across multiple firmware. Document compatible string "nvidia,tegra264-i2c" for Tegra264 I2C. Signed-off-by: Kartik Rajput Acked-by: Conor Dooley --- v2 -> v3: * Add constraints for "nvidia,tegra264-i2c". v1 -> v2: * Fixed typos. --- .../devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml = b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index 6b6f6762d122..f0693b872cb6 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -80,6 +80,12 @@ properties: support for 64 KiB transactions whereas earlier chips supported = no more than 4 KiB per transactions. const: nvidia,tegra194-i2c + - description: + Tegra264 has 17 generic I2C controllers, two of which are in the= AON + (always-on) partition of the SoC. In addition to the features fr= om + Tegra194, a SW mutex register is added to support use of the sam= e I2C + instance across multiple firmwares. + const: nvidia,tegra264-i2c =20 reg: maxItems: 1 @@ -186,6 +192,7 @@ allOf: contains: enum: - nvidia,tegra194-i2c + - nvidia,tegra264-i2c then: required: - resets --=20 2.43.0 From nobody Fri Oct 3 16:47:19 2025 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2085.outbound.protection.outlook.com [40.107.223.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 579AB271476; Thu, 28 Aug 2025 06:00:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.85 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756360804; cv=fail; b=RRe8mACA9LNoZYtiv3owHJCxk2m/ze8f4Sogq4RHJiUb6AysoUf5+Bw0o94hkotN4NV45H/XYZQyhxlhx+k8Ff589IJI0mewwtEcaMeFBRpvVKYYaIXQHf23x7VIHeiXmxldDqeFmMrFEiYGvlW9q4rxRtHJ/sgCYTDcNpKkKmo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756360804; c=relaxed/simple; bh=dFdpBy806e1fxNZfUxnACskBXaStls6gX1eNuojym2I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jZuuacT+fl86BaCuI2ptZWHZV6Hjy4wu9lSaHb1y02UqQvOK558qq10hfqGukbrtIzrnqcWHlnTEIhpRSReg2PLb5j07WxptM3gsG/Ym9wURkVVej3fnZw0R0z1mFZZ9TkO4i2kKyaO8+7xTXAhAiS55SSzKgr68TV8k4gek3j4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Ugpa7kEd; arc=fail smtp.client-ip=40.107.223.85 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Ugpa7kEd" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OpPW4Ai0bdLuScNSRrKDLxdncF1JZDnQwB0XdqrjusbAWMYplVCkkXS+6YSpZZyHZnl/O35IadYkZwF32pd6LgW1XAnvl558cmCurWB8bs/fYuhIsnyg4AcICwQLgY7r9/ML4YMZPR2j96urFUyvXhKbV6UlwpV6cRCFPyXXIPyvfRfVmhiWr+iidD8pF3Gd/nqnFmEiiWOp5GSTzWBjdqbvUrFN2Vd6btyGaV3YdTxvrDEv+xioLH9fom66zIYxMzaDgQl8mWZWKxRosN9+tk7xX8vzcYcSwU5NpAuxX2mdJ39ZLVTQr6IsSGeMFVa8jKKTs81vwRYDC2ReISYizA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zCYKPCmOmQZ9rtDoq3Ggw9KJvwWQ2OcmrBUpWS9O0VA=; b=DGKcbZax/YPpdOIOPJ8OcD0Kdb8+Xjt9WrTRf1TXJPiocOMp7ipvHD77XXqT+8wym7G9+Qs5tvusMZ680dcTbVSdhOwkbZ0AzxFFPqLhBNhpGLdj39nSGiOHEKqjxIf1bjjfjX2q/NatYN+Wp+ZhLHZU6N874YYUOTFmXqbXPt7HqR/D/uv/2tJyVFw/HsJQPvxP3NRMBbkEg/6ZHLor0NbFDJuEtMQlvsvzuVHAm2aW16R9nERRu4V6XaTO6COhdwmfYJnNrvhpszpIawnhIDupXuzU+RzBB3vT98opQlDW3vqrWNjeU4MfiSjiwSgm3pIKtMpHoMKfWNUFDhmkmQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zCYKPCmOmQZ9rtDoq3Ggw9KJvwWQ2OcmrBUpWS9O0VA=; b=Ugpa7kEdgdcFStCSgBPV6+gZdvDROjcfJcCnTEmzyrWcf6TS3PXcOf9XQi2zPIySfp5tgNKFHJSO1kSZVyEQYJ7piMnk6EwtUMKySRLXpSTlGDPqho2wLF3dasAqM/jPUHDnaE23V3yfEHw4Kj7QNi8ezb0ZOMpFLQ1F5PUxhlrOYieX8s2ZQxsOh9vgekYbykEF//oD7sSPOdkIRdKGLPydfoem+BKyd7s6Qdgv2EyEfA+BK0l679e1OTorapxDZ4oEp/U2m/dH514kiFENJX8CjYmL/sGU39SX7BEUJ/ez8vpsuysAmbz4NtG/jzTbjt2RdecCfIQzQ2pCmPkNIg== Received: from BN9P222CA0007.NAMP222.PROD.OUTLOOK.COM (2603:10b6:408:10c::12) by SN7PR12MB7812.namprd12.prod.outlook.com (2603:10b6:806:329::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9052.15; Thu, 28 Aug 2025 06:00:00 +0000 Received: from BN1PEPF00004687.namprd05.prod.outlook.com (2603:10b6:408:10c:cafe::1) by BN9P222CA0007.outlook.office365.com (2603:10b6:408:10c::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9073.16 via Frontend Transport; Thu, 28 Aug 2025 05:59:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by BN1PEPF00004687.mail.protection.outlook.com (10.167.243.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9073.11 via Frontend Transport; Thu, 28 Aug 2025 05:59:59 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 27 Aug 2025 22:59:50 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 27 Aug 2025 22:59:49 -0700 Received: from kkartik-desktop.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 27 Aug 2025 22:59:45 -0700 From: Kartik Rajput To: , , , , , , , , , , , , CC: Subject: [PATCH v6 2/5] i2c: tegra: Do not configure DMA if not supported Date: Thu, 28 Aug 2025 11:29:30 +0530 Message-ID: <20250828055933.496548-3-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250828055933.496548-1-kkartik@nvidia.com> References: <20250828055933.496548-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004687:EE_|SN7PR12MB7812:EE_ X-MS-Office365-Filtering-Correlation-Id: 13522899-233e-4abf-3f4d-08dde5f81f5a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013|7416014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?23rGS2XrpnvjvDLpSZEWwvxbQqhYUVseBdYegjHwlO7P3x7F++qOLb08J0NB?= =?us-ascii?Q?dOYe9CIi2yFNIsrwpgzHSCZB/JZO65TdccCWh0oFkWceLokBTZ3A/VzFTZSs?= =?us-ascii?Q?ird7HGkSoxguGz8IpshWnNnEiOuhSkQFjzFnc6oxz7Xhatn4Dee0yI7XxVIX?= =?us-ascii?Q?okQG0EtWHbdiI6sWxzvOxGiuL+tksIcs1XEbl0edUq/o8bsK4twDufX0hp1u?= =?us-ascii?Q?O1lnUH3fOm/kXBmk+xIm17xR8WlrDCV3X2QATZxECz0iq4714BZStWC6QYE5?= =?us-ascii?Q?OauRJI4SZY8vKsCMKCaiA2MYWsPbBY7xkou8ESzgXrkVhgSls6DZBskiQK+K?= =?us-ascii?Q?erLAAf+3Y9y2d7zpz46k8dH0/egxbCzi9L2IolQ8tOkF1ReAs4EgRnJGPkb7?= =?us-ascii?Q?YXiOye01Ad1VphTi8ZWe6qHtkNUEqIAGyb7T0oXsQACUFMh0/XoYFoVbKJp+?= =?us-ascii?Q?Ff/I7KG9fF5TNlKz3je5vpGHz3cVR5/rptD7w8jCPC+FWlylqSLS+8f0zldY?= =?us-ascii?Q?w+53PIVCOHRWaKOXTFiFIC1qSXWRLImsRBZI4oMDOuRqQE2dKkxCbSi7Tv78?= =?us-ascii?Q?Y/kXpXuKekjvNctniVMUhFKuXYFMloBNE+utRrcqoM8fKHkb1tEFyu4PtZFc?= =?us-ascii?Q?AcY105Nbl/471hPKrl7lCrXMxqc2hLQTYl/KtKKox6t7ezGmzT8bpRCDoc/6?= =?us-ascii?Q?5brgzeb7JMPq0RH41vdsKYb5/zqaDJ6cc7Miy+zYAs2CfJgLJPC1XjMuF91N?= =?us-ascii?Q?iN+eGqrxKivyi74hxGn3226b7mYibXFz3Q9oFndr/FwTC14W75GtoulWBnd8?= =?us-ascii?Q?JCbWnE2SS4KF5iV7M8eXKESgGFJM2hpJIjcVca6h0wnsHAbw3MpRLAhAtExE?= =?us-ascii?Q?RNCz1/9vQpfrLvORjrB8ODXXJJMjpcy6cVdqeul/6qwGMAhkqKwSVUN6Hn12?= =?us-ascii?Q?4y6EKGKZjq95dPtLJx8RHP567eLkkwBcbB3MxSekp8zGPXSFnAw9R/YnpnUK?= =?us-ascii?Q?mCPgD3im3vOOu4jUe23a/eTnpSp5YnDTRVVXqJDpSukLArqbfixNoSiEcJos?= =?us-ascii?Q?xa2V5QwQABFOPiyiIysteuKkk3mHS4V4jITzJ8oijvoKXYURhcpwiuwWRPFA?= =?us-ascii?Q?XDgTkSlGMp+2y4fubVWIkiV+HGM7wsCDy6lkwsbPbN9/1JVu2XwwVAleC33M?= =?us-ascii?Q?PjjnMv2uIvAvRIV0QEjNcy7YSjYDxkjUOhiNFvWytkLabX5sN/uqHQdZNgWs?= =?us-ascii?Q?5nhJabsSU1rWLz1XVSolnq+YlfkvgpmQnrYDFcq3AdT4F3NSKPPuwfCXS8Ne?= =?us-ascii?Q?QWQp9Qr0MRD98j+vQO/MexVxgJmbwIEjpeZrRIFeP8C0lftqAoAD0FrWo9vF?= =?us-ascii?Q?bejxoDpvTyZQKqpJXl/ZmRKznguLAH2mi1E8MaPup8liL/hL0APjcP7VxCuC?= =?us-ascii?Q?K6w1NZL8ZxptC/YP4AKuk0ZRsokBMtkS8hHAKFW3zs1/FV0sD8ytL0s5V629?= =?us-ascii?Q?MlGQjyMJtxg+Emn3JJuljkeKnJm0cYWLG5jMvc3kXwqrzVZXIs3JNXrXnw?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2025 05:59:59.5227 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13522899-233e-4abf-3f4d-08dde5f81f5a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004687.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7812 Content-Type: text/plain; charset="utf-8" On Tegra264, not all I2C controllers have the necessary interface to GPC DMA, this causes failures when function tegra_i2c_init_dma() is called. Ensure that "dmas" device-tree property is present before initializing DMA in function tegra_i2c_init_dma(). Signed-off-by: Kartik Rajput --- v2 -> v4: * Add debug print if DMA is not supported by the I2C controller. v1 -> v2: * Update commit message to clarify that some I2C controllers may not have the necessary interface to GPC DMA. --- drivers/i2c/busses/i2c-tegra.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 4eb31b913c1a..0c428cba4df3 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -446,6 +446,11 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2= c_dev) u32 *dma_buf; int err; =20 + if (!of_property_present(i2c_dev->dev->of_node, "dmas")) { + dev_dbg(i2c_dev->dev, "DMA not available, falling back to PIO\n"); + return 0; + } + if (IS_VI(i2c_dev)) return 0; =20 --=20 2.43.0 From nobody Fri Oct 3 16:47:19 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2067.outbound.protection.outlook.com [40.107.243.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C194227FD75; Thu, 28 Aug 2025 06:00:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.67 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756360810; cv=fail; b=kD/2zms2+uHebHNS0A5S0uCPO1ei52FO7DLEOs7457ME0wVqFQLhy03tbzYv7sSqQubLIQZaDB0/ldDnSp2mpG0U88wuSvfdCjwO2wli8vaphZEAS6EAiqwQ/aprUmSKayYQxglZkJLpydbRFCdMqAmWGXotRlvm7D/E7L9q9Sc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756360810; c=relaxed/simple; bh=2VMW242CtkOQ+PNfot0klWHe1n3VaxA1T1gab/rP16A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MT3VPAReVE+KA+7+LXS7+RlpCoGBh4kKgRK+zYI82iGaXKpUK2xXfqY6qmhiu2bokfcxjS+MsQCCZaED0+HO/GMI7wlp+ROYmCJ/w8GZA8w2nIj8w/pLrQCrUU48YrfqcsITUICGGFr3k6lOUXE7No4g819mbysQ5tPy3Xnnp/0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=IZzf4vih; arc=fail smtp.client-ip=40.107.243.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="IZzf4vih" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=QoY78D1kJC3yno+tae9Tb/GxbdDPWeiFqGgMEi4p4OCLLNqSg/ozCVDbphZfoEGFRAvWQJX7WAifyu3HWS3x2XrcMlHjOtcweJHtsJJKvl6vmVHJMuX5G5ZFIDRvcHRdh0UKzKKmbVBGrGoUNq8sMy2HiPel+eMP8DhCopg3xMhkzhOWtFh85m/DrcEdxsglnSDVcpCwPFK/s7LFrQwBfczxMMj+q2gLlflhqSNJZSMIp82KKc4xI0Zju8BV2lnLR0PVVoos7UDiAJ4YeaUploN0qOED/6aPTI1ksoqQUF+oPY7gnxSEbTARx+JW4qCs32wl82j2Jnm9d+hnjyGqAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hRg0JU/yjvdLxd9Z7WD5qPZ5qDytPrEVsV6okmmrTew=; b=VEyu7p6e9GrTVZroIbeyonkRpP2OnfnNsTUiLgX84b9cTiKoNW9lB/VXiPUOCxRcM4ZuH7pSdlrVK3XdI4/g3NGtgtKKxp64SHQNF1wYOnlYzw1893WzYhgp/b6eSI3xNJNu2UaabBFPWXRMB998TkqA0MvGzez0Mi6G/jG7WX2uoBMaTmbDo55QRnwHIMou3FzBPO/Qn03mqdQgH8Q6XcX++OuAw32i1l0ux8ikjKU+Mj+rUGlNEoasKOxQXe6P/QuI20g3nTMlC/96j+lckbsQl5alBvYbd8no5TX4LFf3STiBlKA340h3zIzUkBffc+CWeJVE3DYRvoCC/E5h+g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hRg0JU/yjvdLxd9Z7WD5qPZ5qDytPrEVsV6okmmrTew=; b=IZzf4vihKzSHPawQxFk/29NDu0M8h8GOEWQWY5uUuMFy6s2eIoes4148yobFgBCFWnNI9hHiPbq9tZwXdFHZCnaXur1//EMzHHwJzWRrAx8EC7FwyF9lmflvNCIHqLYVWakgYYbiTobO7C0U4lniO7W6QK87Lff9jXlZ99Yjf/+GsSFZYvsVv9KIik5V6VyPsxCgKVy/Uyi/LT6mGbJONVqN/JY6dxRHlrJcrVjiz0o0573a8CPsg7iANUUN0YZiuVkqfqSXi2Bf7cyWpurGX3jqkVL5enGDL43jctlxO6VKHqrQInFZECjdLsC2qevaiJUcd08fO0VXTiS7Z8xxtw== Received: from CH0PR03CA0223.namprd03.prod.outlook.com (2603:10b6:610:e7::18) by SA1PR12MB9548.namprd12.prod.outlook.com (2603:10b6:806:458::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9052.15; Thu, 28 Aug 2025 06:00:05 +0000 Received: from CH3PEPF0000000F.namprd04.prod.outlook.com (2603:10b6:610:e7:cafe::f1) by CH0PR03CA0223.outlook.office365.com (2603:10b6:610:e7::18) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9073.17 via Frontend Transport; Thu, 28 Aug 2025 06:00:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH3PEPF0000000F.mail.protection.outlook.com (10.167.244.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9073.11 via Frontend Transport; Thu, 28 Aug 2025 06:00:04 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 27 Aug 2025 22:59:54 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 27 Aug 2025 22:59:53 -0700 Received: from kkartik-desktop.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 27 Aug 2025 22:59:50 -0700 From: Kartik Rajput To: , , , , , , , , , , , , CC: Subject: [PATCH v6 3/5] i2c: tegra: Add HS mode support Date: Thu, 28 Aug 2025 11:29:31 +0530 Message-ID: <20250828055933.496548-4-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250828055933.496548-1-kkartik@nvidia.com> References: <20250828055933.496548-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000F:EE_|SA1PR12MB9548:EE_ X-MS-Office365-Filtering-Correlation-Id: a1a0f20d-d4f4-4a1f-539f-08dde5f8228a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|7416014|1800799024|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KvTX7f994UEYeiUmPLDQTK9boixX7YyP4M+ltzAyO1aMg5D2l1TjI3gMTWC4?= =?us-ascii?Q?ivIc8pREIUprKttu+QOchPwoin0qzjcTgqUlMCjEJxngCalVwexjWxU9yGoO?= =?us-ascii?Q?i7/Mozm8qfAfks/Ww02Juxdl7j9gjBM/L6ozwp98NtvMVIZK1wgxdA5uGneW?= =?us-ascii?Q?k6+4X/gRlrKU8PQ3ujSdTTlpyOLN7ESP922g3pUEILBNoDxCct/deJPTDME7?= =?us-ascii?Q?3DG6hMdAgSQgq6CuZQPoi2WOfFlfRDdxxYKwZ14EdSJtDzq/A0tnPQsAHdJo?= =?us-ascii?Q?qd82a9DJKbgHH/HwzUxiznLPD6TpfHaGtCXZLJcMfdaGprA7fr3Uleo2VoKU?= =?us-ascii?Q?Wacao/f0TEM2TLranT/yDeV1Fga+TCvI7mT9RQrfhJpNiC0v3sXECcYDPm96?= =?us-ascii?Q?r/Pz/wBCPWlJKpoLZrIF/mvAWefmLuetUrTMCroIm8LtAE1EeffgTUa4EBEe?= =?us-ascii?Q?Vi0XqdLBIqu3tYAJovoQOcTNcZr5oUVLVN7OD6XrD+EX4CVK2NWNVnG4LjrX?= =?us-ascii?Q?Mjalzs+Ig1gn1f9QY6VCANH9Fzfn6GBg5m3R57Me4zpUhJe6uCraqGoCz3mQ?= =?us-ascii?Q?TPA+n9xo22LvhB/gyeYHOrmYYnMx/xoA15uwCrzXBFvc38Rg5B6y2lZcwNH5?= =?us-ascii?Q?x+v70YOI8/ubeMNs71NzS1tHT5BFApZ2tLmoyr3ZHncdcdsk9kUlsDhBJ1vR?= =?us-ascii?Q?uahxA9pjbjaYlzNJZBxcoZ4cNqg7byIPZZWyixBtdhB3GCBNu9HZMVoFfvLN?= =?us-ascii?Q?3WSVCVj7q2HsT+/ckwiQjU05ioviRLCXrATd70zDZVQvBDl4Wd59GZLHgglY?= =?us-ascii?Q?Y+U3zUiHgpvM2R/3RimQ1osHrsLhvbyFTtZ2ErZc72mBdM0dtu6gex9CpgHD?= =?us-ascii?Q?/yCWUCdMijLlva6aAelDpyutQlr5/VkzqyyE5QfN169PrPyydF8wURpI8F4F?= =?us-ascii?Q?0dCKlrGk9tUkI/r+wbC2fIqRjwB1IRQEdnUaCzkOM8yeUh9hbojgg+NU/au2?= =?us-ascii?Q?UBCv/+Op6/6zoy7sqoTCdKSnZi8yuk7jrmlsNKJsMmIkinFpIhXbRzGlpWE+?= =?us-ascii?Q?JDiojh/4GN4bdCcxxNAGm+L6gse3ZFpWMO6zN6M/fZcUU86dT5qy0FUChCOM?= =?us-ascii?Q?QAMvbpY537UUCITbUqlwRO8jHyp/ii1fQP7Y/d3xYGPX/W3//NZ9+bg3pDKr?= =?us-ascii?Q?cn+xGt2PFTzr2WVrbAND9OQ+bTT5ICHI4FKhtb9d/I+3Yws9oaVGLBiB+q85?= =?us-ascii?Q?Rgxy35pLmFznDraw8FqTBUrz6W7XIb6abVzc9bVN+ZMHhkcevR7j25UUE6bB?= =?us-ascii?Q?CIDhG1zWGrM5UmHl/zmWSxmhagYewELIEtFQMybpR5sWZZmLEtM4NSog+zkN?= =?us-ascii?Q?SOImcQOHqsm12FQehay4sYnETXAHB+6SWS7ttt+ucs/PvRKJDCkwvKwEuk+M?= =?us-ascii?Q?zVHPpNHFMjKwLa4NO/vyB/9vOPedGrigbN1oa9gIcMhrI4YkiB4E+iEQwmcD?= =?us-ascii?Q?Wvjvxg3haHjJyTTnG6LEiKTPpTDujKIy7CKdkcnVvlyjOvVJEFNQDewtQw?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(7416014)(1800799024)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2025 06:00:04.9228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1a0f20d-d4f4-4a1f-539f-08dde5f8228a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9548 Content-Type: text/plain; charset="utf-8" From: Akhil R Add support for HS (High Speed) mode transfers, which is supported by Tegra194 onwards. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- v3 -> v5: * Set has_hs_mode_support to false for unsupported SoCs. v2 -> v3: * Document tlow_hs_mode and thigh_hs_mode. v1 -> v2: * Document has_hs_mode_support. * Add a check to set the frequency to fastmode+ if the device does not support HS mode but the requested frequency is more than fastmode+. --- drivers/i2c/busses/i2c-tegra.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 0c428cba4df3..20d5c8a6925d 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -91,6 +91,7 @@ #define I2C_HEADER_IE_ENABLE BIT(17) #define I2C_HEADER_REPEAT_START BIT(16) #define I2C_HEADER_CONTINUE_XFER BIT(15) +#define I2C_HEADER_HS_MODE BIT(22) #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 =20 #define I2C_BUS_CLEAR_CNFG 0x084 @@ -198,6 +199,8 @@ enum msg_end_type { * @thigh_std_mode: High period of the clock in standard mode. * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus mod= es. * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus m= odes. + * @tlow_hs_mode: Low period of the clock in HS mode. + * @thigh_hs_mode: High period of the clock in HS mode. * @setup_hold_time_std_mode: Setup and hold time for start and stop condi= tions * in standard mode. * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and= stop @@ -206,6 +209,7 @@ enum msg_end_type { * in HS mode. * @has_interface_timing_reg: Has interface timing register to program the= tuned * timing settings. + * @has_hs_mode_support: Has support for high speed (HS) mode transfers. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -226,10 +230,13 @@ struct tegra_i2c_hw_feature { u32 thigh_std_mode; u32 tlow_fast_fastplus_mode; u32 thigh_fast_fastplus_mode; + u32 tlow_hs_mode; + u32 thigh_hs_mode; u32 setup_hold_time_std_mode; u32 setup_hold_time_fast_fast_plus_mode; u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; + bool has_hs_mode_support; }; =20 /** @@ -717,6 +724,20 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_de= v) if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); =20 + /* Write HS mode registers. These will get used only for HS mode*/ + if (i2c_dev->hw->has_hs_mode_support) { + tlow =3D i2c_dev->hw->tlow_hs_mode; + thigh =3D i2c_dev->hw->thigh_hs_mode; + tsu_thd =3D i2c_dev->hw->setup_hold_time_hs_mode; + + val =3D FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | + FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); + i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); + i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); + } else if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { + t->bus_freq_hz =3D I2C_MAX_FAST_MODE_PLUS_FREQ; + } + clk_multiplier =3D (tlow + thigh + 2) * (non_hs_mode + 1); =20 err =3D clk_set_rate(i2c_dev->div_clk, @@ -1214,6 +1235,9 @@ static void tegra_i2c_push_packet_header(struct tegra= _i2c_dev *i2c_dev, if (msg->flags & I2C_M_RD) packet_header |=3D I2C_HEADER_READ; =20 + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) + packet_header |=3D I2C_HEADER_HS_MODE; + if (i2c_dev->dma_mode && !i2c_dev->msg_read) *dma_buf++ =3D packet_header; else @@ -1502,6 +1526,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_= hw =3D { .setup_hold_time_fast_fast_plus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra30_i2c_hw =3D { @@ -1527,6 +1552,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .setup_hold_time_fast_fast_plus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1552,6 +1578,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .setup_hold_time_fast_fast_plus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1577,6 +1604,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .setup_hold_time_fast_fast_plus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1602,6 +1630,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c= _hw =3D { .setup_hold_time_fast_fast_plus_mode =3D 0, .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra186_i2c_hw =3D { @@ -1627,6 +1656,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .setup_hold_time_fast_fast_plus_mode =3D 0, .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra194_i2c_hw =3D { @@ -1648,10 +1678,13 @@ static const struct tegra_i2c_hw_feature tegra194_i= 2c_hw =3D { .thigh_std_mode =3D 0x7, .tlow_fast_fastplus_mode =3D 0x2, .thigh_fast_fastplus_mode =3D 0x2, + .tlow_hs_mode =3D 0x8, + .thigh_hs_mode =3D 0x3, .setup_hold_time_std_mode =3D 0x08080808, .setup_hold_time_fast_fast_plus_mode =3D 0x02020202, .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D true, }; =20 static const struct of_device_id tegra_i2c_of_match[] =3D { --=20 2.43.0 From nobody Fri Oct 3 16:47:19 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2061.outbound.protection.outlook.com [40.107.237.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D27A0278158; Thu, 28 Aug 2025 06:00:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.61 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756360812; cv=fail; b=nlSM8GwZkp1OPo1de0ovc2rIDQnx22v3JLkRHF8rP26xI+ZkOIAT9BPQ8OKw/fCVLjqZzdiw1Nu7+wsO2DWcHsaLmtpop6NkOS1pzh1JjHvK9QncX+NUz6dPOim9B5ka2FWVGPQfgwfCo2Gdunm3a1udqsF3UvkQ+mCVRK/vx68= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756360812; c=relaxed/simple; bh=Oljk+NrQM81Yd638pCNPdPGte1+VQl/Uo3zi24cK6XA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fPIntL6K+Xc4+hBQx7NkvsjD1mo0X3wb4kgL4/28DtjTk3YtyPWHdGpvKfVNOm5lrlZC111o1Uw2uoPiwk6mLLR5aoEvf/gREBKfQ1o2iotLhY4OeJhcuWETprYCOIrv5tTJh158GgdaPZKC3cXtvr7uqW6Y/w4ZvJqUv2CCJCg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ikP+gfeA; arc=fail smtp.client-ip=40.107.237.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ikP+gfeA" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wN8NkDnhsifZn95cypxhE27d2+j0lggEr0/KmWZ8AppiosgzRWTGPQwKMbUj4WgH2xsRjj7oF6D57JqeIdxQhDfo+6wPlz6RaJtWRT+2SaqO27i0cAUaavzKlg6ctRoNnP7rKJPWPgp1wBpgX+4f4bPgYT7q2pBTZFPakoS1nsoepC7I9mfvfAla88YdDkxKlkFfn3G6t1AwysrbQ11JstWkkGlwE5SvMGgerEVZvuQnvAoeJJZ/6Ne2OgAG8SiyZG3LNOBC4t4nYVq2O1ehswbADDqYF2p839v68eRL4XiC3XPrSATYGRMNgLjGlqLTP4scSDYXJ/A7NYl3NNCTGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ReUomarV8sR9Nn+0rHkhkpulrzJUqqUjKScErWMjDcs=; b=T6sJ7FVCAH/YHJuqIgcuekocU5VTDZx5PpPejqECNfSYmatuirNRZvCPLJZTZISvm28TZT+jG4gBRAop6b0xOC1nm9YIks71/XZNICN9yNg9iq9oG7j+iz86GuxtuBD8EiJKL0pLWl9v9f27wI5xdiAddA62KqjdvgTPWEoP/7u/CM89cjTzPPrUONFy0CV8Yrjq8+pnToUcJV4UUEP2ThI40HoiS0IyGG2l7/5Ig8XR2gTXjlaNUCrdnK+b5GpQ1idh3nw5xLFi5n3bL5UqiuEEjGPIKCRPOr7I/95H0/UQQF5TMNRYhYcwFnN0Xx0tbzGtOFYREBR4GsnyETcrCg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ReUomarV8sR9Nn+0rHkhkpulrzJUqqUjKScErWMjDcs=; b=ikP+gfeAKfdGkGuTBCMlkNzfZbevNyhlULK+YUZb/6RiGKt8BZ9eovbNg8pIajCqbRj1J1jUU/vYB+lO1bAkQ+EmZcr9JqgMoYQaJT2NzRxjBjWFqacQ7pXSb97vSwPk9p8kL1sGWAoNF4wyuD7txwRIjUyfDSlmo1qGnDsehV31QvGOg6TivlMQo6m9lTkDpIcIgYQp7Tfwec0lWf7NWNJZRHAdKIkHpRWGM2JJCFjZNmjHjryw7R/dLMSTtsAM47TY+MSKanXUVO25PErzosnN/PEvD19Rfa2Gl6BmCfZ/1TV3NphjLB6vrmy8hbvk7mCYNNGVVHTtnfkv/Q3RZg== Received: from MW4PR03CA0242.namprd03.prod.outlook.com (2603:10b6:303:b4::7) by DS0PR12MB8198.namprd12.prod.outlook.com (2603:10b6:8:f2::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9052.21; Thu, 28 Aug 2025 06:00:05 +0000 Received: from SJ5PEPF000001CF.namprd05.prod.outlook.com (2603:10b6:303:b4:cafe::bf) by MW4PR03CA0242.outlook.office365.com (2603:10b6:303:b4::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9073.17 via Frontend Transport; Thu, 28 Aug 2025 06:00:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ5PEPF000001CF.mail.protection.outlook.com (10.167.242.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9073.11 via Frontend Transport; Thu, 28 Aug 2025 06:00:04 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 27 Aug 2025 22:59:58 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 27 Aug 2025 22:59:58 -0700 Received: from kkartik-desktop.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 27 Aug 2025 22:59:54 -0700 From: Kartik Rajput To: , , , , , , , , , , , , CC: Subject: [PATCH v6 4/5] i2c: tegra: Add support for SW mutex register Date: Thu, 28 Aug 2025 11:29:32 +0530 Message-ID: <20250828055933.496548-5-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250828055933.496548-1-kkartik@nvidia.com> References: <20250828055933.496548-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CF:EE_|DS0PR12MB8198:EE_ X-MS-Office365-Filtering-Correlation-Id: b2a43d10-3700-4296-a40c-08dde5f8227e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014|7416014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KvAiTpvBaLn6rI/OaXinSrjOyIFV6L/pp+56SeMdiLuj8+h+JFFxza3VFt/B?= =?us-ascii?Q?nQW7bKIbRsUKxzmWpTlR0HFjL2QkvDiRikHmt0li0wRVdRotHTCn2ft/vsqM?= =?us-ascii?Q?ZtivXqDCWMsk6wRvP394kgughZ/4hNtLcGz05sjwEudm9oK5BygGdtFDcqOw?= =?us-ascii?Q?YsDn8aqC0seRWsnHFKSfVj1sT6uuVRva0XJGPoHMQ+PXUnQVJH3WeUh9P/3V?= =?us-ascii?Q?G1puS4tluBXiQULDChfG+Ti6ExyiIEjuvWEDj/CkBItxXbh0/+2lbK40ZFNG?= =?us-ascii?Q?FsqG5nNpOF0MvIONNI8uTDv0N2RxxF+raATIhY6P2hLayBiejdiCpxGKcT5+?= =?us-ascii?Q?y5V8ouY1NZk3cT5f6DMcir0lJpeIFLWtgejhoGqQ8n8f4O4GzGUq5I4psGZ8?= =?us-ascii?Q?33SQOVIMSIjGyvfa+UpfQBBXDQQHva9ManBv29jzYYeUS6zAyQJ8vYTzrtWW?= =?us-ascii?Q?YyPljOxpNy3ozRGY/v+6kCFeZSrQ6EvmgdoVI7mF1iGG23XXE5oQMeXbPG3E?= =?us-ascii?Q?WqoVq9HkzXpiRVh6yi3rF/sBQ8/iz+UyvLNyIjzT3e9ftHWWDeunpmK8oryd?= =?us-ascii?Q?PKUsDEYZU/1U7DfPVT4WPRK1g7VsB+SwXFDYot0cqN8BZo7Kxw0LNgCcFkqp?= =?us-ascii?Q?Es+G/GqjBHX/pRqxV+tHWK0+rPYcny0AUwtQ8LSWOErpU118s7LVnzIAdR5D?= =?us-ascii?Q?HuYEWEWeXVmDilfkZsr1t+Og+CCK2ujDvUZBgHSMnVTrg+R76RRRUMs06sgB?= =?us-ascii?Q?IO3eY1997FrbXGSTFQ65XcLmw52QQ1KVTtKkdaxA9ICo+xLypIxC5zy4J9Wl?= =?us-ascii?Q?1ySCkskQYSeUuhU4GCriV9NjHN6WKaqsNtozu7CT7Da74tR6F/ip7we1zK2o?= =?us-ascii?Q?uf6OhoAwjHMAvxFoaogaAq86bN9B79hcurZ/IXLQJ1ArzwjfRvL1AIiWOgQv?= =?us-ascii?Q?+daROGlZHL2SofJ2Cy3fRPoY54fM+9Sfy1Of4tvpAfGb90yfanDFjr1Ov4Ai?= =?us-ascii?Q?7GsGJ73hOuKqvS8t5lFHBpn6LmWTYWgrGZrsNwXRFUFQWOI6T7iqHzM+rYZF?= =?us-ascii?Q?+I6ZLj4IX+BhOkv05q3J+/CPzvaDXNfG6sJ1+7JMBsxq2g5daeyT5DuOXzR0?= =?us-ascii?Q?yNYD7skMvL6ij4Uk7Hes9dLBULgpjTyvTWyXsIrq7OvWWwfZL8HQ0vg1YloM?= =?us-ascii?Q?yj7O1OinxZZNu8VzxXqsWdyCXYtUoxrvCKHgC3m6TgfC6dCvynEs8J+MlWFr?= =?us-ascii?Q?OIh8CgP7SDV82os+CBJW66cg0smBvsVmGlRizg7GhV6BzB9zYRLyQy4t+UvT?= =?us-ascii?Q?hRgxV2e0HggoyWemx4/VBI8rt5y1/4xSd7fo+/lr5xVrzUUKt90C6SUYJk7z?= =?us-ascii?Q?rXPMsmTEoS8KDaCKVnqKTkyN8fgPSPXgvy12cXlSL/2EReP0VhKqjhPMcY2/?= =?us-ascii?Q?aSslVjDtJCG5/cne7CjX1M3bivNDsnHhywGOvJ35XI/4LRvD2KCUlxwLaMBr?= =?us-ascii?Q?CKxCwIwhbS96GGgBlVI7KWAqqO0x97XZD0GAN/6n0kBq6X295kDP/+aGog?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2025 06:00:04.9605 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2a43d10-3700-4296-a40c-08dde5f8227e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8198 Content-Type: text/plain; charset="utf-8" Add support for SW mutex register introduced in Tegra264 to provide an option to share the interface between multiple firmwares and/or VMs. However, the hardware does not ensure any protection based on the values. The driver/firmware should honor the peer who already holds the mutex. Signed-off-by: Kartik Rajput Signed-off-by: Akhil R --- v4 -> v6: * Guard tegra_i2c_mutex_lock() and tegra_i2c_mutex_unlock() to ensure that they are called on platforms which support SW mutex.=20 v3 -> v4: * Update timeout logic of tegra_i2c_mutex_lock() to use read_poll_timeout APIs for improving timeout logic. * Add tegra_i2c_mutex_acquired() to check if mutex is acquired or not. * Rename I2C_SW_MUTEX_ID as I2C_SW_MUTEX_ID_CCPLEX. * Function tegra_i2c_poll_register() was moved unnecessarily, it has now been moved to its original location. * Use tegra_i2c_mutex_lock/unlock APIs in the tegra_i2c_xfer() function. This ensures proper propagation of error in case mutex lock fails. Please note that as the function tegra_i2c_xfer() is already guarded by the bus lock operation there is no need of additional lock for the tegra_i2c_mutex_lock/unlock APIs. v2 -> v3: * Update tegra_i2c_mutex_trylock and tegra_i2c_mutex_unlock to use readl and writel APIs instead of i2c_readl and i2c_writel which use relaxed APIs. * Use dev_warn instead of WARN_ON if mutex lock/unlock fails. v1 -> v2: * Fixed typos. * Fix tegra_i2c_mutex_lock() logic. * Add a timeout in tegra_i2c_mutex_lock() instead of polling for mutex indefinitely. --- drivers/i2c/busses/i2c-tegra.c | 97 ++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 20d5c8a6925d..88ee27f90526 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -137,6 +137,14 @@ =20 #define I2C_MASTER_RESET_CNTRL 0x0a8 =20 +#define I2C_SW_MUTEX 0x0ec +#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0) +#define I2C_SW_MUTEX_GRANT GENMASK(7, 4) +#define I2C_SW_MUTEX_ID_CCPLEX 9 + +/* SW mutex acquire timeout value in microseconds. */ +#define I2C_SW_MUTEX_TIMEOUT_US (25 * USEC_PER_MSEC) + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 =20 @@ -210,6 +218,7 @@ enum msg_end_type { * @has_interface_timing_reg: Has interface timing register to program the= tuned * timing settings. * @has_hs_mode_support: Has support for high speed (HS) mode transfers. + * @has_mutex: Has mutex register for mutual exclusion with other firmware= s or VMs. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -237,6 +246,7 @@ struct tegra_i2c_hw_feature { u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; bool has_hs_mode_support; + bool has_mutex; }; =20 /** @@ -381,6 +391,73 @@ static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, = void *data, readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); } =20 +static int tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val =3D readl(i2c_dev->base + reg); + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + + if (id !=3D I2C_SW_MUTEX_ID_CCPLEX) + return 0; + + return 1; +} + +static int tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val =3D readl(i2c_dev->base + reg); + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id !=3D 0 && id !=3D I2C_SW_MUTEX_ID_CCPLEX) + return 0; + + val =3D FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX); + writel(val, i2c_dev->base + reg); + + return tegra_i2c_mutex_acquired(i2c_dev); +} + +static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev) +{ + int locked; + int ret; + + if (i2c_dev->atomic_mode) + ret =3D read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked, + USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US, + false, i2c_dev); + else + ret =3D read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_= PER_MSEC, + I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev); + + if (!tegra_i2c_mutex_acquired(i2c_dev)) + dev_warn(i2c_dev->dev, "failed to acquire mutex\n"); + + return ret; +} + +static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val =3D readl(i2c_dev->base + reg); + + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id && id !=3D I2C_SW_MUTEX_ID_CCPLEX) { + dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n"= , id); + return -EPERM; + } + + writel(0, i2c_dev->base + reg); + + return 0; +} + static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) { u32 int_mask; @@ -1422,6 +1499,13 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, = struct i2c_msg msgs[], return ret; } =20 + + if (i2c_dev->hw->has_mutex) { + ret =3D tegra_i2c_mutex_lock(i2c_dev); + if (ret) + return ret; + } + for (i =3D 0; i < num; i++) { enum msg_end_type end_type =3D MSG_END_STOP; =20 @@ -1451,6 +1535,12 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, = struct i2c_msg msgs[], break; } =20 + if (i2c_dev->hw->has_mutex) { + ret =3D tegra_i2c_mutex_unlock(i2c_dev); + if (ret) + return ret; + } + pm_runtime_put(i2c_dev->dev); =20 return ret ?: i; @@ -1527,6 +1617,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_= hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra30_i2c_hw =3D { @@ -1553,6 +1644,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1579,6 +1671,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1605,6 +1698,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1631,6 +1725,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra186_i2c_hw =3D { @@ -1657,6 +1752,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra194_i2c_hw =3D { @@ -1685,6 +1781,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D true, + .has_mutex =3D false, }; =20 static const struct of_device_id tegra_i2c_of_match[] =3D { --=20 2.43.0 From nobody Fri Oct 3 16:47:19 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2048.outbound.protection.outlook.com [40.107.237.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BA124A02; Thu, 28 Aug 2025 06:00:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.48 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756360825; cv=fail; b=WvfJW/gWq8NDn31ztpF71G3v96qWgcDVJ2oqEMKmTQFjkoHfMmmxzckQ9rAzW8SFbXDfioTKS97qjAMzTQb5FJtZFDtYZ/vntUnxjKXuY4opv7Eauw4J7l0HCQWW75EBJF8O60BHCByEGuhh7Sv3cttpFPyeUrPAXuDP5f5Kd6c= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756360825; c=relaxed/simple; bh=G4VV19jFqs856+Ggpi1/frm+DoMPsmAx2gllTXWL7CQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=s9LVhkW+X2xqF5OwKMzVw4EG1vLbAZqqchKyY2GtLZ1JWOCm/xUHX797/PCZnIYdR5CS8mhlsCPX4HJQkkAJx4624RBTrOXmIzeR3r94emFr/NlISgeD/76l7ecfh77vNLJPNC5m2Y4ZnskhymH/0TkXfReRPNLUjiXcJXkDbK8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=kfibw37F; arc=fail smtp.client-ip=40.107.237.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="kfibw37F" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=bdEcDz/oesTheBdoPUX8b+RgPWfJSwnTU8WyBUSAgZos0mjgkNUNGq/9z7h/ThfoU2vQNsdQDjSYe1FQ0P8tsrxDDN/9uSvLQyTRaMV/HSMc8ovGc2UqW3gjPOhEjDJOim6GnNWXzseM+wQTVB3KKX+Tsl61cDpK3vP5g9WADBGzulnRBL/sIqldHZdRTJDpbKHxSLvx8K62ndgeFA+Aptgb3cWpPqgD2YYyYo/XmWGBgV/o8xGVkl3Fs9SrhlIzUBQAHqIfnEk6Ho98Ip4JDHb3lFxdImr5ZN7vo5EYe6doLyG6CuvtA4B8Pg4HeBS74h9B+/4ZP6RTjj6gCBpHuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Wr/r5hvoMGqP7vXY30zVWnFPbtOtAcqwd+9ikZuqK1E=; b=IXNz8NURYT83nhAr2etp3ik/61cZoFXwyDd8pmnVyPRUEATjrh23orkMTpU2IMKatgR2LReiDy4yCWHz6O4b/36UwP9u+H+XjZs+nuSTZ/Mx0wyRRVizgE2XkMt/HxV7OLry/bKxzenNsiAv7RugUAjOYOCR3NL7FNXDwzVP3jPRBdG9MVjQ1+2xD/AcKtJA4uozo98BXzVU/dtC49RZ6AVGLeQLQFmXEw1a/JY6yNYXIhv816jZQMRLyNJ2kLczyGBdwB7XXsji3ksqtUgrLi9h60Y9bnMv7pGhinlRBDQy805yruyqz02uRsA5Nw7kBVdUlDcpIHXSjlIqfmxYGQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Wr/r5hvoMGqP7vXY30zVWnFPbtOtAcqwd+9ikZuqK1E=; b=kfibw37F9K2RL7hrfFStJTVMlLJA/3YXEpygShcTaGRR/JnaKtO95q60WKPeuvXQI6qALoDlevvn3fCY32tnlpMnr+S4RXxeywtwIGmFgqInDM2TNDJNtelwf6hhDiAFDaItjduiEQbasNbd5MLfD1P4rZ7/Ik2sQTmQe9iuK+fYJNMCGjFLtGupMgorbknz+Dcgsm9fToI18MLben4sXZgdfEFcFMoMx0ms66rJvPK+7pett6ZHEKfLR5Ef2H6Dvss6SReGT7xJaQjw9GAtqrs0YNGKi31JOucMAmRB93XB92UQhVBZag/8fJC6wPWPv2MMZvOfCfTrRgneZFqkSw== Received: from SJ0PR05CA0075.namprd05.prod.outlook.com (2603:10b6:a03:332::20) by LV8PR12MB9134.namprd12.prod.outlook.com (2603:10b6:408:180::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9052.21; Thu, 28 Aug 2025 06:00:18 +0000 Received: from SJ1PEPF00001CEA.namprd03.prod.outlook.com (2603:10b6:a03:332:cafe::1b) by SJ0PR05CA0075.outlook.office365.com (2603:10b6:a03:332::20) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9073.10 via Frontend Transport; Thu, 28 Aug 2025 06:00:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF00001CEA.mail.protection.outlook.com (10.167.242.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9073.11 via Frontend Transport; Thu, 28 Aug 2025 06:00:17 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 27 Aug 2025 23:00:03 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 27 Aug 2025 23:00:02 -0700 Received: from kkartik-desktop.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Wed, 27 Aug 2025 22:59:58 -0700 From: Kartik Rajput To: , , , , , , , , , , , , CC: Subject: [PATCH v6 5/5] i2c: tegra: Add Tegra264 support Date: Thu, 28 Aug 2025 11:29:33 +0530 Message-ID: <20250828055933.496548-6-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250828055933.496548-1-kkartik@nvidia.com> References: <20250828055933.496548-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|LV8PR12MB9134:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a2ce25d-07be-4706-7144-08dde5f82a0e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|7416014|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?CJjUnvQw5kE8wmWs/pqkVt7/8pg9bC7blHtmj/C0PR31DPb/Ku7OiHQ3thV1?= =?us-ascii?Q?EAjdrZ6Vdkfxx2XdsFq6zeaukJiWTlojg+MCcRgt7gyAt+OBKoEgoRakQfv0?= =?us-ascii?Q?xbamR/FIRcqPf+X8/MuibOWXDGWcqE9z4OGnPfZTNq9OXCb7xhD/7HcUq8fh?= =?us-ascii?Q?Wy5YefKhMEBvZy1pAck5S6+qwh1EWtYOoT4wSJzc8hlNz/BPGAwl8Ol6dYQm?= =?us-ascii?Q?rJyLXAV+U9HUkfbtCbSiOq3QvJQ3ye56pFBdvw+3jTFkNGJj5mfbmgKTGlIR?= =?us-ascii?Q?G6l4Cm5/KKvDc8N9eViWFwWPFlPGpiCSbgFZogudZQuIT0wp1rx6dEcbjpkh?= =?us-ascii?Q?QzobdOxXpDPbWY13w5seEbON6Z43/BEXDlpoarMfaEaSwvfUTjjg7URA8HKT?= =?us-ascii?Q?b7eyf/vhrcnBFs+pSApm5E+F+uV/sywxjWTrq31u9Z2v3KPHQgkItGrvO2yS?= =?us-ascii?Q?dQ7syj59WDVoaSb5/4G/DaS25rRpK0oBdnF8N9IacBeijdGtUH0ChxQptgvJ?= =?us-ascii?Q?8QiTlNc7MegF0GqmIUiXbtKrQg3L7BzCVvt5sjVlrPvdeNTMIkXi3YtXQM35?= =?us-ascii?Q?ocE5W0ry0BqSASFs7XiwM7HEc5aWFrB14NTfUwmxmUQ+SOiLJceMn7YYbLB8?= =?us-ascii?Q?TuoVGa85JoC4Xt5tuThFec0DjzIk2SeUFbDkf4XQHdddHJpunAEiySuHPfbZ?= =?us-ascii?Q?o5H5yLB3Oem3mp7+Wvc2Vxt9osG7S+PTH5xE3AzHMXOL3LxNO1k0H1Dm7agg?= =?us-ascii?Q?Qdfn4w1rsiqBvh+xoXnpXM2eMOxulwpeqtY9cuet09p1p7Y+Z54t3KkSJZwY?= =?us-ascii?Q?H0CBtC35IMrNhKkd43mNx0q+IBSHJZ9rZRxYWbUP0Pad0azHhE+nvZAkKBdf?= =?us-ascii?Q?E0pqOqPaOYNolMx72H/1BKxcdbHMmEOUbYwTedDz+oIChzygqEW7jAvXcxeV?= =?us-ascii?Q?FSWSFkLrIL49AqOawdsx4P0ju8Nb0AvJ1QOuOhGtNo3W5ir6ySxPfXPiOsQD?= =?us-ascii?Q?EXwU5z5htN7r+ocrA+j2tUUNmBVeQYaRyVTmphv2TuRlFIA/EuatPnoxS45N?= =?us-ascii?Q?Hssia4s1hnA2d2yi9Ejv82vZEKcSn42i0IiJgQnkAWQ01QUR3Ju5cdOkpiKd?= =?us-ascii?Q?BJnQNvmsrBQcFQh42usPnrpcBZfNE9O5uiFNcAF6I48PuAPl/5rOo0+4mG1e?= =?us-ascii?Q?X2unV/vtO+8hUIqbPwO0EpDo3dDDtGsA46CXNYHFY3aD+B3333idv8y5yvpq?= =?us-ascii?Q?o9bHJWdOQ3DwB8wTR1u/pWX/RUUltkhJTcTs+VCP95Y8cKd6J9NwomU/nIlR?= =?us-ascii?Q?93J0iA06EC5/ncNVuaap4y3MYSoH+0/nZckgvovLH7dkTl25EHLGX44ia2yd?= =?us-ascii?Q?9LsGtHYIgIehnGSFV2kPNXx4b61TTHsHkjNbtCrL19wCeL1WvG8MQWuRUA5g?= =?us-ascii?Q?SihDcoBRPmCCqm85ZHRijNx7cVjYCDZfgt/DB8UCM2i7SSrEZJEjABzfy1tt?= =?us-ascii?Q?rfNNf7tn9gtrV11EKeeg8DdMBhQF/lP/5VKYrqeHhQ2ufiirvknAa9nsjg?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(7416014)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2025 06:00:17.5995 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a2ce25d-07be-4706-7144-08dde5f82a0e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9134 Content-Type: text/plain; charset="utf-8" From: Akhil R Add support for Tegra264 SoC which supports 17 generic I2C controllers, two of which are in the AON (always-on) partition of the SoC. In addition to the features supported by Tegra194 it also supports a SW mutex register to allow sharing the same I2C instance across multiple firmware. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- v1 -> v4: * Update commit message to mention the SW mutex feature available on Tegra264. --- drivers/i2c/busses/i2c-tegra.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 88ee27f90526..971aa1559fa5 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1784,7 +1784,36 @@ static const struct tegra_i2c_hw_feature tegra194_i2= c_hw =3D { .has_mutex =3D false, }; =20 +static const struct tegra_i2c_hw_feature tegra264_i2c_hw =3D { + .has_continue_xfer_support =3D true, + .has_per_pkt_xfer_complete_irq =3D true, + .clk_divisor_hs_mode =3D 1, + .clk_divisor_std_mode =3D 0x1d, + .clk_divisor_fast_mode =3D 0x15, + .clk_divisor_fast_plus_mode =3D 0x8, + .has_config_load_reg =3D true, + .has_multi_master_mode =3D true, + .has_slcg_override_reg =3D true, + .has_mst_fifo =3D true, + .quirks =3D &tegra194_i2c_quirks, + .supports_bus_clear =3D true, + .has_apb_dma =3D false, + .tlow_std_mode =3D 0x8, + .thigh_std_mode =3D 0x7, + .tlow_fast_fastplus_mode =3D 0x2, + .thigh_fast_fastplus_mode =3D 0x2, + .tlow_hs_mode =3D 0x4, + .thigh_hs_mode =3D 0x2, + .setup_hold_time_std_mode =3D 0x08080808, + .setup_hold_time_fast_fast_plus_mode =3D 0x02020202, + .setup_hold_time_hs_mode =3D 0x090909, + .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D true, + .has_mutex =3D true, +}; + static const struct of_device_id tegra_i2c_of_match[] =3D { + { .compatible =3D "nvidia,tegra264-i2c", .data =3D &tegra264_i2c_hw, }, { .compatible =3D "nvidia,tegra194-i2c", .data =3D &tegra194_i2c_hw, }, { .compatible =3D "nvidia,tegra186-i2c", .data =3D &tegra186_i2c_hw, }, #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) --=20 2.43.0