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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe72c35ebdsm927942666b.7.2025.08.27.22.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 22:51:20 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/6] thermal: tegra: add Tegra114 specific SOCTHERM driver Date: Thu, 28 Aug 2025 08:51:03 +0300 Message-ID: <20250828055104.8073-6-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250828055104.8073-1-clamor95@gmail.com> References: <20250828055104.8073-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Tegra114 specific SOCTHERM driver. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/thermal/tegra/Makefile | 1 + drivers/thermal/tegra/soctherm.c | 13 ++ drivers/thermal/tegra/soctherm.h | 4 + drivers/thermal/tegra/tegra114-soctherm.c | 209 ++++++++++++++++++++++ 4 files changed, 227 insertions(+) create mode 100644 drivers/thermal/tegra/tegra114-soctherm.c diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile index eb27d194c583..9b3e91f7fb97 100644 --- a/drivers/thermal/tegra/Makefile +++ b/drivers/thermal/tegra/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_TEGRA_BPMP_THERMAL) +=3D tegra-bpmp-thermal.o obj-$(CONFIG_TEGRA30_TSENSOR) +=3D tegra30-tsensor.o =20 tegra-soctherm-y :=3D soctherm.o soctherm-fuse.o +tegra-soctherm-$(CONFIG_ARCH_TEGRA_114_SOC) +=3D tegra114-soctherm.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) +=3D tegra124-soctherm.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_132_SOC) +=3D tegra132-soctherm.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_210_SOC) +=3D tegra210-soctherm.o diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/socth= erm.c index 926f1052e6de..bd1919f70860 100644 --- a/drivers/thermal/tegra/soctherm.c +++ b/drivers/thermal/tegra/soctherm.c @@ -31,6 +31,7 @@ #include #include =20 +#include #include =20 #include "../thermal_core.h" @@ -357,6 +358,12 @@ struct soctherm_oc_irq_chip_data { =20 static struct soctherm_oc_irq_chip_data soc_irq_cdata; =20 +/* Ensure that TEGRA114_* and TEGRA124_* counterparts are equal */ +static_assert(TEGRA114_SOCTHERM_SENSOR_CPU =3D=3D TEGRA124_SOCTHERM_SENSOR= _CPU); +static_assert(TEGRA114_SOCTHERM_SENSOR_MEM =3D=3D TEGRA124_SOCTHERM_SENSOR= _MEM); +static_assert(TEGRA114_SOCTHERM_SENSOR_GPU =3D=3D TEGRA124_SOCTHERM_SENSOR= _GPU); +static_assert(TEGRA114_SOCTHERM_SENSOR_PLLX =3D=3D TEGRA124_SOCTHERM_SENSO= R_PLLX); + /** * ccroc_writel() - writes a value to a CCROC register * @ts: pointer to a struct tegra_soctherm @@ -2048,6 +2055,12 @@ static void soctherm_init(struct platform_device *pd= ev) } =20 static const struct of_device_id tegra_soctherm_of_match[] =3D { +#ifdef CONFIG_ARCH_TEGRA_114_SOC + { + .compatible =3D "nvidia,tegra114-soctherm", + .data =3D &tegra114_soctherm, + }, +#endif #ifdef CONFIG_ARCH_TEGRA_124_SOC { .compatible =3D "nvidia,tegra124-soctherm", diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/socth= erm.h index 083388094fd4..aa4af9268b05 100644 --- a/drivers/thermal/tegra/soctherm.h +++ b/drivers/thermal/tegra/soctherm.h @@ -142,6 +142,10 @@ int tegra_calc_tsensor_calib(const struct tegra_tsenso= r *sensor, const struct tsensor_shared_calib *shared, u32 *calib); =20 +#ifdef CONFIG_ARCH_TEGRA_114_SOC +extern const struct tegra_soctherm_soc tegra114_soctherm; +#endif + #ifdef CONFIG_ARCH_TEGRA_124_SOC extern const struct tegra_soctherm_soc tegra124_soctherm; #endif diff --git a/drivers/thermal/tegra/tegra114-soctherm.c b/drivers/thermal/te= gra/tegra114-soctherm.c new file mode 100644 index 000000000000..688104f28052 --- /dev/null +++ b/drivers/thermal/tegra/tegra114-soctherm.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2024, Svyatoslav Ryhel + */ + +#include +#include + +#include + +#include "soctherm.h" + +#define TEGRA114_THERMTRIP_ANY_EN_MASK (0x1 << 28) +#define TEGRA114_THERMTRIP_MEM_EN_MASK (0x1 << 27) +#define TEGRA114_THERMTRIP_GPU_EN_MASK (0x1 << 26) +#define TEGRA114_THERMTRIP_CPU_EN_MASK (0x1 << 25) +#define TEGRA114_THERMTRIP_TSENSE_EN_MASK (0x1 << 24) +#define TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16) +#define TEGRA114_THERMTRIP_CPU_THRESH_MASK (0xff << 8) +#define TEGRA114_THERMTRIP_TSENSE_THRESH_MASK 0xff + +#define TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17) +#define TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9) + +#define TEGRA114_THRESH_GRAIN 1000 +#define TEGRA114_BPTT 8 + +static const struct tegra_tsensor_configuration tegra114_tsensor_config = =3D { + .tall =3D 16300, + .tiddq_en =3D 1, + .ten_count =3D 1, + .tsample =3D 163, + .tsample_ate =3D 655, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_cpu =3D { + .id =3D TEGRA114_SOCTHERM_SENSOR_CPU, + .name =3D "cpu", + .sensor_temp_offset =3D SENSOR_TEMP1, + .sensor_temp_mask =3D SENSOR_TEMP1_CPU_TEMP_MASK, + .pdiv =3D 10, + .pdiv_ate =3D 10, + .pdiv_mask =3D SENSOR_PDIV_CPU_MASK, + .pllx_hotspot_diff =3D 6, + .pllx_hotspot_mask =3D SENSOR_HOTSPOT_CPU_MASK, + .thermtrip_any_en_mask =3D TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask =3D TEGRA114_THERMTRIP_CPU_EN_MASK, + .thermtrip_threshold_mask =3D TEGRA114_THERMTRIP_CPU_THRESH_MASK, + .thermctl_isr_mask =3D THERM_IRQ_CPU_MASK, + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_CPU, + .thermctl_lvl0_up_thresh_mask =3D TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask =3D TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_gpu =3D { + .id =3D TEGRA114_SOCTHERM_SENSOR_GPU, + .name =3D "gpu", + .sensor_temp_offset =3D SENSOR_TEMP1, + .sensor_temp_mask =3D SENSOR_TEMP1_GPU_TEMP_MASK, + .pdiv =3D 10, + .pdiv_ate =3D 10, + .pdiv_mask =3D SENSOR_PDIV_GPU_MASK, + .pllx_hotspot_diff =3D 6, + .pllx_hotspot_mask =3D SENSOR_HOTSPOT_GPU_MASK, + .thermtrip_any_en_mask =3D TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask =3D TEGRA114_THERMTRIP_GPU_EN_MASK, + .thermtrip_threshold_mask =3D TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK, + .thermctl_isr_mask =3D THERM_IRQ_GPU_MASK, + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_GPU, + .thermctl_lvl0_up_thresh_mask =3D TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask =3D TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_pll =3D { + .id =3D TEGRA114_SOCTHERM_SENSOR_PLLX, + .name =3D "pll", + .sensor_temp_offset =3D SENSOR_TEMP2, + .sensor_temp_mask =3D SENSOR_TEMP2_PLLX_TEMP_MASK, + .pdiv =3D 10, + .pdiv_ate =3D 10, + .pdiv_mask =3D SENSOR_PDIV_PLLX_MASK, + .thermtrip_any_en_mask =3D TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask =3D TEGRA114_THERMTRIP_TSENSE_EN_MASK, + .thermtrip_threshold_mask =3D TEGRA114_THERMTRIP_TSENSE_THRESH_MASK, + .thermctl_isr_mask =3D THERM_IRQ_TSENSE_MASK, + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_TSENSE, + .thermctl_lvl0_up_thresh_mask =3D TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask =3D TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_mem =3D { + .id =3D TEGRA114_SOCTHERM_SENSOR_MEM, + .name =3D "mem", + .sensor_temp_offset =3D SENSOR_TEMP2, + .sensor_temp_mask =3D SENSOR_TEMP2_MEM_TEMP_MASK, + .pdiv =3D 10, + .pdiv_ate =3D 10, + .pdiv_mask =3D SENSOR_PDIV_MEM_MASK, + .pllx_hotspot_diff =3D 0, + .pllx_hotspot_mask =3D SENSOR_HOTSPOT_MEM_MASK, + .thermtrip_any_en_mask =3D TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask =3D TEGRA114_THERMTRIP_MEM_EN_MASK, + .thermtrip_threshold_mask =3D TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK, + .thermctl_isr_mask =3D THERM_IRQ_MEM_MASK, + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_MEM, + .thermctl_lvl0_up_thresh_mask =3D TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask =3D TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group *tegra114_tsensor_groups[] =3D { + &tegra114_tsensor_group_cpu, + &tegra114_tsensor_group_gpu, + &tegra114_tsensor_group_pll, + &tegra114_tsensor_group_mem, +}; + +static const struct tegra_tsensor tegra114_tsensors[] =3D { + { + .name =3D "cpu0", + .base =3D 0xc0, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x098, + .fuse_corr_alpha =3D 1196400, + .fuse_corr_beta =3D -13600000, + .group =3D &tegra114_tsensor_group_cpu, + }, { + .name =3D "cpu1", + .base =3D 0xe0, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x084, + .fuse_corr_alpha =3D 1196400, + .fuse_corr_beta =3D -13600000, + .group =3D &tegra114_tsensor_group_cpu, + }, { + .name =3D "cpu2", + .base =3D 0x100, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x088, + .fuse_corr_alpha =3D 1196400, + .fuse_corr_beta =3D -13600000, + .group =3D &tegra114_tsensor_group_cpu, + }, { + .name =3D "cpu3", + .base =3D 0x120, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x12c, + .fuse_corr_alpha =3D 1196400, + .fuse_corr_beta =3D -13600000, + .group =3D &tegra114_tsensor_group_cpu, + }, { + .name =3D "mem0", + .base =3D 0x140, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x158, + .fuse_corr_alpha =3D 1000000, + .fuse_corr_beta =3D 0, + .group =3D &tegra114_tsensor_group_mem, + }, { + .name =3D "mem1", + .base =3D 0x160, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x15c, + .fuse_corr_alpha =3D 1000000, + .fuse_corr_beta =3D 0, + .group =3D &tegra114_tsensor_group_mem, + }, { + .name =3D "gpu", + .base =3D 0x180, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x154, + .fuse_corr_alpha =3D 1124500, + .fuse_corr_beta =3D -9793100, + .group =3D &tegra114_tsensor_group_gpu, + }, { + .name =3D "pllx", + .base =3D 0x1a0, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x160, + .fuse_corr_alpha =3D 1224200, + .fuse_corr_beta =3D -14665000, + .group =3D &tegra114_tsensor_group_pll, + }, +}; + +static const struct tegra_soctherm_fuse tegra114_soctherm_fuse =3D { + .fuse_base_cp_mask =3D 0x3ff, + .fuse_base_cp_shift =3D 0, + .fuse_shift_cp_mask =3D 0x3f << 10, + .fuse_shift_cp_shift =3D 10, + .fuse_base_ft_mask =3D 0x7ff << 16, + .fuse_base_ft_shift =3D 16, + .fuse_shift_ft_mask =3D 0x1f << 27, + .fuse_shift_ft_shift =3D 27, + .fuse_common_reg =3D FUSE_VSENSOR_CALIB, + .fuse_spare_realignment =3D 0, + .nominal_calib_ft =3D 90, +}; + +const struct tegra_soctherm_soc tegra114_soctherm =3D { + .tsensors =3D tegra114_tsensors, + .num_tsensors =3D ARRAY_SIZE(tegra114_tsensors), + .ttgs =3D tegra114_tsensor_groups, + .num_ttgs =3D ARRAY_SIZE(tegra114_tsensor_groups), + .tfuse =3D &tegra114_soctherm_fuse, + .thresh_grain =3D TEGRA114_THRESH_GRAIN, + .bptt =3D TEGRA114_BPTT, + .use_ccroc =3D false, +}; --=20 2.48.1