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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe72c35ebdsm927942666b.7.2025.08.27.22.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 22:51:15 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/6] soc: tegra: fuse: add Tegra114 nvmem cells and fuse lookups Date: Thu, 28 Aug 2025 08:50:59 +0300 Message-ID: <20250828055104.8073-2-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250828055104.8073-1-clamor95@gmail.com> References: <20250828055104.8073-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add missing Tegra114 nvmem cells and fuse lookups which were added for Tegra124+ but omitted for Tegra114. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/soc/tegra/fuse/fuse-tegra30.c | 122 ++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse= /fuse-tegra30.c index e24ab5f7d2bf..524fa1b0cd3d 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -117,6 +117,124 @@ const struct tegra_fuse_soc tegra30_fuse_soc =3D { #endif =20 #ifdef CONFIG_ARCH_TEGRA_114_SOC +static const struct nvmem_cell_info tegra114_fuse_cells[] =3D { + { + .name =3D "tsensor-cpu1", + .offset =3D 0x084, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-cpu2", + .offset =3D 0x088, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-common", + .offset =3D 0x08c, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-cpu0", + .offset =3D 0x098, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "xusb-pad-calibration", + .offset =3D 0x0f0, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-cpu3", + .offset =3D 0x12c, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-gpu", + .offset =3D 0x154, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-mem0", + .offset =3D 0x158, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-mem1", + .offset =3D 0x15c, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-pllx", + .offset =3D 0x160, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, +}; + +static const struct nvmem_cell_lookup tegra114_fuse_lookups[] =3D { + { + .nvmem_name =3D "fuse", + .cell_name =3D "xusb-pad-calibration", + .dev_id =3D "7009f000.padctl", + .con_id =3D "calibration", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "tsensor-common", + .dev_id =3D "700e2000.thermal-sensor", + .con_id =3D "common", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "tsensor-cpu0", + .dev_id =3D "700e2000.thermal-sensor", + .con_id =3D "cpu0", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "tsensor-cpu1", + .dev_id =3D "700e2000.thermal-sensor", + .con_id =3D "cpu1", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "tsensor-cpu2", + .dev_id =3D "700e2000.thermal-sensor", + .con_id =3D "cpu2", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "tsensor-cpu3", + .dev_id =3D "700e2000.thermal-sensor", + .con_id =3D "cpu3", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "tsensor-mem0", + .dev_id =3D "700e2000.thermal-sensor", + .con_id =3D "mem0", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "tsensor-mem1", + .dev_id =3D "700e2000.thermal-sensor", + .con_id =3D "mem1", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "tsensor-gpu", + .dev_id =3D "700e2000.thermal-sensor", + .con_id =3D "gpu", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "tsensor-pllx", + .dev_id =3D "700e2000.thermal-sensor", + .con_id =3D "pllx", + }, +}; + static const struct tegra_fuse_info tegra114_fuse_info =3D { .read =3D tegra30_fuse_read, .size =3D 0x2a0, @@ -127,6 +245,10 @@ const struct tegra_fuse_soc tegra114_fuse_soc =3D { .init =3D tegra30_fuse_init, .speedo_init =3D tegra114_init_speedo_data, .info =3D &tegra114_fuse_info, + .lookups =3D tegra114_fuse_lookups, + .num_lookups =3D ARRAY_SIZE(tegra114_fuse_lookups), + .cells =3D tegra114_fuse_cells, + .num_cells =3D ARRAY_SIZE(tegra114_fuse_cells), .soc_attr_group =3D &tegra_soc_attr_group, .clk_suspend_on =3D false, }; --=20 2.48.1 From nobody Fri Oct 3 16:47:17 2025 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0F76272E61; Thu, 28 Aug 2025 05:51:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe72c35ebdsm927942666b.7.2025.08.27.22.51.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 22:51:16 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/6] dt-bindings: thermal: Document Tegra114 SOCTHERM Thermal Management System Date: Thu, 28 Aug 2025 08:51:00 +0300 Message-ID: <20250828055104.8073-3-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250828055104.8073-1-clamor95@gmail.com> References: <20250828055104.8073-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document SOCTHERM Thermal Management System found in the Tegra 4 SoC. Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soct= herm.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-socth= erm.yaml index 19bb1f324183..2fd493fcca63 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.ya= ml +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.ya= ml @@ -18,6 +18,7 @@ description: The SOCTHERM IP block contains thermal senso= rs, support for properties: compatible: enum: + - nvidia,tegra114-soctherm - nvidia,tegra124-soctherm - nvidia,tegra132-soctherm - nvidia,tegra210-soctherm @@ -205,6 +206,7 @@ allOf: compatible: contains: enum: + - nvidia,tegra114-soctherm - nvidia,tegra124-soctherm - nvidia,tegra210-soctherm then: --=20 2.48.1 From nobody Fri Oct 3 16:47:17 2025 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D60B27815D; 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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe72c35ebdsm927942666b.7.2025.08.27.22.51.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 22:51:18 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/6] thermal: tegra: soctherm-fuse: prepare calibration for Tegra114 support Date: Thu, 28 Aug 2025 08:51:01 +0300 Message-ID: <20250828055104.8073-4-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250828055104.8073-1-clamor95@gmail.com> References: <20250828055104.8073-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Tegra114 has a different fuse calibration register layout and address compared to other Tegra SoCs, requiring SOCTHERM shift, mask, register address, and nominal tf calibration value to be configurable. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/thermal/tegra/soctherm-fuse.c | 18 ++++++++++++------ drivers/thermal/tegra/soctherm.h | 7 ++++++- drivers/thermal/tegra/tegra124-soctherm.c | 4 ++++ drivers/thermal/tegra/tegra132-soctherm.c | 4 ++++ drivers/thermal/tegra/tegra210-soctherm.c | 4 ++++ 5 files changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/tegra/soctherm-fuse.c b/drivers/thermal/tegra/= soctherm-fuse.c index 190f95280e0b..8d37cd8c9122 100644 --- a/drivers/thermal/tegra/soctherm-fuse.c +++ b/drivers/thermal/tegra/soctherm-fuse.c @@ -9,15 +9,12 @@ =20 #include "soctherm.h" =20 -#define NOMINAL_CALIB_FT 105 #define NOMINAL_CALIB_CP 25 =20 #define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff #define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13) #define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13 =20 -#define FUSE_TSENSOR_COMMON 0x180 - /* * Tegra210: Layout of bits in FUSE_TSENSOR_COMMON: * 3 2 1 0 @@ -26,7 +23,7 @@ * | BASE_FT | BASE_CP | SHFT_FT | SHIFT_CP | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * - * Tegra12x, etc: + * Tegra124: * In chips prior to Tegra210, this fuse was incorrectly sized as 26 bits, * and didn't hold SHIFT_CP in [31:26]. Therefore these missing six bits * were obtained via the FUSE_SPARE_REALIGNMENT_REG register [5:0]. @@ -44,6 +41,13 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * |---------------------------------------------------| SHIFT_CP | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * + * Tegra114: Layout of bits in FUSE_TSENSOR_COMMON aka FUSE_VSENSOR_CALIB: + * 3 2 1 0 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | SHFT_FT | BASE_FT | SHIFT_CP | BASE_CP | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ =20 #define CALIB_COEFFICIENT 1000000LL @@ -77,7 +81,7 @@ int tegra_calc_shared_calib(const struct tegra_soctherm_f= use *tfuse, s32 shifted_cp, shifted_ft; int err; =20 - err =3D tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val); + err =3D tegra_fuse_readl(tfuse->fuse_common_reg, &val); if (err) return err; =20 @@ -96,10 +100,12 @@ int tegra_calc_shared_calib(const struct tegra_socther= m_fuse *tfuse, return err; } =20 + shifted_cp =3D (val & tfuse->fuse_shift_cp_mask) >> + tfuse->fuse_shift_cp_shift; shifted_cp =3D sign_extend32(val, 5); =20 shared->actual_temp_cp =3D 2 * NOMINAL_CALIB_CP + shifted_cp; - shared->actual_temp_ft =3D 2 * NOMINAL_CALIB_FT + shifted_ft; + shared->actual_temp_ft =3D 2 * tfuse->nominal_calib_ft + shifted_ft; =20 return 0; } diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/socth= erm.h index 70501e73d586..083388094fd4 100644 --- a/drivers/thermal/tegra/soctherm.h +++ b/drivers/thermal/tegra/soctherm.h @@ -56,6 +56,9 @@ #define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16) #define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff =20 +#define FUSE_VSENSOR_CALIB 0x08c +#define FUSE_TSENSOR_COMMON 0x180 + /** * struct tegra_tsensor_group - SOC_THERM sensor group data * @name: short name of the temperature sensor group @@ -109,9 +112,11 @@ struct tsensor_group_thermtrips { =20 struct tegra_soctherm_fuse { u32 fuse_base_cp_mask, fuse_base_cp_shift; + u32 fuse_shift_cp_mask, fuse_shift_cp_shift; u32 fuse_base_ft_mask, fuse_base_ft_shift; u32 fuse_shift_ft_mask, fuse_shift_ft_shift; - u32 fuse_spare_realignment; + u32 fuse_common_reg, fuse_spare_realignment; + u32 nominal_calib_ft; }; =20 struct tsensor_shared_calib { diff --git a/drivers/thermal/tegra/tegra124-soctherm.c b/drivers/thermal/te= gra/tegra124-soctherm.c index 20ad27f4d1a1..d86acff1b234 100644 --- a/drivers/thermal/tegra/tegra124-soctherm.c +++ b/drivers/thermal/tegra/tegra124-soctherm.c @@ -200,11 +200,15 @@ static const struct tegra_tsensor tegra124_tsensors[]= =3D { static const struct tegra_soctherm_fuse tegra124_soctherm_fuse =3D { .fuse_base_cp_mask =3D 0x3ff, .fuse_base_cp_shift =3D 0, + .fuse_shift_cp_mask =3D 0x3f, + .fuse_shift_cp_shift =3D 0, .fuse_base_ft_mask =3D 0x7ff << 10, .fuse_base_ft_shift =3D 10, .fuse_shift_ft_mask =3D 0x1f << 21, .fuse_shift_ft_shift =3D 21, + .fuse_common_reg =3D FUSE_TSENSOR_COMMON, .fuse_spare_realignment =3D 0x1fc, + .nominal_calib_ft =3D 105, }; =20 const struct tegra_soctherm_soc tegra124_soctherm =3D { diff --git a/drivers/thermal/tegra/tegra132-soctherm.c b/drivers/thermal/te= gra/tegra132-soctherm.c index b76308fdad9e..64c0363b9717 100644 --- a/drivers/thermal/tegra/tegra132-soctherm.c +++ b/drivers/thermal/tegra/tegra132-soctherm.c @@ -200,11 +200,15 @@ static struct tegra_tsensor tegra132_tsensors[] =3D { static const struct tegra_soctherm_fuse tegra132_soctherm_fuse =3D { .fuse_base_cp_mask =3D 0x3ff, .fuse_base_cp_shift =3D 0, + .fuse_shift_cp_mask =3D 0x3f, + .fuse_shift_cp_shift =3D 0, .fuse_base_ft_mask =3D 0x7ff << 10, .fuse_base_ft_shift =3D 10, .fuse_shift_ft_mask =3D 0x1f << 21, .fuse_shift_ft_shift =3D 21, + .fuse_common_reg =3D FUSE_TSENSOR_COMMON, .fuse_spare_realignment =3D 0x1fc, + .nominal_calib_ft =3D 105, }; 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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe72c35ebdsm927942666b.7.2025.08.27.22.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 22:51:19 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/6] dt-bindings: thermal: add Tegra114 soctherm header Date: Thu, 28 Aug 2025 08:51:02 +0300 Message-ID: <20250828055104.8073-5-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250828055104.8073-1-clamor95@gmail.com> References: <20250828055104.8073-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds header for the Tegra114 SOCTHERM device tree node. Signed-off-by: Svyatoslav Ryhel Acked-by: Conor Dooley Reviewed-by: Mikko Perttunen --- .../dt-bindings/thermal/tegra114-soctherm.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/thermal/tegra114-soctherm.h diff --git a/include/dt-bindings/thermal/tegra114-soctherm.h b/include/dt-b= indings/thermal/tegra114-soctherm.h new file mode 100644 index 000000000000..b766a61cd1ce --- /dev/null +++ b/include/dt-bindings/thermal/tegra114-soctherm.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for binding nvidia,tegra114-soctherm. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA114_SOCTHERM_H +#define _DT_BINDINGS_THERMAL_TEGRA114_SOCTHERM_H + +#define TEGRA114_SOCTHERM_SENSOR_CPU 0 +#define TEGRA114_SOCTHERM_SENSOR_MEM 1 +#define TEGRA114_SOCTHERM_SENSOR_GPU 2 +#define TEGRA114_SOCTHERM_SENSOR_PLLX 3 + +#define TEGRA114_SOCTHERM_THROT_LEVEL_NONE 0 +#define TEGRA114_SOCTHERM_THROT_LEVEL_LOW 1 +#define TEGRA114_SOCTHERM_THROT_LEVEL_MED 2 +#define TEGRA114_SOCTHERM_THROT_LEVEL_HIGH 3 + +#endif --=20 2.48.1 From nobody Fri Oct 3 16:47:17 2025 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C68E027CCC4; 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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe72c35ebdsm927942666b.7.2025.08.27.22.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 22:51:20 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/6] thermal: tegra: add Tegra114 specific SOCTHERM driver Date: Thu, 28 Aug 2025 08:51:03 +0300 Message-ID: <20250828055104.8073-6-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250828055104.8073-1-clamor95@gmail.com> References: <20250828055104.8073-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Tegra114 specific SOCTHERM driver. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/thermal/tegra/Makefile | 1 + drivers/thermal/tegra/soctherm.c | 13 ++ drivers/thermal/tegra/soctherm.h | 4 + drivers/thermal/tegra/tegra114-soctherm.c | 209 ++++++++++++++++++++++ 4 files changed, 227 insertions(+) create mode 100644 drivers/thermal/tegra/tegra114-soctherm.c diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile index eb27d194c583..9b3e91f7fb97 100644 --- a/drivers/thermal/tegra/Makefile +++ b/drivers/thermal/tegra/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_TEGRA_BPMP_THERMAL) +=3D tegra-bpmp-thermal.o obj-$(CONFIG_TEGRA30_TSENSOR) +=3D tegra30-tsensor.o =20 tegra-soctherm-y :=3D soctherm.o soctherm-fuse.o +tegra-soctherm-$(CONFIG_ARCH_TEGRA_114_SOC) +=3D tegra114-soctherm.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) +=3D tegra124-soctherm.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_132_SOC) +=3D tegra132-soctherm.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_210_SOC) +=3D tegra210-soctherm.o diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/socth= erm.c index 926f1052e6de..bd1919f70860 100644 --- a/drivers/thermal/tegra/soctherm.c +++ b/drivers/thermal/tegra/soctherm.c @@ -31,6 +31,7 @@ #include #include =20 +#include #include =20 #include "../thermal_core.h" @@ -357,6 +358,12 @@ struct soctherm_oc_irq_chip_data { =20 static struct soctherm_oc_irq_chip_data soc_irq_cdata; =20 +/* Ensure that TEGRA114_* and TEGRA124_* counterparts are equal */ +static_assert(TEGRA114_SOCTHERM_SENSOR_CPU =3D=3D TEGRA124_SOCTHERM_SENSOR= _CPU); +static_assert(TEGRA114_SOCTHERM_SENSOR_MEM =3D=3D TEGRA124_SOCTHERM_SENSOR= _MEM); +static_assert(TEGRA114_SOCTHERM_SENSOR_GPU =3D=3D TEGRA124_SOCTHERM_SENSOR= _GPU); +static_assert(TEGRA114_SOCTHERM_SENSOR_PLLX =3D=3D TEGRA124_SOCTHERM_SENSO= R_PLLX); + /** * ccroc_writel() - writes a value to a CCROC register * @ts: pointer to a struct tegra_soctherm @@ -2048,6 +2055,12 @@ static void soctherm_init(struct platform_device *pd= ev) } =20 static const struct of_device_id tegra_soctherm_of_match[] =3D { +#ifdef CONFIG_ARCH_TEGRA_114_SOC + { + .compatible =3D "nvidia,tegra114-soctherm", + .data =3D &tegra114_soctherm, + }, +#endif #ifdef CONFIG_ARCH_TEGRA_124_SOC { .compatible =3D "nvidia,tegra124-soctherm", diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/socth= erm.h index 083388094fd4..aa4af9268b05 100644 --- a/drivers/thermal/tegra/soctherm.h +++ b/drivers/thermal/tegra/soctherm.h @@ -142,6 +142,10 @@ int tegra_calc_tsensor_calib(const struct tegra_tsenso= r *sensor, const struct tsensor_shared_calib *shared, u32 *calib); =20 +#ifdef CONFIG_ARCH_TEGRA_114_SOC +extern const struct tegra_soctherm_soc tegra114_soctherm; +#endif + #ifdef CONFIG_ARCH_TEGRA_124_SOC extern const struct tegra_soctherm_soc tegra124_soctherm; #endif diff --git a/drivers/thermal/tegra/tegra114-soctherm.c b/drivers/thermal/te= gra/tegra114-soctherm.c new file mode 100644 index 000000000000..688104f28052 --- /dev/null +++ b/drivers/thermal/tegra/tegra114-soctherm.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2024, Svyatoslav Ryhel + */ + +#include +#include + +#include + +#include "soctherm.h" + +#define TEGRA114_THERMTRIP_ANY_EN_MASK (0x1 << 28) +#define TEGRA114_THERMTRIP_MEM_EN_MASK (0x1 << 27) +#define TEGRA114_THERMTRIP_GPU_EN_MASK (0x1 << 26) +#define TEGRA114_THERMTRIP_CPU_EN_MASK (0x1 << 25) +#define TEGRA114_THERMTRIP_TSENSE_EN_MASK (0x1 << 24) +#define TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16) +#define TEGRA114_THERMTRIP_CPU_THRESH_MASK (0xff << 8) +#define TEGRA114_THERMTRIP_TSENSE_THRESH_MASK 0xff + +#define TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17) +#define TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9) + +#define TEGRA114_THRESH_GRAIN 1000 +#define TEGRA114_BPTT 8 + +static const struct tegra_tsensor_configuration tegra114_tsensor_config = =3D { + .tall =3D 16300, + .tiddq_en =3D 1, + .ten_count =3D 1, + .tsample =3D 163, + .tsample_ate =3D 655, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_cpu =3D { + .id =3D TEGRA114_SOCTHERM_SENSOR_CPU, + .name =3D "cpu", + .sensor_temp_offset =3D SENSOR_TEMP1, + .sensor_temp_mask =3D SENSOR_TEMP1_CPU_TEMP_MASK, + .pdiv =3D 10, + .pdiv_ate =3D 10, + .pdiv_mask =3D SENSOR_PDIV_CPU_MASK, + .pllx_hotspot_diff =3D 6, + .pllx_hotspot_mask =3D SENSOR_HOTSPOT_CPU_MASK, + .thermtrip_any_en_mask =3D TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask =3D TEGRA114_THERMTRIP_CPU_EN_MASK, + .thermtrip_threshold_mask =3D TEGRA114_THERMTRIP_CPU_THRESH_MASK, + .thermctl_isr_mask =3D THERM_IRQ_CPU_MASK, + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_CPU, + .thermctl_lvl0_up_thresh_mask =3D TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask =3D TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_gpu =3D { + .id =3D TEGRA114_SOCTHERM_SENSOR_GPU, + .name =3D "gpu", + .sensor_temp_offset =3D SENSOR_TEMP1, + .sensor_temp_mask =3D SENSOR_TEMP1_GPU_TEMP_MASK, + .pdiv =3D 10, + .pdiv_ate =3D 10, + .pdiv_mask =3D SENSOR_PDIV_GPU_MASK, + .pllx_hotspot_diff =3D 6, + .pllx_hotspot_mask =3D SENSOR_HOTSPOT_GPU_MASK, + .thermtrip_any_en_mask =3D TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask =3D TEGRA114_THERMTRIP_GPU_EN_MASK, + .thermtrip_threshold_mask =3D TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK, + .thermctl_isr_mask =3D THERM_IRQ_GPU_MASK, + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_GPU, + .thermctl_lvl0_up_thresh_mask =3D TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask =3D TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_pll =3D { + .id =3D TEGRA114_SOCTHERM_SENSOR_PLLX, + .name =3D "pll", + .sensor_temp_offset =3D SENSOR_TEMP2, + .sensor_temp_mask =3D SENSOR_TEMP2_PLLX_TEMP_MASK, + .pdiv =3D 10, + .pdiv_ate =3D 10, + .pdiv_mask =3D SENSOR_PDIV_PLLX_MASK, + .thermtrip_any_en_mask =3D TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask =3D TEGRA114_THERMTRIP_TSENSE_EN_MASK, + .thermtrip_threshold_mask =3D TEGRA114_THERMTRIP_TSENSE_THRESH_MASK, + .thermctl_isr_mask =3D THERM_IRQ_TSENSE_MASK, + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_TSENSE, + .thermctl_lvl0_up_thresh_mask =3D TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask =3D TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_mem =3D { + .id =3D TEGRA114_SOCTHERM_SENSOR_MEM, + .name =3D "mem", + .sensor_temp_offset =3D SENSOR_TEMP2, + .sensor_temp_mask =3D SENSOR_TEMP2_MEM_TEMP_MASK, + .pdiv =3D 10, + .pdiv_ate =3D 10, + .pdiv_mask =3D SENSOR_PDIV_MEM_MASK, + .pllx_hotspot_diff =3D 0, + .pllx_hotspot_mask =3D SENSOR_HOTSPOT_MEM_MASK, + .thermtrip_any_en_mask =3D TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask =3D TEGRA114_THERMTRIP_MEM_EN_MASK, + .thermtrip_threshold_mask =3D TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK, + .thermctl_isr_mask =3D THERM_IRQ_MEM_MASK, + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_MEM, + .thermctl_lvl0_up_thresh_mask =3D TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask =3D TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group *tegra114_tsensor_groups[] =3D { + &tegra114_tsensor_group_cpu, + &tegra114_tsensor_group_gpu, + &tegra114_tsensor_group_pll, + &tegra114_tsensor_group_mem, +}; + +static const struct tegra_tsensor tegra114_tsensors[] =3D { + { + .name =3D "cpu0", + .base =3D 0xc0, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x098, + .fuse_corr_alpha =3D 1196400, + .fuse_corr_beta =3D -13600000, + .group =3D &tegra114_tsensor_group_cpu, + }, { + .name =3D "cpu1", + .base =3D 0xe0, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x084, + .fuse_corr_alpha =3D 1196400, + .fuse_corr_beta =3D -13600000, + .group =3D &tegra114_tsensor_group_cpu, + }, { + .name =3D "cpu2", + .base =3D 0x100, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x088, + .fuse_corr_alpha =3D 1196400, + .fuse_corr_beta =3D -13600000, + .group =3D &tegra114_tsensor_group_cpu, + }, { + .name =3D "cpu3", + .base =3D 0x120, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x12c, + .fuse_corr_alpha =3D 1196400, + .fuse_corr_beta =3D -13600000, + .group =3D &tegra114_tsensor_group_cpu, + }, { + .name =3D "mem0", + .base =3D 0x140, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x158, + .fuse_corr_alpha =3D 1000000, + .fuse_corr_beta =3D 0, + .group =3D &tegra114_tsensor_group_mem, + }, { + .name =3D "mem1", + .base =3D 0x160, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x15c, + .fuse_corr_alpha =3D 1000000, + .fuse_corr_beta =3D 0, + .group =3D &tegra114_tsensor_group_mem, + }, { + .name =3D "gpu", + .base =3D 0x180, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x154, + .fuse_corr_alpha =3D 1124500, + .fuse_corr_beta =3D -9793100, + .group =3D &tegra114_tsensor_group_gpu, + }, { + .name =3D "pllx", + .base =3D 0x1a0, + .config =3D &tegra114_tsensor_config, + .calib_fuse_offset =3D 0x160, + .fuse_corr_alpha =3D 1224200, + .fuse_corr_beta =3D -14665000, + .group =3D &tegra114_tsensor_group_pll, + }, +}; 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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe72c35ebdsm927942666b.7.2025.08.27.22.51.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 22:51:21 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 6/6] ARM: tegra: Add SOCTHERM support on Tegra114 Date: Thu, 28 Aug 2025 08:51:04 +0300 Message-ID: <20250828055104.8073-7-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250828055104.8073-1-clamor95@gmail.com> References: <20250828055104.8073-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SOCTHERM and thermal zones nodes into common Tegra 4 device tree. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 197 +++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index c429478eb122..c3f540b29c69 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include =20 / { compatible =3D "nvidia,tegra114"; @@ -694,6 +695,46 @@ mipi: mipi@700e3000 { #nvidia,mipi-calibrate-cells =3D <1>; }; =20 + soctherm: thermal-sensor@700e2000 { + compatible =3D "nvidia,tegra114-soctherm"; + reg =3D <0x700e2000 0x600>, /* SOC_THERM reg_base */ + <0x60006000 0x400>; /* CAR reg_base */ + reg-names =3D "soctherm-reg", "car-reg"; + interrupts =3D , + ; + interrupt-names =3D "thermal", "edp"; + clocks =3D <&tegra_car TEGRA114_CLK_TSENSOR>, + <&tegra_car TEGRA114_CLK_SOC_THERM>; + clock-names =3D "tsensor", "soctherm"; + resets =3D <&tegra_car 78>; + reset-names =3D "soctherm"; + + assigned-clocks =3D <&tegra_car TEGRA114_CLK_TSENSOR>, + <&tegra_car TEGRA114_CLK_SOC_THERM>; + assigned-clock-rates =3D <500000>, <51000000>; + + assigned-clock-parents =3D <&tegra_car TEGRA114_CLK_CLK_M>, + <&tegra_car TEGRA114_CLK_PLL_P>; + + #thermal-sensor-cells =3D <1>; + + throttle-cfgs { + throttle_heavy: heavy { + nvidia,priority =3D <100>; + nvidia,cpu-throt-percent =3D <80>; + nvidia,gpu-throt-level =3D ; + #cooling-cells =3D <2>; + }; + + throttle_light: light { + nvidia,priority =3D <80>; + nvidia,cpu-throt-percent =3D <50>; + nvidia,gpu-throt-level =3D ; + #cooling-cells =3D <2>; + }; + }; + }; + dfll: clock@70110000 { compatible =3D "nvidia,tegra114-dfll"; reg =3D <0x70110000 0x100>, /* DFLL control */ @@ -857,24 +898,28 @@ cpu0: cpu@0 { clock-names =3D "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; /* FIXME: what's the actual transition time? */ clock-latency =3D <300000>; + #cooling-cells =3D <2>; }; =20 cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <1>; + #cooling-cells =3D <2>; }; =20 cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <2>; + #cooling-cells =3D <2>; }; =20 cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <3>; + #cooling-cells =3D <2>; }; }; =20 @@ -887,6 +932,158 @@ pmu { interrupt-affinity =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; =20 + thermal-zones { + cpu-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D + <&soctherm TEGRA114_SOCTHERM_SENSOR_CPU>; + + trips { + cpu-shutdown-trip { + temperature =3D <102000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + + cpu_throttle_trip: cpu-throttle-trip { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + cpu_balanced_trip: cpu-balanced-trip { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_throttle_trip>; + cooling-device =3D <&throttle_heavy 1 1>; + }; + + map1 { + trip =3D <&cpu_balanced_trip>; + cooling-device =3D <&throttle_light 1 1>; + }; + }; + }; + + mem-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D + <&soctherm TEGRA114_SOCTHERM_SENSOR_MEM>; + + trips { + mem-shutdown-trip { + temperature =3D <102000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + + mem_throttle_trip: mem-throttle-trip { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + mem_balanced_trip: mem-balanced-trip { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + + gpu-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D + <&soctherm TEGRA114_SOCTHERM_SENSOR_GPU>; + + trips { + gpu-shutdown-trip { + temperature =3D <102000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + + gpu_throttle_trip: gpu-throttle-trip { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + gpu_balanced_trip: gpu-balanced-trip { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&gpu_throttle_trip>; + cooling-device =3D <&throttle_heavy 1 1>; + }; + + map1 { + trip =3D <&gpu_balanced_trip>; + cooling-device =3D <&throttle_light 1 1>; + }; + }; + }; + + pllx-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D + <&soctherm TEGRA114_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx-shutdown-trip { + temperature =3D <102000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + + pllx_throttle_trip: pllx-throttle-trip { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + pllx_balanced_trip: pllx-balanced-trip { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + }; + timer { compatible =3D "arm,armv7-timer"; interrupts =3D --=20 2.48.1