From nobody Fri Oct 3 15:34:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 153D4270568; Thu, 28 Aug 2025 19:23:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756409020; cv=none; b=sNCuuOz4zvJg5zEzmt9s4DkVerATx2pwQ7GBk6HptkR69unznp1GJAZIeY5jL29C9Q60KPcL+MIGGkD8MZiDApNUNv54cbp8Qt/uU3K5j59BQCwCFEA2nqdkpByD2aE5SELBK9WovGeDDNb32QuuKzLKRzYWynBfFLOfQuU220c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756409020; c=relaxed/simple; bh=JWHLtek4k5suu8EbBErIvruvR2tJvUjGe6+Sr41q1Jg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k7taG++upWbkS6c4pdAh6R6SRJIj8Jjz7M9JUqGmBmYwG7tYqCetG3Re8/1jyzfky0ujX4Hp+SQ3TmhjxAifk4lcGqIDMvw3faMrxzEm8uNerk7XEfabonhrqwfrgbXu9S/TP5LMRXdXnkJsRkzFzxGP5pXfE/CpzmiyDw/pr1Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jnaEuTPD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jnaEuTPD" Received: by smtp.kernel.org (Postfix) with ESMTPS id A78C8C4CEEB; Thu, 28 Aug 2025 19:23:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756409019; bh=JWHLtek4k5suu8EbBErIvruvR2tJvUjGe6+Sr41q1Jg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=jnaEuTPDvJFOR/jQVUVNO5uaXEBEVO9nxIpqrIjQmMliafwth1wOQlNe/NXJTw6Mp eEGz/bTmM69CK4dmK3CBhggTlOfkzBljYyNvyS6GX7P6h1nsRqlYae/Q1BmDnY/X6H aze1yRg9jDcpoJopTooPTbkfdSn1rpR9KdiVy/AhgaLzew497f5aviw4A5Nduppe6S IKBsdMWRehkqmNBMyO5sraWpfkI/yI74RYMJN8AR0P18Aov972WCb8oS46ThFYwYi1 NjpWnGCwjZhVuQnuG+VwSb4EKHbs1yATBa2IhD23cCtQ3wDdwBp2OCAEotiFjuNUV2 CbfWcp1vxFpkA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B2BAC8303F; Thu, 28 Aug 2025 19:23:39 +0000 (UTC) From: Nickolay Goppen via B4 Relay Date: Thu, 28 Aug 2025 22:23:37 +0300 Subject: [PATCH v4 1/3] pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-sdm660-lpass-lpi-v4-1-af4afdd52965@yandex.ru> References: <20250828-sdm660-lpass-lpi-v4-0-af4afdd52965@yandex.ru> In-Reply-To: <20250828-sdm660-lpass-lpi-v4-0-af4afdd52965@yandex.ru> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nickolay Goppen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756409018; l=3248; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=/WK82cuSvBmdPjcww2s89K1u5jRqfdDhfVpHCgd9t3w=; b=X86tC9inPJB0w/b4uE2S/GXLPgZCHrnJoVI5Gor/3oBMtUSHDr1dyyn+FygtxFPxbrwHhwEU8 5v7EN7v0ij/BPPsiJJHMlheGmQeAZz7aLeTiuypCirIPQzeqQJXriwZ X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= X-Endpoint-Received: by B4 Relay for setotau@yandex.ru/20250815 with auth_id=492 X-Original-From: Nickolay Goppen Reply-To: setotau@yandex.ru From: Nickolay Goppen By default pin_offset is calculated by formula: LPI_TLMM_REG_OFFSET * pin_i= d. However not all platforms are using this pin_offset formula (e.g. SDM660 LP= ASS LPI uses a predefined array of offsets [1]), so extend lpi_pingroup struct with pin_offset field, introduce extended LPI_PINGROUP_OFFSET macro with pin_offet field and introduce LPI_FLAG_USE_PREDEFINED_PIN_OFFSET flag. This adds an ability to use predefined offset for pin if it exists. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-0= 7400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Signed-off-by: Nickolay Goppen --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 18 ++++++++++++++++-- drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 18 ++++++++++++++++++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 57fefeb603f0e2502fccd14ba3982ae3cb591978..9e841fed87162551bf7165ca483= 8a1e530e02724 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -41,13 +41,27 @@ struct lpi_pinctrl { static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) { - return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + u32 pin_offset; + + if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) + pin_offset =3D state->data->groups[pin].pin_offset; + else + pin_offset =3D LPI_TLMM_REG_OFFSET * pin; + + return ioread32(state->tlmm_base + pin_offset + addr); } =20 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { - iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + u32 pin_offset; + + if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) + pin_offset =3D state->data->groups[pin].pin_offset; + else + pin_offset =3D LPI_TLMM_REG_OFFSET * pin; + + iowrite32(val, state->tlmm_base + pin_offset + addr); =20 return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.h index a9b2f65c1ebe0f8fb5d7814f8ef8b723c617c85b..f48368492861348519ea19b5291= ac7df13050eef 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -55,6 +55,22 @@ struct pinctrl_pin_desc; LPI_MUX_##f4, \ }, \ .nfuncs =3D 5, \ + .pin_offset =3D 0, \ + } + +#define LPI_PINGROUP_OFFSET(id, soff, f1, f2, f3, f4, poff) \ + { \ + .pin =3D id, \ + .slew_offset =3D soff, \ + .funcs =3D (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs =3D 5, \ + .pin_offset =3D poff, \ } =20 /* @@ -62,6 +78,7 @@ struct pinctrl_pin_desc; * pin configuration. */ #define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0) +#define LPI_FLAG_USE_PREDEFINED_PIN_OFFSET BIT(1) =20 struct lpi_pingroup { unsigned int pin; @@ -69,6 +86,7 @@ struct lpi_pingroup { int slew_offset; unsigned int *funcs; unsigned int nfuncs; + unsigned int pin_offset; }; =20 struct lpi_function { --=20 2.51.0 From nobody Fri Oct 3 15:34:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1530E26FA52; Thu, 28 Aug 2025 19:23:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756409020; cv=none; b=BbzmwW5rmNEUar9b4brUc4uRTgKQDwc/bpkERCDM0GKrp2ynqUymyprd3VGk7nUHH2P6brvLctwShBvisM9emb/pkLSzSoZ/p4OryPgbNUTwrkNeLg6cqRblVAogHodL74Bq8qF7Imen8k72BeFRdob6IGNiJU6BeoajVL8heTg= ARC-Message-Signature: i=1; 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b=AxdBJmzNuINyvD4nUUo4jTWsb7DfKwqZxp3Abbc54XDRbrrBG+9JkTpBPn/O1i2b9 LijnrYlPSHabxR4pzzdaXl2yivwm1ny1INkZA5s7SIXEzVd8Ppxh3+XnAyN+TVpUVT D61zREVJEzeS3mycfw+u+8JI7Aq/UtQbExTD5xiKkliVIWZOwVKXwKP857TT7JFy+H rA1aJVVFL9wLs3UrSfasSQ27xllL8svphX1CAiHM06J+R9+bgW7gqwQ6y3kZzYlm+D C2MvxP01Izqd0BU+yiWOM6UXmPjxc7qaF/me2PmvRuClsHEH0xs0CZZZs61rsBuAaV z873EdXW4lkcA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A81FCCA0FF9; Thu, 28 Aug 2025 19:23:39 +0000 (UTC) From: Nickolay Goppen via B4 Relay Date: Thu, 28 Aug 2025 22:23:38 +0300 Subject: [PATCH v4 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-sdm660-lpass-lpi-v4-2-af4afdd52965@yandex.ru> References: <20250828-sdm660-lpass-lpi-v4-0-af4afdd52965@yandex.ru> In-Reply-To: <20250828-sdm660-lpass-lpi-v4-0-af4afdd52965@yandex.ru> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nickolay Goppen , Richard Acayan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756409018; l=2869; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=vFIjBIiT0xa6pAPf/4umxL0RLwDzLrxG2P7MmgFf9vQ=; b=pE6hgqz5HjgMc3QqoNAmcGwhLiDp7PQAoCD+EMIpH11DtRc5z/b6b6CLnxPqPH3YSkMLnWg1+ 270w+qjFHq+ATrxr7prPGPKk2+37Wx4VVFwv+ozNPndUqBMnux4/mhp X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= X-Endpoint-Received: by B4 Relay for setotau@yandex.ru/20250815 with auth_id=492 X-Original-From: Nickolay Goppen Reply-To: setotau@yandex.ru From: Nickolay Goppen Add bindings for pin controller in SDM660 Low Power Audio SubSystem LPASS). Co-developed-by: Richard Acayan Signed-off-by: Richard Acayan Signed-off-by: Nickolay Goppen --- .../pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml | 74 ++++++++++++++++++= ++++ 1 file changed, 74 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lp= i-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpas= s-lpi-pinctrl.yaml new file mode 100644 index 0000000000000000000000000000000000000000..f71dbea9f75b398c9c5dd585635= c469e1f426b6f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinct= rl.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM660 SoC LPASS LPI TLMM + +maintainers: + - Nickolay Goppen + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSyst= em + (LPASS) Low Power Island (LPI) of Qualcomm SDM660 SoC. + +properties: + compatible: + const: qcom,sdm660-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm660-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm660-lpass-state" + additionalProperties: false + +$defs: + qcom-sdm660-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-2][0-9]|3[0-1])$" + + function: + enum: [ gpio, comp_rx, dmic12, dmic34, mclk0, pdm_2_gpios, + pdm_clk, pdm_rx, pdm_sync ] + description: + Specify the alternative function to be configured for the specif= ied + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + lpi_tlmm: pinctrl@15070000 { + compatible =3D "qcom,sdm660-lpass-lpi-pinctrl"; + reg =3D <0x15070000 0x20000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpi_tlmm 0 0 32>; + }; --=20 2.51.0 From nobody Fri Oct 3 15:34:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15444270EBC; Thu, 28 Aug 2025 19:23:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756409020; cv=none; b=kqHu8UwBfjMVUIob6RQopSsRiKoZ5+1mmpNvLeI0muX7+DAHejOi/kneCPQYRrFbt2+g8e81+6tG+hdmnMW0ZH/UOgikAQnfYZ774zzDX2KV5nDA4lfWVIw9JRXklR1/+QYTXhEgbDonIY9Oj/zB0dEpf5GLGvFrJNL8oIvcTAI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756409020; c=relaxed/simple; bh=KT3ThlL77vylRlL0LdnhraifmjDYP6lox3AggI8ipEk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Thu, 28 Aug 2025 19:23:39 +0000 (UTC) From: Nickolay Goppen via B4 Relay Date: Thu, 28 Aug 2025 22:23:39 +0300 Subject: [PATCH v4 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-sdm660-lpass-lpi-v4-3-af4afdd52965@yandex.ru> References: <20250828-sdm660-lpass-lpi-v4-0-af4afdd52965@yandex.ru> In-Reply-To: <20250828-sdm660-lpass-lpi-v4-0-af4afdd52965@yandex.ru> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nickolay Goppen , Richard Acayan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756409018; l=8801; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=FAksBGnsZ8kDvC0bR8KQg80odraUiy0qtIYjCppkfNo=; b=H6FQVCwkTKEnaqCp8ClKVwTY50I120DOqK9XGjbXJpf2kN+GQv2hCdK5t+KPkOXr2182GzwJy LYnUEQUB67iBa+NJGR/dwvIrNTA4pE2eLRiFGR/x6UipX8V2jDcnouC X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= X-Endpoint-Received: by B4 Relay for setotau@yandex.ru/20250815 with auth_id=492 X-Original-From: Nickolay Goppen Reply-To: setotau@yandex.ru From: Richard Acayan The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring pins related to audio. Add the driver for this. Also, this driver uses predefined pin_offsets for each pin taken from downstream driver, which does not follow the usual 0x1000 distance between pins and uses an array with predefined offsets that do not follow any regular pattern [1]. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-0= 7400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Signed-off-by: Richard Acayan Co-developed-by: Nickolay Goppen Signed-off-by: Nickolay Goppen --- drivers/pinctrl/qcom/Kconfig | 10 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 155 ++++++++++++++++++++= ++++ 3 files changed, 166 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index dd9bbe8f3e11c37418d2143b33c21eeea10d456b..ef42520115f461302098d878cb7= 6c6f25e55b5e4 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,16 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platfo= rm. =20 +config PINCTRL_SDM660_LPASS_LPI + tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller drive= r" + depends on GPIOLIB + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platfo= rm. + config PINCTRL_SM4250_LPASS_LPI tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller drive= r" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 954f5291cc37242baffc021e3c68d850aabd57cd..cea8617ac650ecfc75c2a0c745a= 53d6a1b829842 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) +=3D pinctrl-sc728= 0-lpass-lpi.o obj-$(CONFIG_PINCTRL_SC8180X) +=3D pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SC8280XP) +=3D pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) +=3D pinctrl-sdm660.o +obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) +=3D pinctrl-sdm660-lpass-lpi.o obj-$(CONFIG_PINCTRL_SDM670) +=3D pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_SDM845) +=3D pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) +=3D pinctrl-sdx55.o diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sdm660-lpass-lpi.c new file mode 100644 index 0000000000000000000000000000000000000000..7e7e2202c6da75f4ccc60cecc4a= 47655f5aa5de1 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * This driver is solely based on the limited information in downstream co= de. + * Any verification with schematics would be greatly appreciated. + * + * Copyright (c) 2023, Richard Acayan. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_comp_rx, + LPI_MUX_dmic12, + LPI_MUX_dmic34, + LPI_MUX_mclk0, + LPI_MUX_pdm_2_gpios, + LPI_MUX_pdm_clk, + LPI_MUX_pdm_rx, + LPI_MUX_pdm_sync, + + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc sdm660_lpi_pinctrl_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), +}; + +static const char * const comp_rx_groups[] =3D { "gpio22", "gpio24" }; +static const char * const dmic12_groups[] =3D { "gpio26", "gpio28" }; +static const char * const dmic34_groups[] =3D { "gpio27", "gpio29" }; +static const char * const mclk0_groups[] =3D { "gpio18" }; +static const char * const pdm_2_gpios_groups[] =3D { "gpio20" }; +static const char * const pdm_clk_groups[] =3D { "gpio18" }; +static const char * const pdm_rx_groups[] =3D { "gpio21", "gpio23", "gpio2= 5" }; +static const char * const pdm_sync_groups[] =3D { "gpio19" }; + +const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] =3D { + LPI_PINGROUP_OFFSET(0, LPI_NO_SLEW, _, _, _, _, 0x0000), + LPI_PINGROUP_OFFSET(1, LPI_NO_SLEW, _, _, _, _, 0x1000), + LPI_PINGROUP_OFFSET(2, LPI_NO_SLEW, _, _, _, _, 0x2000), + LPI_PINGROUP_OFFSET(3, LPI_NO_SLEW, _, _, _, _, 0x2010), + LPI_PINGROUP_OFFSET(4, LPI_NO_SLEW, _, _, _, _, 0x3000), + LPI_PINGROUP_OFFSET(5, LPI_NO_SLEW, _, _, _, _, 0x3010), + LPI_PINGROUP_OFFSET(6, LPI_NO_SLEW, _, _, _, _, 0x4000), + LPI_PINGROUP_OFFSET(7, LPI_NO_SLEW, _, _, _, _, 0x4010), + LPI_PINGROUP_OFFSET(8, LPI_NO_SLEW, _, _, _, _, 0x5000), + LPI_PINGROUP_OFFSET(9, LPI_NO_SLEW, _, _, _, _, 0x5010), + LPI_PINGROUP_OFFSET(10, LPI_NO_SLEW, _, _, _, _, 0x5020), + LPI_PINGROUP_OFFSET(11, LPI_NO_SLEW, _, _, _, _, 0x5030), + LPI_PINGROUP_OFFSET(12, LPI_NO_SLEW, _, _, _, _, 0x6000), + LPI_PINGROUP_OFFSET(13, LPI_NO_SLEW, _, _, _, _, 0x6010), + LPI_PINGROUP_OFFSET(14, LPI_NO_SLEW, _, _, _, _, 0x7000), + LPI_PINGROUP_OFFSET(15, LPI_NO_SLEW, _, _, _, _, 0x7010), + LPI_PINGROUP_OFFSET(16, LPI_NO_SLEW, _, _, _, _, 0x5040), + LPI_PINGROUP_OFFSET(17, LPI_NO_SLEW, _, _, _, _, 0x5050), + + /* The function names of the PDM GPIOs are derived from SDM670 */ + LPI_PINGROUP_OFFSET(18, LPI_NO_SLEW, pdm_clk, mclk0, _, _, 0x8000), + LPI_PINGROUP_OFFSET(19, LPI_NO_SLEW, pdm_sync, _, _, _, 0x8010), + LPI_PINGROUP_OFFSET(20, LPI_NO_SLEW, pdm_2_gpios, _, _, _, 0x8020), + LPI_PINGROUP_OFFSET(21, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8030), + LPI_PINGROUP_OFFSET(22, LPI_NO_SLEW, comp_rx, _, _, _, 0x8040), + LPI_PINGROUP_OFFSET(23, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8050), + LPI_PINGROUP_OFFSET(24, LPI_NO_SLEW, comp_rx, _, _, _, 0x8060), + LPI_PINGROUP_OFFSET(25, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8070), + LPI_PINGROUP_OFFSET(26, LPI_NO_SLEW, dmic12, _, _, _, 0x9000), + LPI_PINGROUP_OFFSET(27, LPI_NO_SLEW, dmic34, _, _, _, 0x9010), + LPI_PINGROUP_OFFSET(28, LPI_NO_SLEW, dmic12, _, _, _, 0xa000), + LPI_PINGROUP_OFFSET(29, LPI_NO_SLEW, dmic34, _, _, _, 0xa010), + + LPI_PINGROUP_OFFSET(30, LPI_NO_SLEW, _, _, _, _, 0xb000), + LPI_PINGROUP_OFFSET(31, LPI_NO_SLEW, _, _, _, _, 0xb010), +}; + +const struct lpi_function sdm660_lpi_pinctrl_functions[] =3D { + LPI_FUNCTION(comp_rx), + LPI_FUNCTION(dmic12), + LPI_FUNCTION(dmic34), + LPI_FUNCTION(mclk0), + LPI_FUNCTION(pdm_2_gpios), + LPI_FUNCTION(pdm_clk), + LPI_FUNCTION(pdm_rx), + LPI_FUNCTION(pdm_sync), +}; + +static const struct lpi_pinctrl_variant_data sdm660_lpi_pinctrl_data =3D { + .pins =3D sdm660_lpi_pinctrl_pins, + .npins =3D ARRAY_SIZE(sdm660_lpi_pinctrl_pins), + .groups =3D sdm660_lpi_pinctrl_groups, + .ngroups =3D ARRAY_SIZE(sdm660_lpi_pinctrl_groups), + .functions =3D sdm660_lpi_pinctrl_functions, + .nfunctions =3D ARRAY_SIZE(sdm660_lpi_pinctrl_functions), + .flags =3D LPI_FLAG_SLEW_RATE_SAME_REG | LPI_FLAG_USE_PREDEFINED_PIN_OFFS= ET +}; + +static const struct of_device_id sdm660_lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,sdm660-lpass-lpi-pinctrl", + .data =3D &sdm660_lpi_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); + +static struct platform_driver sdm660_lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-sdm660-lpass-lpi-pinctrl", + .of_match_table =3D sdm660_lpi_pinctrl_of_match, + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; +module_platform_driver(sdm660_lpi_pinctrl_driver); + +MODULE_AUTHOR("Richard Acayan "); +MODULE_DESCRIPTION("QTI SDM660 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0