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Thu, 28 Aug 2025 14:55:30 -0700 (PDT) From: David Lechner Date: Thu, 28 Aug 2025 16:54:52 -0500 Subject: [PATCH v3 1/4] dt-bindings: iio: adc: adi,ad7124: fix clocks properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-iio-adc-ad7124-proper-clock-support-v3-1-0b317b4605e5@baylibre.com> References: <20250828-iio-adc-ad7124-proper-clock-support-v3-0-0b317b4605e5@baylibre.com> In-Reply-To: <20250828-iio-adc-ad7124-proper-clock-support-v3-0-0b317b4605e5@baylibre.com> To: Michael Hennerich , Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, David Lechner X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3149; i=dlechner@baylibre.com; h=from:subject:message-id; bh=ejiW++p+A0I9xjvm23IuPsPQ6EO4iCmJb+R47NFoGFU=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBosNA1O0KkNBJ9aNcMpiNpN0mL0yWZXDt161WKd V7fJ3SqsHGJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaLDQNQAKCRDCzCAB/wGP wCbiB/4+PzMxVzV3DSBjQKryiHukMKB7ZFrX8RalKvJGOisgzuD7Prh4Spexa2ufXG7KI7T+KrL 0HgkRQIJB/+/T0e0fcf6E1x9g+xJX3Rsvpnlv7qS7oPwOY/ciuy30+/wo0caKSp7a3JTF53BdxB 0gT7fGFowhXpZCDgJj+tSA7Q84dD+dNCexnLvwXxDe22VrM0ieC8i1NY7LdgfPJ71r16kiqDoZV W3lxQ5ugVV7PjfHMumHQaQyNyHapt8xRTl8Q6JCGlPBDgA4ylm5f478Xbsl1ztt2kSO618XrrFV QObtXUbz30UCRPrghl+sXVBW5iYPUCzLxWx+cQrBwTkyJbkS X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Use correct clocks properties for the AD7124 family of ADCs. These ADCs have an internal clock along with an optional external clock that can be connected to the CLK pin. This pin can be wired up 3 ways: 1. Not connected - the internal clock is used. 2. Connected to an external clock (input) - the external clock is used. 3. Connected to the CLK pin on another ADC (output) - the internal clock is used on one and the other is configured for an external clock. The new bindings describe these 3 cases by picking one of the following: 1. Omit both clocks and #clock-cells properties. 2. Include only the clocks property with a phandle to the external clock. 3. Include only the #clock-cells property on the ADC providing the output. The clock-names property is now deprecated and should not be used. The MCLK signal that it refers to is an internal counter in the ADC and therefore does not make sense as a devicetree property as it can't be connected to anything external to the ADC. Since there is only one possible external clock, the clock-names property is not needed anyway. Based on the implementation of the Linux driver, it looks like the "mclk" clock was basically being used as a control to select the power mode of the ADC, which is not something that should be done in the devicetree. Reviewed-by: Rob Herring (Arm) Signed-off-by: David Lechner --- .../devicetree/bindings/iio/adc/adi,ad7124.yaml | 21 ++++++++++++++++-= ---- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7124.yaml index 4dd5395730c10925c86782116dfd70a75d033bfb..2e3f84db6193b3d8765e2bdbd2d= 3175cf1892ba4 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml @@ -28,12 +28,21 @@ properties: =20 clocks: maxItems: 1 - description: phandle to the master clock (mclk) + description: Optional external clock connected to the CLK pin. =20 clock-names: + deprecated: true + description: + MCLK is an internal counter in the ADC. Do not use this property. items: - const: mclk =20 + '#clock-cells': + description: + The CLK pin can be used as an output. When that is the case, include + this property. + const: 0 + interrupts: description: IRQ line for the ADC maxItems: 1 @@ -67,10 +76,14 @@ properties: required: - compatible - reg - - clocks - - clock-names - interrupts =20 +# Can't have both clock input and output at the same time. +not: + required: + - '#clock-cells' + - clocks + patternProperties: "^channel@([0-9]|1[0-5])$": $ref: adc.yaml @@ -136,8 +149,6 @@ examples: interrupt-parent =3D <&gpio>; rdy-gpios =3D <&gpio 25 GPIO_ACTIVE_LOW>; refin1-supply =3D <&adc_vref>; - clocks =3D <&ad7124_mclk>; - clock-names =3D "mclk"; =20 #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.43.0 From nobody Fri Oct 3 15:34:24 2025 Received: from mail-oa1-f48.google.com (mail-oa1-f48.google.com [209.85.160.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B2212C08A8 for ; Thu, 28 Aug 2025 21:55:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 28 Aug 2025 14:55:32 -0700 (PDT) Received: from [127.0.1.1] ([2600:8803:e7e4:1d00:aa84:2d2c:f28c:4102]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7455853804asm136084a34.33.2025.08.28.14.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 14:55:31 -0700 (PDT) From: David Lechner Date: Thu, 28 Aug 2025 16:54:53 -0500 Subject: [PATCH v3 2/4] iio: adc: ad7124: do not require mclk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-iio-adc-ad7124-proper-clock-support-v3-2-0b317b4605e5@baylibre.com> References: <20250828-iio-adc-ad7124-proper-clock-support-v3-0-0b317b4605e5@baylibre.com> In-Reply-To: <20250828-iio-adc-ad7124-proper-clock-support-v3-0-0b317b4605e5@baylibre.com> To: Michael Hennerich , Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, David Lechner X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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The MCLK is an internal counter on the ADC, so it is not something that should be coming from the devicetree. However, existing users may be using this to essentially select the power mode of the ADC from the devicetree. In order to not break those users, we have to keep the existing "mclk" handling, but now it is optional. Now, when the "mclk" clock is omitted from the devicetree, the driver will default to the full power mode. Support for an external clock and dynamic power mode switching can be added later if needed. Signed-off-by: David Lechner --- drivers/iio/adc/ad7124.c | 62 ++++++++++++++++++++++++++++++++++----------= ---- 1 file changed, 44 insertions(+), 18 deletions(-) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index 3fc24f5fffc8f200c8656cb97f9e7f80546f688b..49003c8436463f49a47564644fd= 8e405579df829 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -174,7 +174,6 @@ struct ad7124_state { struct ad_sigma_delta sd; struct ad7124_channel *channels; struct regulator *vref[4]; - struct clk *mclk; unsigned int adc_control; unsigned int num_channels; struct mutex cfgs_lock; /* lock for configs access */ @@ -254,7 +253,9 @@ static void ad7124_set_channel_odr(struct ad7124_state = *st, unsigned int channel { unsigned int fclk, odr_sel_bits; =20 - fclk =3D clk_get_rate(st->mclk); + fclk =3D ad7124_master_clk_freq_hz[FIELD_GET(AD7124_ADC_CONTROL_POWER_MOD= E, + st->adc_control)]; + /* * FS[10:0] =3D fCLK / (fADC x 32) where: * fADC is the output data rate @@ -1111,21 +1112,50 @@ static int ad7124_parse_channel_config(struct iio_d= ev *indio_dev, static int ad7124_setup(struct ad7124_state *st) { struct device *dev =3D &st->sd.spi->dev; - unsigned int fclk, power_mode; + unsigned int power_mode; + struct clk *mclk; int i, ret; =20 - fclk =3D clk_get_rate(st->mclk); - if (!fclk) - return dev_err_probe(dev, -EINVAL, "Failed to get mclk rate\n"); + /* + * Always use full power mode for max performance. If needed, the driver + * could be adapted to use a dynamic power mode based on the requested + * output data rate. + */ + power_mode =3D AD7124_ADC_CONTROL_POWER_MODE_FULL; =20 - /* The power mode changes the master clock frequency */ - power_mode =3D ad7124_find_closest_match(ad7124_master_clk_freq_hz, - ARRAY_SIZE(ad7124_master_clk_freq_hz), - fclk); - if (fclk !=3D ad7124_master_clk_freq_hz[power_mode]) { - ret =3D clk_set_rate(st->mclk, fclk); - if (ret) - return dev_err_probe(dev, ret, "Failed to set mclk rate\n"); + /* + * This "mclk" business is needed for backwards compatibility with old + * devicetrees that specified a fake clock named "mclk" to select the + * power mode. + */ + mclk =3D devm_clk_get_optional_enabled(dev, "mclk"); + if (IS_ERR(mclk)) + return dev_err_probe(dev, PTR_ERR(mclk), "Failed to get mclk\n"); + + if (mclk) { + unsigned long mclk_hz; + + mclk_hz =3D clk_get_rate(mclk); + if (!mclk_hz) + return dev_err_probe(dev, -EINVAL, + "Failed to get mclk rate\n"); + + /* + * This logic is a bit backwards, which is why it is only here + * for backwards compatibility. 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Previously, the driver only supported using the internal clock and had bad devicetree bindings that used a fake clock to essentially select the power mode. This is preserved for backwards compatibility. If the clock is not named "mclk", then we know that the devicetree is using the correct bindings and we can configure the chip to use an external clock source rather than internal. Also drop a redundant comment when configuring the register fields instead of adding more. Signed-off-by: David Lechner --- drivers/iio/adc/ad7124.c | 83 ++++++++++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 76 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index 49003c8436463f49a47564644fd8e405579df829..eb5b2028dfad0f62145edff13a2= 4e824b05e0c13 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -18,6 +18,7 @@ #include #include #include +#include =20 #include #include @@ -44,6 +45,11 @@ #define AD7124_STATUS_POR_FLAG BIT(4) =20 /* AD7124_ADC_CONTROL */ +#define AD7124_ADC_CONTROL_CLK_SEL GENMASK(1, 0) +#define AD7124_ADC_CONTROL_CLK_SEL_INT 0 +#define AD7124_ADC_CONTROL_CLK_SEL_INT_OUT 1 +#define AD7124_ADC_CONTROL_CLK_SEL_EXT 2 +#define AD7124_ADC_CONTROL_CLK_SEL_EXT_DIV4 3 #define AD7124_ADC_CONTROL_MODE GENMASK(5, 2) #define AD7124_ADC_CONTROL_MODE_CONTINUOUS 0 #define AD7124_ADC_CONTROL_MODE_SINGLE 1 @@ -92,6 +98,8 @@ #define AD7124_MAX_CONFIGS 8 #define AD7124_MAX_CHANNELS 16 =20 +#define AD7124_INT_CLK_HZ 614400 + /* AD7124 input sources */ =20 enum ad7124_ref_sel { @@ -120,9 +128,9 @@ static const unsigned int ad7124_reg_size[] =3D { }; =20 static const int ad7124_master_clk_freq_hz[3] =3D { - [AD7124_LOW_POWER] =3D 76800, - [AD7124_MID_POWER] =3D 153600, - [AD7124_FULL_POWER] =3D 614400, + [AD7124_LOW_POWER] =3D AD7124_INT_CLK_HZ / 8, + [AD7124_MID_POWER] =3D AD7124_INT_CLK_HZ / 4, + [AD7124_FULL_POWER] =3D AD7124_INT_CLK_HZ, }; =20 static const char * const ad7124_ref_names[] =3D { @@ -174,6 +182,7 @@ struct ad7124_state { struct ad_sigma_delta sd; struct ad7124_channel *channels; struct regulator *vref[4]; + u32 clk_hz; unsigned int adc_control; unsigned int num_channels; struct mutex cfgs_lock; /* lock for configs access */ @@ -249,12 +258,33 @@ static int ad7124_set_mode(struct ad_sigma_delta *sd, return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); } =20 +static u32 ad7124_get_fclk_hz(struct ad7124_state *st) +{ + enum ad7124_power_mode power_mode; + u32 fclk_hz; + + power_mode =3D FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, st->adc_control); + fclk_hz =3D st->clk_hz; + + switch (power_mode) { + case AD7124_LOW_POWER: + fclk_hz /=3D 8; + break; + case AD7124_MID_POWER: + fclk_hz /=3D 4; + break; + default: + break; + } + + return fclk_hz; +} + static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int c= hannel, unsigned int odr) { unsigned int fclk, odr_sel_bits; =20 - fclk =3D ad7124_master_clk_freq_hz[FIELD_GET(AD7124_ADC_CONTROL_POWER_MOD= E, - st->adc_control)]; + fclk =3D ad7124_get_fclk_hz(st); =20 /* * FS[10:0] =3D fCLK / (fADC x 32) where: @@ -1112,7 +1142,7 @@ static int ad7124_parse_channel_config(struct iio_dev= *indio_dev, static int ad7124_setup(struct ad7124_state *st) { struct device *dev =3D &st->sd.spi->dev; - unsigned int power_mode; + unsigned int power_mode, clk_sel; struct clk *mclk; int i, ret; =20 @@ -1156,9 +1186,48 @@ static int ad7124_setup(struct ad7124_state *st) return dev_err_probe(dev, ret, "Failed to set mclk rate\n"); } + + clk_sel =3D AD7124_ADC_CONTROL_CLK_SEL_INT; + st->clk_hz =3D AD7124_INT_CLK_HZ; + } else { + struct clk *clk; + + clk =3D devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get external clock\n"); + + if (clk) { + unsigned long clk_hz; + + clk_hz =3D clk_get_rate(clk); + if (!clk_hz) + return dev_err_probe(dev, -EINVAL, + "Failed to get external clock rate\n"); + + /* + * The external clock may be 4x the nominal clock rate, + * in which case the ADC needs to be configured to + * divide it by 4. Using MEGA is a bit arbitrary, but + * the expected clock rates are either 614.4 kHz or + * 2.4576 MHz, so this should work. + */ + if (clk_hz > MEGA) { + clk_sel =3D AD7124_ADC_CONTROL_CLK_SEL_EXT_DIV4; + st->clk_hz =3D clk_hz / 4; + } else { + clk_sel =3D AD7124_ADC_CONTROL_CLK_SEL_EXT; + st->clk_hz =3D clk_hz; + } + } else { + clk_sel =3D AD7124_ADC_CONTROL_CLK_SEL_INT; + st->clk_hz =3D AD7124_INT_CLK_HZ; + } } =20 - /* Set the power mode */ + st->adc_control &=3D ~AD7124_ADC_CONTROL_CLK_SEL; + st->adc_control |=3D FIELD_PREP(AD7124_ADC_CONTROL_CLK_SEL, clk_sel); + st->adc_control &=3D ~AD7124_ADC_CONTROL_POWER_MODE; st->adc_control |=3D FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, power_mode= ); =20 --=20 2.43.0 From nobody Fri Oct 3 15:34:24 2025 Received: from mail-ot1-f42.google.com (mail-ot1-f42.google.com [209.85.210.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17BE72C2377 for ; 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If the #clock-cells property is present, turn on the internal clock output during probe. If both the clocks and #clock-names properties are present (not allowed by devicetree bindings), assume that an external clock is being used so that we don't accidentally have two outputs fighting each other. Signed-off-by: David Lechner --- drivers/iio/adc/ad7124.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index eb5b2028dfad0f62145edff13a24e824b05e0c13..9b410571413429a99ea3303f493= 77f8a7e0ceba6 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -6,7 +6,9 @@ */ #include #include +#include #include +#include #include #include #include @@ -18,6 +20,7 @@ #include #include #include +#include #include =20 #include @@ -1189,6 +1192,36 @@ static int ad7124_setup(struct ad7124_state *st) =20 clk_sel =3D AD7124_ADC_CONTROL_CLK_SEL_INT; st->clk_hz =3D AD7124_INT_CLK_HZ; + } else if (!device_property_present(dev, "clocks") && + device_property_present(dev, "#clock-cells")) { +#ifdef CONFIG_COMMON_CLK + struct clk_hw *clk_hw; + + const char *name __free(kfree) =3D kasprintf(GFP_KERNEL, "%pfwP-clk", + dev_fwnode(dev)); + if (!name) + return -ENOMEM; + + clk_hw =3D devm_clk_hw_register_fixed_rate(dev, name, NULL, 0, + AD7124_INT_CLK_HZ); + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "Failed to register clock provider\n"); + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + clk_hw); + if (ret) + return dev_err_probe(dev, ret, + "Failed to add clock provider\n"); +#endif + + /* + * Treat the clock as always on. This way we don't have to deal + * with someone trying to enable/disable the clock while we are + * reading samples. + */ + clk_sel =3D AD7124_ADC_CONTROL_CLK_SEL_INT_OUT; + st->clk_hz =3D AD7124_INT_CLK_HZ; } else { struct clk *clk; =20 --=20 2.43.0