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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70e6264141asm5588696d6.65.2025.08.28.17.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 17:38:40 -0700 (PDT) From: Brian Masney Date: Thu, 28 Aug 2025 20:38:21 -0400 Subject: [PATCH 2/8] clk: qcom: alpha-pll: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-clk-round-rate-v2-v1-2-b97ec8ba6cc4@redhat.com> References: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> In-Reply-To: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> To: Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Piotr Wojtaszczyk , Chen Wang , Inochi Amaoto , Michal Simek , Bjorn Andersson , Heiko Stuebner , Andrea della Porta , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Masney , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756427914; l=16351; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=9nEbhYDzoBNmi/PobaJ6T7eWIrqDvbzH5yntpiRsu9M=; b=yHjmM+DGGOe8RhI6LsZ4fKGbYLCUkFCUKPgF3b+Os98dKIFFNeETSye5rdIeMch6evCEu7Qc+ inxr7bfCHGfCY6zkCyUCEGmPGyXcjFklda6J92sJyLbN0yRRIamnynB X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Note that prior to running the Coccinelle, clk_alpha_pll_postdiv_round_ro_rate() was renamed to clk_alpha_pll_postdiv_ro_round_rate(). Reviewed-by: Konrad Dybcio Signed-off-by: Brian Masney --- drivers/clk/qcom/clk-alpha-pll.c | 136 ++++++++++++++++++++++-------------= ---- 1 file changed, 77 insertions(+), 59 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index 81a1ce42285f7eb19dba92cb7415c7e694a829dd..6aeba40358c11e44c5f39d15f14= 9d62149393cd3 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -849,22 +849,25 @@ static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw= *hw, unsigned long rate, clk_alpha_pll_hwfsm_is_enabled); } =20 -static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_alpha_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); u32 l, alpha_width =3D pll_alpha_width(pll); u64 a; unsigned long min_freq, max_freq; =20 - rate =3D alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); - if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) - return rate; + req->rate =3D alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, + &a, alpha_width); + if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) + return 0; =20 min_freq =3D pll->vco_table[0].min_freq; max_freq =3D pll->vco_table[pll->num_vco - 1].max_freq; =20 - return clamp(rate, min_freq, max_freq); + req->rate =3D clamp(req->rate, min_freq, max_freq); + + return 0; } =20 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regma= p *regmap, @@ -1048,12 +1051,15 @@ static int alpha_pll_huayra_set_rate(struct clk_hw = *hw, unsigned long rate, return 0; } =20 -static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long r= ate, - unsigned long *prate) +static int alpha_pll_huayra_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { u32 l, a; =20 - return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); + req->rate =3D alpha_huayra_pll_round_rate(req->rate, + req->best_parent_rate, &l, &a); + + return 0; } =20 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, @@ -1175,7 +1181,7 @@ const struct clk_ops clk_alpha_pll_ops =3D { .disable =3D clk_alpha_pll_disable, .is_enabled =3D clk_alpha_pll_is_enabled, .recalc_rate =3D clk_alpha_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D clk_alpha_pll_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); @@ -1185,7 +1191,7 @@ const struct clk_ops clk_alpha_pll_huayra_ops =3D { .disable =3D clk_alpha_pll_disable, .is_enabled =3D clk_alpha_pll_is_enabled, .recalc_rate =3D alpha_pll_huayra_recalc_rate, - .round_rate =3D alpha_pll_huayra_round_rate, + .determine_rate =3D alpha_pll_huayra_determine_rate, .set_rate =3D alpha_pll_huayra_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); @@ -1195,7 +1201,7 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops =3D { .disable =3D clk_alpha_pll_hwfsm_disable, .is_enabled =3D clk_alpha_pll_hwfsm_is_enabled, .recalc_rate =3D clk_alpha_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D clk_alpha_pll_hwfsm_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); @@ -1205,7 +1211,7 @@ const struct clk_ops clk_alpha_pll_fixed_trion_ops = =3D { .disable =3D clk_trion_pll_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); =20 @@ -1240,9 +1246,8 @@ static const struct clk_div_table clk_alpha_2bit_div_= table[] =3D { { } }; =20 -static long -clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_alpha_pll_postdiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll_postdiv *pll =3D to_clk_alpha_pll_postdiv(hw); const struct clk_div_table *table; @@ -1252,13 +1257,15 @@ clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw,= unsigned long rate, else table =3D clk_alpha_div_table; =20 - return divider_round_rate(hw, rate, prate, table, - pll->width, CLK_DIVIDER_POWER_OF_TWO); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + table, pll->width, + CLK_DIVIDER_POWER_OF_TWO); + + return 0; } =20 -static long -clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_alpha_pll_postdiv_ro_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll_postdiv *pll =3D to_clk_alpha_pll_postdiv(hw); u32 ctl, div; @@ -1270,9 +1277,12 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *h= w, unsigned long rate, div =3D 1 << fls(ctl); =20 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) - *prate =3D clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); + req->best_parent_rate =3D clk_hw_round_rate(clk_hw_get_parent(hw), + div * req->rate); + + req->rate =3D DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); =20 - return DIV_ROUND_UP_ULL((u64)*prate, div); + return 0; } =20 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long= rate, @@ -1291,13 +1301,13 @@ static int clk_alpha_pll_postdiv_set_rate(struct cl= k_hw *hw, unsigned long rate, =20 const struct clk_ops clk_alpha_pll_postdiv_ops =3D { .recalc_rate =3D clk_alpha_pll_postdiv_recalc_rate, - .round_rate =3D clk_alpha_pll_postdiv_round_rate, + .determine_rate =3D clk_alpha_pll_postdiv_determine_rate, .set_rate =3D clk_alpha_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); =20 const struct clk_ops clk_alpha_pll_postdiv_ro_ops =3D { - .round_rate =3D clk_alpha_pll_postdiv_round_ro_rate, + .determine_rate =3D clk_alpha_pll_postdiv_ro_determine_rate, .recalc_rate =3D clk_alpha_pll_postdiv_recalc_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); @@ -1542,7 +1552,7 @@ const struct clk_ops clk_alpha_pll_fabia_ops =3D { .is_enabled =3D clk_alpha_pll_is_enabled, .set_rate =3D alpha_pll_fabia_set_rate, .recalc_rate =3D alpha_pll_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); =20 @@ -1551,7 +1561,7 @@ const struct clk_ops clk_alpha_pll_fixed_fabia_ops = =3D { .disable =3D alpha_pll_fabia_disable, .is_enabled =3D clk_alpha_pll_is_enabled, .recalc_rate =3D alpha_pll_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); =20 @@ -1602,14 +1612,16 @@ clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw= , unsigned long parent_rate) return (parent_rate / div); } =20 -static long -clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_trion_pll_postdiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll_postdiv *pll =3D to_clk_alpha_pll_postdiv(hw); =20 - return divider_round_rate(hw, rate, prate, pll->post_div_table, - pll->width, CLK_DIVIDER_ROUND_CLOSEST); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + pll->post_div_table, + pll->width, CLK_DIVIDER_ROUND_CLOSEST); + + return 0; }; =20 static int @@ -1635,18 +1647,21 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, u= nsigned long rate, =20 const struct clk_ops clk_alpha_pll_postdiv_trion_ops =3D { .recalc_rate =3D clk_trion_pll_postdiv_recalc_rate, - .round_rate =3D clk_trion_pll_postdiv_round_rate, + .determine_rate =3D clk_trion_pll_postdiv_determine_rate, .set_rate =3D clk_trion_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); =20 -static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *prate) +static int clk_alpha_pll_postdiv_fabia_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll_postdiv *pll =3D to_clk_alpha_pll_postdiv(hw); =20 - return divider_round_rate(hw, rate, prate, pll->post_div_table, - pll->width, CLK_DIVIDER_ROUND_CLOSEST); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + pll->post_div_table, + pll->width, CLK_DIVIDER_ROUND_CLOSEST); + + return 0; } =20 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, @@ -1681,7 +1696,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struc= t clk_hw *hw, =20 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops =3D { .recalc_rate =3D clk_alpha_pll_postdiv_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_postdiv_fabia_round_rate, + .determine_rate =3D clk_alpha_pll_postdiv_fabia_determine_rate, .set_rate =3D clk_alpha_pll_postdiv_fabia_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); @@ -1833,7 +1848,7 @@ const struct clk_ops clk_alpha_pll_trion_ops =3D { .disable =3D clk_trion_pll_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D alpha_pll_trion_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); @@ -1844,14 +1859,14 @@ const struct clk_ops clk_alpha_pll_lucid_ops =3D { .disable =3D clk_trion_pll_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D alpha_pll_trion_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); =20 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops =3D { .recalc_rate =3D clk_alpha_pll_postdiv_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_postdiv_fabia_round_rate, + .determine_rate =3D clk_alpha_pll_postdiv_fabia_determine_rate, .set_rate =3D clk_alpha_pll_postdiv_fabia_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); @@ -1903,7 +1918,7 @@ const struct clk_ops clk_alpha_pll_agera_ops =3D { .disable =3D clk_alpha_pll_disable, .is_enabled =3D clk_alpha_pll_is_enabled, .recalc_rate =3D alpha_pll_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D clk_alpha_pll_agera_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); @@ -2119,7 +2134,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops =3D= { .disable =3D alpha_pll_lucid_5lpe_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D alpha_pll_lucid_5lpe_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); @@ -2129,13 +2144,13 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe= _ops =3D { .disable =3D alpha_pll_lucid_5lpe_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); =20 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops =3D { .recalc_rate =3D clk_alpha_pll_postdiv_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_postdiv_fabia_round_rate, + .determine_rate =3D clk_alpha_pll_postdiv_fabia_determine_rate, .set_rate =3D clk_lucid_5lpe_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); @@ -2304,7 +2319,7 @@ const struct clk_ops clk_alpha_pll_zonda_ops =3D { .disable =3D clk_zonda_pll_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D clk_zonda_pll_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); @@ -2529,13 +2544,13 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_evo_= ops =3D { .disable =3D alpha_pll_lucid_evo_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D alpha_pll_lucid_evo_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); =20 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops =3D { .recalc_rate =3D clk_alpha_pll_postdiv_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_postdiv_fabia_round_rate, + .determine_rate =3D clk_alpha_pll_postdiv_fabia_determine_rate, .set_rate =3D clk_lucid_evo_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); @@ -2546,7 +2561,7 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops =3D { .disable =3D alpha_pll_lucid_evo_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D alpha_pll_lucid_evo_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D alpha_pll_lucid_5lpe_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); @@ -2557,7 +2572,7 @@ const struct clk_ops clk_alpha_pll_reset_lucid_evo_op= s =3D { .disable =3D alpha_pll_reset_lucid_evo_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D alpha_pll_lucid_evo_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D alpha_pll_lucid_5lpe_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); @@ -2732,22 +2747,25 @@ static unsigned long clk_rivian_evo_pll_recalc_rate= (struct clk_hw *hw, return parent_rate * l; } =20 -static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long= rate, - unsigned long *prate) +static int clk_rivian_evo_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); unsigned long min_freq, max_freq; u32 l; u64 a; =20 - rate =3D alpha_pll_round_rate(rate, *prate, &l, &a, 0); - if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) - return rate; + req->rate =3D alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, + &a, 0); + if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) + return 0; =20 min_freq =3D pll->vco_table[0].min_freq; max_freq =3D pll->vco_table[pll->num_vco - 1].max_freq; =20 - return clamp(rate, min_freq, max_freq); + req->rate =3D clamp(req->rate, min_freq, max_freq); + + return 0; } =20 const struct clk_ops clk_alpha_pll_rivian_evo_ops =3D { @@ -2755,7 +2773,7 @@ const struct clk_ops clk_alpha_pll_rivian_evo_ops =3D= { .disable =3D alpha_pll_lucid_5lpe_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_rivian_evo_pll_recalc_rate, - .round_rate =3D clk_rivian_evo_pll_round_rate, + .determine_rate =3D clk_rivian_evo_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); =20 @@ -2964,7 +2982,7 @@ const struct clk_ops clk_alpha_pll_regera_ops =3D { .disable =3D clk_zonda_pll_disable, .is_enabled =3D clk_alpha_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D clk_zonda_pll_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops); @@ -3169,7 +3187,7 @@ const struct clk_ops clk_alpha_pll_slew_ops =3D { .enable =3D clk_alpha_pll_slew_enable, .disable =3D clk_alpha_pll_disable, .recalc_rate =3D clk_alpha_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D clk_alpha_pll_slew_set_rate, }; EXPORT_SYMBOL(clk_alpha_pll_slew_ops); --=20 2.50.1