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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70e6264141asm5588696d6.65.2025.08.28.17.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 17:38:37 -0700 (PDT) From: Brian Masney Date: Thu, 28 Aug 2025 20:38:20 -0400 Subject: [PATCH 1/8] clk: nxp: lpc32xx: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-clk-round-rate-v2-v1-1-b97ec8ba6cc4@redhat.com> References: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> In-Reply-To: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> To: Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Piotr Wojtaszczyk , Chen Wang , Inochi Amaoto , Michal Simek , Bjorn Andersson , Heiko Stuebner , Andrea della Porta , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756427914; l=6057; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=3ht1wGseKshyK0elknVvnPuwk+xst31YCIMTYyJbsnI=; b=vBgDN2UolIYgWOoWXbkA84AYONG/GqJkkikThkMURYKOSkSyvbFpmEqJUiCoeaUkKgCqq7nEQ DFy61Z9uuUoC1htEQWfzBbUhQKFicg1qdsl//DSZRp+vreyJtcnSot0 X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Note that the changes involving LPC32XX_DEFINE_PLL_OPS were done by hand. Signed-off-by: Brian Masney --- drivers/clk/nxp/clk-lpc32xx.c | 59 ++++++++++++++++++++++++---------------= ---- 1 file changed, 33 insertions(+), 26 deletions(-) diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index 96a1a527b3808573d3ce2c73af066a0bf37f1245..23f980cf6a2b59ee1c93a2519fe= 5188d251fa12f 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -578,17 +578,17 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsign= ed long rate, return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val); } =20 -static long clk_hclk_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int clk_hclk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct lpc32xx_pll_clk *clk =3D to_lpc32xx_pll_clk(hw); - u64 m_i, o =3D rate, i =3D *parent_rate, d =3D (u64)rate << 6; + u64 m_i, o =3D req->rate, i =3D req->best_parent_rate, d =3D (u64)req->ra= te << 6; u64 m =3D 0, n =3D 0, p =3D 0; int p_i, n_i; =20 - pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); + pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), req->best_parent_rate, req= ->rate); =20 - if (rate > 266500000) + if (req->rate > 266500000) return -EINVAL; =20 /* Have to check all 20 possibilities to find the minimal M */ @@ -613,9 +613,9 @@ static long clk_hclk_pll_round_rate(struct clk_hw *hw, = unsigned long rate, } } =20 - if (d =3D=3D (u64)rate << 6) { + if (d =3D=3D (u64)req->rate << 6) { pr_err("%s: %lu: no valid PLL parameters are found\n", - clk_hw_get_name(hw), rate); + clk_hw_get_name(hw), req->rate); return -EINVAL; } =20 @@ -633,22 +633,25 @@ static long clk_hclk_pll_round_rate(struct clk_hw *hw= , unsigned long rate, =20 if (!d) pr_debug("%s: %lu: found exact match: %llu/%llu/%llu\n", - clk_hw_get_name(hw), rate, m, n, p); + clk_hw_get_name(hw), req->rate, m, n, p); else pr_debug("%s: %lu: found closest: %llu/%llu/%llu - %llu\n", - clk_hw_get_name(hw), rate, m, n, p, o); + clk_hw_get_name(hw), req->rate, m, n, p, o); =20 - return o; + req->rate =3D o; + + return 0; } =20 -static long clk_usb_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int clk_usb_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct lpc32xx_pll_clk *clk =3D to_lpc32xx_pll_clk(hw); struct clk_hw *usb_div_hw, *osc_hw; u64 d_i, n_i, m, o; =20 - pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); + pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), req->best_parent_rate, + req->rate); =20 /* * The only supported USB clock is 48MHz, with PLL internal constraints @@ -656,7 +659,7 @@ static long clk_usb_pll_round_rate(struct clk_hw *hw, u= nsigned long rate, * and post-divider must be 4, this slightly simplifies calculation of * USB divider, USB PLL N and M parameters. */ - if (rate !=3D 48000000) + if (req->rate !=3D 48000000) return -EINVAL; =20 /* USB divider clock */ @@ -684,30 +687,30 @@ static long clk_usb_pll_round_rate(struct clk_hw *hw,= unsigned long rate, clk->m_div =3D m; clk->p_div =3D 2; clk->mode =3D PLL_NON_INTEGER; - *parent_rate =3D div64_u64(o, d_i); + req->best_parent_rate =3D div64_u64(o, d_i); =20 - return rate; + return 0; } } =20 return -EINVAL; } =20 -#define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _rr) \ +#define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _dr) \ static const struct clk_ops clk_ ##_name ## _ops =3D { \ .enable =3D clk_pll_enable, \ .disable =3D clk_pll_disable, \ .is_enabled =3D clk_pll_is_enabled, \ .recalc_rate =3D _rc, \ .set_rate =3D _sr, \ - .round_rate =3D _rr, \ + .determine_rate =3D _dr, \ } =20 LPC32XX_DEFINE_PLL_OPS(pll_397x, clk_pll_397x_recalc_rate, NULL, NULL); LPC32XX_DEFINE_PLL_OPS(hclk_pll, clk_pll_recalc_rate, - clk_pll_set_rate, clk_hclk_pll_round_rate); + clk_pll_set_rate, clk_hclk_pll_determine_rate); LPC32XX_DEFINE_PLL_OPS(usb_pll, clk_pll_recalc_rate, - clk_pll_set_rate, clk_usb_pll_round_rate); + clk_pll_set_rate, clk_usb_pll_determine_rate); =20 static int clk_ddram_is_enabled(struct clk_hw *hw) { @@ -954,8 +957,8 @@ static unsigned long clk_divider_recalc_rate(struct clk= _hw *hw, divider->flags, divider->width); } =20 -static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct lpc32xx_clk_div *divider =3D to_lpc32xx_div(hw); unsigned int bestdiv; @@ -967,11 +970,15 @@ static long clk_divider_round_rate(struct clk_hw *hw,= unsigned long rate, bestdiv &=3D div_mask(divider->width); bestdiv =3D _get_div(divider->table, bestdiv, divider->flags, divider->width); - return DIV_ROUND_UP(*prate, bestdiv); + req->rate =3D DIV_ROUND_UP(req->best_parent_rate, bestdiv); + + return 0; } =20 - return divider_round_rate(hw, rate, prate, divider->table, - divider->width, divider->flags); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + divider->table, divider->width, divider->flags); + + return 0; } =20 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, @@ -990,7 +997,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsi= gned long rate, =20 static const struct clk_ops lpc32xx_clk_divider_ops =3D { .recalc_rate =3D clk_divider_recalc_rate, - .round_rate =3D clk_divider_round_rate, + .determine_rate =3D clk_divider_determine_rate, .set_rate =3D clk_divider_set_rate, }; =20 --=20 2.50.1