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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70e6264141asm5588696d6.65.2025.08.28.17.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 17:38:37 -0700 (PDT) From: Brian Masney Date: Thu, 28 Aug 2025 20:38:20 -0400 Subject: [PATCH 1/8] clk: nxp: lpc32xx: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-clk-round-rate-v2-v1-1-b97ec8ba6cc4@redhat.com> References: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> In-Reply-To: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> To: Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Piotr Wojtaszczyk , Chen Wang , Inochi Amaoto , Michal Simek , Bjorn Andersson , Heiko Stuebner , Andrea della Porta , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756427914; l=6057; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=3ht1wGseKshyK0elknVvnPuwk+xst31YCIMTYyJbsnI=; b=vBgDN2UolIYgWOoWXbkA84AYONG/GqJkkikThkMURYKOSkSyvbFpmEqJUiCoeaUkKgCqq7nEQ DFy61Z9uuUoC1htEQWfzBbUhQKFicg1qdsl//DSZRp+vreyJtcnSot0 X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Note that the changes involving LPC32XX_DEFINE_PLL_OPS were done by hand. Signed-off-by: Brian Masney --- drivers/clk/nxp/clk-lpc32xx.c | 59 ++++++++++++++++++++++++---------------= ---- 1 file changed, 33 insertions(+), 26 deletions(-) diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index 96a1a527b3808573d3ce2c73af066a0bf37f1245..23f980cf6a2b59ee1c93a2519fe= 5188d251fa12f 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -578,17 +578,17 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsign= ed long rate, return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val); } =20 -static long clk_hclk_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int clk_hclk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct lpc32xx_pll_clk *clk =3D to_lpc32xx_pll_clk(hw); - u64 m_i, o =3D rate, i =3D *parent_rate, d =3D (u64)rate << 6; + u64 m_i, o =3D req->rate, i =3D req->best_parent_rate, d =3D (u64)req->ra= te << 6; u64 m =3D 0, n =3D 0, p =3D 0; int p_i, n_i; =20 - pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); + pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), req->best_parent_rate, req= ->rate); =20 - if (rate > 266500000) + if (req->rate > 266500000) return -EINVAL; =20 /* Have to check all 20 possibilities to find the minimal M */ @@ -613,9 +613,9 @@ static long clk_hclk_pll_round_rate(struct clk_hw *hw, = unsigned long rate, } } =20 - if (d =3D=3D (u64)rate << 6) { + if (d =3D=3D (u64)req->rate << 6) { pr_err("%s: %lu: no valid PLL parameters are found\n", - clk_hw_get_name(hw), rate); + clk_hw_get_name(hw), req->rate); return -EINVAL; } =20 @@ -633,22 +633,25 @@ static long clk_hclk_pll_round_rate(struct clk_hw *hw= , unsigned long rate, =20 if (!d) pr_debug("%s: %lu: found exact match: %llu/%llu/%llu\n", - clk_hw_get_name(hw), rate, m, n, p); + clk_hw_get_name(hw), req->rate, m, n, p); else pr_debug("%s: %lu: found closest: %llu/%llu/%llu - %llu\n", - clk_hw_get_name(hw), rate, m, n, p, o); + clk_hw_get_name(hw), req->rate, m, n, p, o); =20 - return o; + req->rate =3D o; + + return 0; } =20 -static long clk_usb_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int clk_usb_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct lpc32xx_pll_clk *clk =3D to_lpc32xx_pll_clk(hw); struct clk_hw *usb_div_hw, *osc_hw; u64 d_i, n_i, m, o; =20 - pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); + pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), req->best_parent_rate, + req->rate); =20 /* * The only supported USB clock is 48MHz, with PLL internal constraints @@ -656,7 +659,7 @@ static long clk_usb_pll_round_rate(struct clk_hw *hw, u= nsigned long rate, * and post-divider must be 4, this slightly simplifies calculation of * USB divider, USB PLL N and M parameters. */ - if (rate !=3D 48000000) + if (req->rate !=3D 48000000) return -EINVAL; =20 /* USB divider clock */ @@ -684,30 +687,30 @@ static long clk_usb_pll_round_rate(struct clk_hw *hw,= unsigned long rate, clk->m_div =3D m; clk->p_div =3D 2; clk->mode =3D PLL_NON_INTEGER; - *parent_rate =3D div64_u64(o, d_i); + req->best_parent_rate =3D div64_u64(o, d_i); =20 - return rate; + return 0; } } =20 return -EINVAL; } =20 -#define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _rr) \ +#define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _dr) \ static const struct clk_ops clk_ ##_name ## _ops =3D { \ .enable =3D clk_pll_enable, \ .disable =3D clk_pll_disable, \ .is_enabled =3D clk_pll_is_enabled, \ .recalc_rate =3D _rc, \ .set_rate =3D _sr, \ - .round_rate =3D _rr, \ + .determine_rate =3D _dr, \ } =20 LPC32XX_DEFINE_PLL_OPS(pll_397x, clk_pll_397x_recalc_rate, NULL, NULL); LPC32XX_DEFINE_PLL_OPS(hclk_pll, clk_pll_recalc_rate, - clk_pll_set_rate, clk_hclk_pll_round_rate); + clk_pll_set_rate, clk_hclk_pll_determine_rate); LPC32XX_DEFINE_PLL_OPS(usb_pll, clk_pll_recalc_rate, - clk_pll_set_rate, clk_usb_pll_round_rate); + clk_pll_set_rate, clk_usb_pll_determine_rate); =20 static int clk_ddram_is_enabled(struct clk_hw *hw) { @@ -954,8 +957,8 @@ static unsigned long clk_divider_recalc_rate(struct clk= _hw *hw, divider->flags, divider->width); } =20 -static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct lpc32xx_clk_div *divider =3D to_lpc32xx_div(hw); unsigned int bestdiv; @@ -967,11 +970,15 @@ static long clk_divider_round_rate(struct clk_hw *hw,= unsigned long rate, bestdiv &=3D div_mask(divider->width); bestdiv =3D _get_div(divider->table, bestdiv, divider->flags, divider->width); - return DIV_ROUND_UP(*prate, bestdiv); + req->rate =3D DIV_ROUND_UP(req->best_parent_rate, bestdiv); + + return 0; } =20 - return divider_round_rate(hw, rate, prate, divider->table, - divider->width, divider->flags); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + divider->table, divider->width, divider->flags); + + return 0; } =20 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, @@ -990,7 +997,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsi= gned long rate, =20 static const struct clk_ops lpc32xx_clk_divider_ops =3D { .recalc_rate =3D clk_divider_recalc_rate, - .round_rate =3D clk_divider_round_rate, + .determine_rate =3D clk_divider_determine_rate, .set_rate =3D clk_divider_set_rate, }; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70e6264141asm5588696d6.65.2025.08.28.17.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 17:38:40 -0700 (PDT) From: Brian Masney Date: Thu, 28 Aug 2025 20:38:21 -0400 Subject: [PATCH 2/8] clk: qcom: alpha-pll: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-clk-round-rate-v2-v1-2-b97ec8ba6cc4@redhat.com> References: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> In-Reply-To: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> To: Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Piotr Wojtaszczyk , Chen Wang , Inochi Amaoto , Michal Simek , Bjorn Andersson , Heiko Stuebner , Andrea della Porta , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Masney , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756427914; l=16351; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=9nEbhYDzoBNmi/PobaJ6T7eWIrqDvbzH5yntpiRsu9M=; b=yHjmM+DGGOe8RhI6LsZ4fKGbYLCUkFCUKPgF3b+Os98dKIFFNeETSye5rdIeMch6evCEu7Qc+ inxr7bfCHGfCY6zkCyUCEGmPGyXcjFklda6J92sJyLbN0yRRIamnynB X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Note that prior to running the Coccinelle, clk_alpha_pll_postdiv_round_ro_rate() was renamed to clk_alpha_pll_postdiv_ro_round_rate(). Reviewed-by: Konrad Dybcio Signed-off-by: Brian Masney --- drivers/clk/qcom/clk-alpha-pll.c | 136 ++++++++++++++++++++++-------------= ---- 1 file changed, 77 insertions(+), 59 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index 81a1ce42285f7eb19dba92cb7415c7e694a829dd..6aeba40358c11e44c5f39d15f14= 9d62149393cd3 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -849,22 +849,25 @@ static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw= *hw, unsigned long rate, clk_alpha_pll_hwfsm_is_enabled); } =20 -static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_alpha_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); u32 l, alpha_width =3D pll_alpha_width(pll); u64 a; unsigned long min_freq, max_freq; =20 - rate =3D alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); - if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) - return rate; + req->rate =3D alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, + &a, alpha_width); + if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) + return 0; =20 min_freq =3D pll->vco_table[0].min_freq; max_freq =3D pll->vco_table[pll->num_vco - 1].max_freq; =20 - return clamp(rate, min_freq, max_freq); + req->rate =3D clamp(req->rate, min_freq, max_freq); + + return 0; } =20 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regma= p *regmap, @@ -1048,12 +1051,15 @@ static int alpha_pll_huayra_set_rate(struct clk_hw = *hw, unsigned long rate, return 0; } =20 -static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long r= ate, - unsigned long *prate) +static int alpha_pll_huayra_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { u32 l, a; =20 - return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); + req->rate =3D alpha_huayra_pll_round_rate(req->rate, + req->best_parent_rate, &l, &a); + + return 0; } =20 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, @@ -1175,7 +1181,7 @@ const struct clk_ops clk_alpha_pll_ops =3D { .disable =3D clk_alpha_pll_disable, .is_enabled =3D clk_alpha_pll_is_enabled, .recalc_rate =3D clk_alpha_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D clk_alpha_pll_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); @@ -1185,7 +1191,7 @@ const struct clk_ops clk_alpha_pll_huayra_ops =3D { .disable =3D clk_alpha_pll_disable, .is_enabled =3D clk_alpha_pll_is_enabled, .recalc_rate =3D alpha_pll_huayra_recalc_rate, - .round_rate =3D alpha_pll_huayra_round_rate, + .determine_rate =3D alpha_pll_huayra_determine_rate, .set_rate =3D alpha_pll_huayra_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); @@ -1195,7 +1201,7 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops =3D { .disable =3D clk_alpha_pll_hwfsm_disable, .is_enabled =3D clk_alpha_pll_hwfsm_is_enabled, .recalc_rate =3D clk_alpha_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D clk_alpha_pll_hwfsm_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); @@ -1205,7 +1211,7 @@ const struct clk_ops clk_alpha_pll_fixed_trion_ops = =3D { .disable =3D clk_trion_pll_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); =20 @@ -1240,9 +1246,8 @@ static const struct clk_div_table clk_alpha_2bit_div_= table[] =3D { { } }; =20 -static long -clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_alpha_pll_postdiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll_postdiv *pll =3D to_clk_alpha_pll_postdiv(hw); const struct clk_div_table *table; @@ -1252,13 +1257,15 @@ clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw,= unsigned long rate, else table =3D clk_alpha_div_table; =20 - return divider_round_rate(hw, rate, prate, table, - pll->width, CLK_DIVIDER_POWER_OF_TWO); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + table, pll->width, + CLK_DIVIDER_POWER_OF_TWO); + + return 0; } =20 -static long -clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_alpha_pll_postdiv_ro_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll_postdiv *pll =3D to_clk_alpha_pll_postdiv(hw); u32 ctl, div; @@ -1270,9 +1277,12 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *h= w, unsigned long rate, div =3D 1 << fls(ctl); =20 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) - *prate =3D clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); + req->best_parent_rate =3D clk_hw_round_rate(clk_hw_get_parent(hw), + div * req->rate); + + req->rate =3D DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); =20 - return DIV_ROUND_UP_ULL((u64)*prate, div); + return 0; } =20 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long= rate, @@ -1291,13 +1301,13 @@ static int clk_alpha_pll_postdiv_set_rate(struct cl= k_hw *hw, unsigned long rate, =20 const struct clk_ops clk_alpha_pll_postdiv_ops =3D { .recalc_rate =3D clk_alpha_pll_postdiv_recalc_rate, - .round_rate =3D clk_alpha_pll_postdiv_round_rate, + .determine_rate =3D clk_alpha_pll_postdiv_determine_rate, .set_rate =3D clk_alpha_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); =20 const struct clk_ops clk_alpha_pll_postdiv_ro_ops =3D { - .round_rate =3D clk_alpha_pll_postdiv_round_ro_rate, + .determine_rate =3D clk_alpha_pll_postdiv_ro_determine_rate, .recalc_rate =3D clk_alpha_pll_postdiv_recalc_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); @@ -1542,7 +1552,7 @@ const struct clk_ops clk_alpha_pll_fabia_ops =3D { .is_enabled =3D clk_alpha_pll_is_enabled, .set_rate =3D alpha_pll_fabia_set_rate, .recalc_rate =3D alpha_pll_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); =20 @@ -1551,7 +1561,7 @@ const struct clk_ops clk_alpha_pll_fixed_fabia_ops = =3D { .disable =3D alpha_pll_fabia_disable, .is_enabled =3D clk_alpha_pll_is_enabled, .recalc_rate =3D alpha_pll_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); =20 @@ -1602,14 +1612,16 @@ clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw= , unsigned long parent_rate) return (parent_rate / div); } =20 -static long -clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_trion_pll_postdiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll_postdiv *pll =3D to_clk_alpha_pll_postdiv(hw); =20 - return divider_round_rate(hw, rate, prate, pll->post_div_table, - pll->width, CLK_DIVIDER_ROUND_CLOSEST); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + pll->post_div_table, + pll->width, CLK_DIVIDER_ROUND_CLOSEST); + + return 0; }; =20 static int @@ -1635,18 +1647,21 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, u= nsigned long rate, =20 const struct clk_ops clk_alpha_pll_postdiv_trion_ops =3D { .recalc_rate =3D clk_trion_pll_postdiv_recalc_rate, - .round_rate =3D clk_trion_pll_postdiv_round_rate, + .determine_rate =3D clk_trion_pll_postdiv_determine_rate, .set_rate =3D clk_trion_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); =20 -static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *prate) +static int clk_alpha_pll_postdiv_fabia_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll_postdiv *pll =3D to_clk_alpha_pll_postdiv(hw); =20 - return divider_round_rate(hw, rate, prate, pll->post_div_table, - pll->width, CLK_DIVIDER_ROUND_CLOSEST); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + pll->post_div_table, + pll->width, CLK_DIVIDER_ROUND_CLOSEST); + + return 0; } =20 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, @@ -1681,7 +1696,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struc= t clk_hw *hw, =20 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops =3D { .recalc_rate =3D clk_alpha_pll_postdiv_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_postdiv_fabia_round_rate, + .determine_rate =3D clk_alpha_pll_postdiv_fabia_determine_rate, .set_rate =3D clk_alpha_pll_postdiv_fabia_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); @@ -1833,7 +1848,7 @@ const struct clk_ops clk_alpha_pll_trion_ops =3D { .disable =3D clk_trion_pll_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D alpha_pll_trion_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); @@ -1844,14 +1859,14 @@ const struct clk_ops clk_alpha_pll_lucid_ops =3D { .disable =3D clk_trion_pll_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D alpha_pll_trion_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); =20 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops =3D { .recalc_rate =3D clk_alpha_pll_postdiv_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_postdiv_fabia_round_rate, + .determine_rate =3D clk_alpha_pll_postdiv_fabia_determine_rate, .set_rate =3D clk_alpha_pll_postdiv_fabia_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); @@ -1903,7 +1918,7 @@ const struct clk_ops clk_alpha_pll_agera_ops =3D { .disable =3D clk_alpha_pll_disable, .is_enabled =3D clk_alpha_pll_is_enabled, .recalc_rate =3D alpha_pll_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D clk_alpha_pll_agera_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); @@ -2119,7 +2134,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops =3D= { .disable =3D alpha_pll_lucid_5lpe_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D alpha_pll_lucid_5lpe_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); @@ -2129,13 +2144,13 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe= _ops =3D { .disable =3D alpha_pll_lucid_5lpe_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); =20 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops =3D { .recalc_rate =3D clk_alpha_pll_postdiv_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_postdiv_fabia_round_rate, + .determine_rate =3D clk_alpha_pll_postdiv_fabia_determine_rate, .set_rate =3D clk_lucid_5lpe_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); @@ -2304,7 +2319,7 @@ const struct clk_ops clk_alpha_pll_zonda_ops =3D { .disable =3D clk_zonda_pll_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_trion_pll_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D clk_zonda_pll_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); @@ -2529,13 +2544,13 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_evo_= ops =3D { .disable =3D alpha_pll_lucid_evo_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D alpha_pll_lucid_evo_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); =20 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops =3D { .recalc_rate =3D clk_alpha_pll_postdiv_fabia_recalc_rate, - .round_rate =3D clk_alpha_pll_postdiv_fabia_round_rate, + .determine_rate =3D clk_alpha_pll_postdiv_fabia_determine_rate, .set_rate =3D clk_lucid_evo_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); @@ -2546,7 +2561,7 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops =3D { .disable =3D alpha_pll_lucid_evo_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D alpha_pll_lucid_evo_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D alpha_pll_lucid_5lpe_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); @@ -2557,7 +2572,7 @@ const struct clk_ops clk_alpha_pll_reset_lucid_evo_op= s =3D { .disable =3D alpha_pll_reset_lucid_evo_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D alpha_pll_lucid_evo_recalc_rate, - .round_rate =3D clk_alpha_pll_round_rate, + .determine_rate =3D clk_alpha_pll_determine_rate, .set_rate =3D alpha_pll_lucid_5lpe_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); @@ -2732,22 +2747,25 @@ static unsigned long clk_rivian_evo_pll_recalc_rate= (struct clk_hw *hw, return parent_rate * l; } =20 -static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long= rate, - unsigned long *prate) +static int clk_rivian_evo_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); unsigned long min_freq, max_freq; u32 l; u64 a; =20 - rate =3D alpha_pll_round_rate(rate, *prate, &l, &a, 0); - if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) - return rate; + req->rate =3D alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, + &a, 0); + if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) + return 0; =20 min_freq =3D pll->vco_table[0].min_freq; max_freq =3D pll->vco_table[pll->num_vco - 1].max_freq; =20 - return clamp(rate, min_freq, max_freq); + req->rate =3D clamp(req->rate, min_freq, max_freq); + + return 0; } =20 const struct clk_ops clk_alpha_pll_rivian_evo_ops =3D { @@ -2755,7 +2773,7 @@ const struct clk_ops clk_alpha_pll_rivian_evo_ops =3D= { .disable =3D alpha_pll_lucid_5lpe_disable, .is_enabled =3D clk_trion_pll_is_enabled, .recalc_rate =3D clk_rivian_evo_pll_recalc_rate, - .round_rate =3D clk_rivian_evo_pll_round_rate, + .determine_rate =3D clk_rivian_evo_pll_determine_rate, }; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70e6264141asm5588696d6.65.2025.08.28.17.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 17:38:43 -0700 (PDT) From: Brian Masney Date: Thu, 28 Aug 2025 20:38:22 -0400 Subject: [PATCH 3/8] clk: rockchip: half-divider: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-clk-round-rate-v2-v1-3-b97ec8ba6cc4@redhat.com> References: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> In-Reply-To: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> To: Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Piotr Wojtaszczyk , Chen Wang , Inochi Amaoto , Michal Simek , Bjorn Andersson , Heiko Stuebner , Andrea della Porta , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756427914; l=1835; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=lRErUXfhlVyOjMePggfg3EacyZAvSvm+w3vZGvHjG+s=; b=77L/EGAGdRYd5Zfk7wMZPiUoUyEJ+wFGI5TKO4e9gl+bXy3dLwkQMeaRO1HRElJrc9TAOKFe/ f1vZeXk72u/BkLnWKmAly+0tQG9J1VwJ/BPTEXNwrw7PqrQdgLjH3+M X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/clk/rockchip/clk-half-divider.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip= /clk-half-divider.c index 64f7faad2148f27099d1ace36da45207e2315a1c..fbc018e8afa44c87a5a7b53475f= c98b318ce1ec8 100644 --- a/drivers/clk/rockchip/clk-half-divider.c +++ b/drivers/clk/rockchip/clk-half-divider.c @@ -92,17 +92,19 @@ static int clk_half_divider_bestdiv(struct clk_hw *hw, = unsigned long rate, return bestdiv; } =20 -static long clk_half_divider_round_rate(struct clk_hw *hw, unsigned long r= ate, - unsigned long *prate) +static int clk_half_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_divider *divider =3D to_clk_divider(hw); int div; =20 - div =3D clk_half_divider_bestdiv(hw, rate, prate, + div =3D clk_half_divider_bestdiv(hw, req->rate, &req->best_parent_rate, divider->width, divider->flags); =20 - return DIV_ROUND_UP_ULL(((u64)*prate * 2), div * 2 + 3); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70e6264141asm5588696d6.65.2025.08.28.17.38.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 17:38:46 -0700 (PDT) From: Brian Masney Date: Thu, 28 Aug 2025 20:38:23 -0400 Subject: [PATCH 4/8] clk: rp1: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-clk-round-rate-v2-v1-4-b97ec8ba6cc4@redhat.com> References: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> In-Reply-To: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> To: Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Piotr Wojtaszczyk , Chen Wang , Inochi Amaoto , Michal Simek , Bjorn Andersson , Heiko Stuebner , Andrea della Porta , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756427914; l=5547; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=77mT8lxlHfMf8DpsPLJTC4LdP2OKAfcaRTXAq7sQvCc=; b=3gMx5iuOgrCwNi+DCXX7JQxOvLwFiVApn+7Bvb0HH6OCc8cBz7oI4PL5ZGPz6XlAL7fZhaSTw 0t/u6mMD55zBBJ4Vh8Qfol7XUf066XGn9A4V2i5zqigVDsEhG7+J6Un X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/clk/clk-rp1.c | 58 +++++++++++++++++++++++++++++------------------= ---- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/drivers/clk/clk-rp1.c b/drivers/clk/clk-rp1.c index e8f264d7f34e42f7186dbba31e5ace95d67b9a7d..fd144755b879862612ea5e22e91= 3dbb44a140033 100644 --- a/drivers/clk/clk-rp1.c +++ b/drivers/clk/clk-rp1.c @@ -532,13 +532,16 @@ static unsigned long rp1_pll_core_recalc_rate(struct = clk_hw *hw, return calc_rate; } =20 -static long rp1_pll_core_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int rp1_pll_core_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { u32 fbdiv_int, fbdiv_frac; =20 - return get_pll_core_divider(hw, rate, *parent_rate, - &fbdiv_int, &fbdiv_frac); + req->rate =3D get_pll_core_divider(hw, req->rate, req->best_parent_rate, + &fbdiv_int, + &fbdiv_frac); + + return 0; } =20 static void get_pll_prim_dividers(unsigned long rate, unsigned long parent= _rate, @@ -616,18 +619,20 @@ static unsigned long rp1_pll_recalc_rate(struct clk_h= w *hw, return DIV_ROUND_CLOSEST(parent_rate, prim_div1 * prim_div2); } =20 -static long rp1_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int rp1_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_hw *clk_audio_hw =3D &clk_audio->hw; u32 div1, div2; =20 - if (hw =3D=3D clk_audio_hw && clk_audio->cached_rate =3D=3D rate) - *parent_rate =3D clk_audio_core->cached_rate; + if (hw =3D=3D clk_audio_hw && clk_audio->cached_rate =3D=3D req->rate) + req->best_parent_rate =3D clk_audio_core->cached_rate; + + get_pll_prim_dividers(req->rate, req->best_parent_rate, &div1, &div2); =20 - get_pll_prim_dividers(rate, *parent_rate, &div1, &div2); + req->rate =3D DIV_ROUND_CLOSEST(req->best_parent_rate, div1 * div2); =20 - return DIV_ROUND_CLOSEST(*parent_rate, div1 * div2); + return 0; } =20 static int rp1_pll_ph_is_on(struct clk_hw *hw) @@ -677,13 +682,15 @@ static unsigned long rp1_pll_ph_recalc_rate(struct cl= k_hw *hw, return parent_rate / data->fixed_divider; } =20 -static long rp1_pll_ph_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int rp1_pll_ph_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct rp1_clk_desc *pll_ph =3D container_of(hw, struct rp1_clk_desc, hw); const struct rp1_pll_ph_data *data =3D pll_ph->data; =20 - return *parent_rate / data->fixed_divider; + req->rate =3D req->best_parent_rate / data->fixed_divider; + + return 0; } =20 static int rp1_pll_divider_is_on(struct clk_hw *hw) @@ -760,11 +767,12 @@ static unsigned long rp1_pll_divider_recalc_rate(stru= ct clk_hw *hw, return clk_divider_ops.recalc_rate(hw, parent_rate); } =20 -static long rp1_pll_divider_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *parent_rate) +static int rp1_pll_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - return clk_divider_ops.round_rate(hw, rate, parent_rate); + req->rate =3D clk_divider_ops.determine_rate(hw, req); + + return 0; } =20 static int rp1_clock_is_on(struct clk_hw *hw) @@ -1166,10 +1174,10 @@ static unsigned long rp1_varsrc_recalc_rate(struct = clk_hw *hw, return clock->cached_rate; } =20 -static long rp1_varsrc_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int rp1_varsrc_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - return rate; + return 0; } =20 static const struct clk_ops rp1_pll_core_ops =3D { @@ -1178,13 +1186,13 @@ static const struct clk_ops rp1_pll_core_ops =3D { .unprepare =3D rp1_pll_core_off, .set_rate =3D rp1_pll_core_set_rate, .recalc_rate =3D rp1_pll_core_recalc_rate, - .round_rate =3D rp1_pll_core_round_rate, + .determine_rate =3D rp1_pll_core_determine_rate, }; =20 static const struct clk_ops rp1_pll_ops =3D { .set_rate =3D rp1_pll_set_rate, .recalc_rate =3D rp1_pll_recalc_rate, - .round_rate =3D rp1_pll_round_rate, + .determine_rate =3D rp1_pll_determine_rate, }; =20 static const struct clk_ops rp1_pll_ph_ops =3D { @@ -1192,7 +1200,7 @@ static const struct clk_ops rp1_pll_ph_ops =3D { .prepare =3D rp1_pll_ph_on, .unprepare =3D rp1_pll_ph_off, .recalc_rate =3D rp1_pll_ph_recalc_rate, - .round_rate =3D rp1_pll_ph_round_rate, + .determine_rate =3D rp1_pll_ph_determine_rate, }; =20 static const struct clk_ops rp1_pll_divider_ops =3D { @@ -1201,7 +1209,7 @@ static const struct clk_ops rp1_pll_divider_ops =3D { .unprepare =3D rp1_pll_divider_off, .set_rate =3D rp1_pll_divider_set_rate, .recalc_rate =3D rp1_pll_divider_recalc_rate, - .round_rate =3D rp1_pll_divider_round_rate, + .determine_rate =3D rp1_pll_divider_determine_rate, }; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70e6264141asm5588696d6.65.2025.08.28.17.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 17:38:48 -0700 (PDT) From: Brian Masney Date: Thu, 28 Aug 2025 20:38:24 -0400 Subject: [PATCH 5/8] clk: sophgo: sg2042-clkgen: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-clk-round-rate-v2-v1-5-b97ec8ba6cc4@redhat.com> References: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> In-Reply-To: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> To: Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Piotr Wojtaszczyk , Chen Wang , Inochi Amaoto , Michal Simek , Bjorn Andersson , Heiko Stuebner , Andrea della Porta , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756427914; l=2463; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=sqQ9Idu7LND8TQvnc9CGktCQVk853FsqtiSZ1I4901o=; b=OqClB2gKvwUjzcBuWISxeT+XMsrr1fq+AKWaKypJZsPPPqcYnCjdJ8UA89aYPddHv0+EsQ93z FAS6xT63b+ACxX8kvKkjjNayIxis6/FhWL13CkGrP4I8GMEnTIJ9PfM X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Reviewed-by: Chen Wang Signed-off-by: Brian Masney --- drivers/clk/sophgo/clk-sg2042-clkgen.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/clk/sophgo/clk-sg2042-clkgen.c b/drivers/clk/sophgo/cl= k-sg2042-clkgen.c index 9e61288d34f3757315702c355f2669577b29676f..683661b71787c9e5428b168502f= 6fbb30ea9f7da 100644 --- a/drivers/clk/sophgo/clk-sg2042-clkgen.c +++ b/drivers/clk/sophgo/clk-sg2042-clkgen.c @@ -176,9 +176,8 @@ static unsigned long sg2042_clk_divider_recalc_rate(str= uct clk_hw *hw, return ret_rate; } =20 -static long sg2042_clk_divider_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *prate) +static int sg2042_clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct sg2042_divider_clock *divider =3D to_sg2042_clk_divider(hw); unsigned long ret_rate; @@ -192,15 +191,17 @@ static long sg2042_clk_divider_round_rate(struct clk_= hw *hw, bestdiv =3D readl(divider->reg) >> divider->shift; bestdiv &=3D clk_div_mask(divider->width); } - ret_rate =3D DIV_ROUND_UP_ULL((u64)*prate, bestdiv); + ret_rate =3D DIV_ROUND_UP_ULL((u64)req->best_parent_rate, bestdiv); } else { - ret_rate =3D divider_round_rate(hw, rate, prate, NULL, + ret_rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, N= ULL, divider->width, divider->div_flags); } =20 pr_debug("--> %s: divider_round_rate: val =3D %ld\n", clk_hw_get_name(hw), ret_rate); - return ret_rate; + req->rate =3D ret_rate; + + return 0; } =20 static int sg2042_clk_divider_set_rate(struct clk_hw *hw, @@ -258,13 +259,13 @@ static int sg2042_clk_divider_set_rate(struct clk_hw = *hw, =20 static const struct clk_ops sg2042_clk_divider_ops =3D { .recalc_rate =3D sg2042_clk_divider_recalc_rate, - .round_rate =3D sg2042_clk_divider_round_rate, + .determine_rate =3D sg2042_clk_divider_determine_rate, .set_rate =3D sg2042_clk_divider_set_rate, }; =20 static const struct clk_ops sg2042_clk_divider_ro_ops =3D { .recalc_rate =3D sg2042_clk_divider_recalc_rate, - .round_rate =3D sg2042_clk_divider_round_rate, + .determine_rate =3D sg2042_clk_divider_determine_rate, }; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70e6264141asm5588696d6.65.2025.08.28.17.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 17:38:51 -0700 (PDT) From: Brian Masney Date: Thu, 28 Aug 2025 20:38:25 -0400 Subject: [PATCH 6/8] clk: sophgo: sg2042-pll: remove round_rate() in favor of determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-clk-round-rate-v2-v1-6-b97ec8ba6cc4@redhat.com> References: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> In-Reply-To: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> To: Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Piotr Wojtaszczyk , Chen Wang , Inochi Amaoto , Michal Simek , Bjorn Andersson , Heiko Stuebner , Andrea della Porta , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756427914; l=2918; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=yQjDlKucQbDfv9rLtsx5KS2YxuVB1vqwKzuSAh7+mnM=; b=NIACu2uEJBGAECXwzUlTYQmeDeO89xJedpYWiz+3jVOZMhats8C5aEq2W9Xgn57Xm3aQE46TX bO0ZY19dAj/ACNhybTA+CdBVvm/B0H9sIJNyaJ+3B0kXEmy97yyk1w2 X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= This driver implements both the determine_rate() and round_rate() clk ops, and the round_rate() clk ops is deprecated. When both are defined, clk_core_determine_round_nolock() from the clk core will only use the determine_rate() clk ops, so let's remove the round_rate() clk ops since it's unused. The implementation of sg2042_clk_pll_determine_rate() calls sg2042_clk_pll_round_rate(), so this folds the two into a single function. Reviewed-by: Chen Wang Signed-off-by: Brian Masney --- drivers/clk/sophgo/clk-sg2042-pll.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/drivers/clk/sophgo/clk-sg2042-pll.c b/drivers/clk/sophgo/clk-s= g2042-pll.c index e5fb0bb7ac4f97616f3b472fcab45e5729eb653e..110b6ee06fe4b61e89f3cbf2ce0= 0eb03c078afb6 100644 --- a/drivers/clk/sophgo/clk-sg2042-pll.c +++ b/drivers/clk/sophgo/clk-sg2042-pll.c @@ -346,37 +346,30 @@ static unsigned long sg2042_clk_pll_recalc_rate(struc= t clk_hw *hw, return rate; } =20 -static long sg2042_clk_pll_round_rate(struct clk_hw *hw, - unsigned long req_rate, - unsigned long *prate) +static int sg2042_clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct sg2042_pll_ctrl pctrl_table; unsigned int value; long proper_rate; int ret; =20 - ret =3D sg2042_get_pll_ctl_setting(&pctrl_table, req_rate, *prate); + ret =3D sg2042_get_pll_ctl_setting(&pctrl_table, + min(req->rate, req->max_rate), + req->best_parent_rate); if (ret) { proper_rate =3D 0; goto out; } =20 value =3D sg2042_pll_ctrl_encode(&pctrl_table); - proper_rate =3D (long)sg2042_pll_recalc_rate(value, *prate); + proper_rate =3D (long)sg2042_pll_recalc_rate(value, req->best_parent_rate= ); =20 out: - pr_debug("--> %s: pll_round_rate: val =3D %ld\n", + pr_debug("--> %s: pll_determine_rate: val =3D %ld\n", clk_hw_get_name(hw), proper_rate); - return proper_rate; -} + req->rate =3D proper_rate; =20 -static int sg2042_clk_pll_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - req->rate =3D sg2042_clk_pll_round_rate(hw, min(req->rate, req->max_rate), - &req->best_parent_rate); - pr_debug("--> %s: pll_determine_rate: val =3D %ld\n", - clk_hw_get_name(hw), req->rate); return 0; } =20 @@ -417,14 +410,13 @@ static int sg2042_clk_pll_set_rate(struct clk_hw *hw, =20 static const struct clk_ops sg2042_clk_pll_ops =3D { .recalc_rate =3D sg2042_clk_pll_recalc_rate, - .round_rate =3D sg2042_clk_pll_round_rate, .determine_rate =3D sg2042_clk_pll_determine_rate, .set_rate =3D sg2042_clk_pll_set_rate, }; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70e6264141asm5588696d6.65.2025.08.28.17.38.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 17:38:53 -0700 (PDT) From: Brian Masney Date: Thu, 28 Aug 2025 20:38:26 -0400 Subject: [PATCH 7/8] clk: x86: cgu: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-clk-round-rate-v2-v1-7-b97ec8ba6cc4@redhat.com> References: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> In-Reply-To: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> To: Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Piotr Wojtaszczyk , Chen Wang , Inochi Amaoto , Michal Simek , Bjorn Andersson , Heiko Stuebner , Andrea della Porta , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756427914; l=3470; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=WJxAzEZ/y8gMiDjK9rGa4K/3JOojl4uHZ0X5uecFxfU=; b=FRh6Dtp6Qu3xMrqG77h69FKmubrcLmD1DaQdhlvkUw0E6UlxV5Rv3RQ4Eg7iODuTrLGqcr72p gQO+ywq9rn/BM+b5lX8Ga2Eu2EAvxju51YKn1XwPasJWhPgQyJz0Qba X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/clk/x86/clk-cgu.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c index 89b53f280aee03b7838e4656eae3571f00eaa263..d099667355f8d80785b0f43097a= d10c274dd61ea 100644 --- a/drivers/clk/x86/clk-cgu.c +++ b/drivers/clk/x86/clk-cgu.c @@ -132,14 +132,15 @@ lgm_clk_divider_recalc_rate(struct clk_hw *hw, unsign= ed long parent_rate) divider->flags, divider->width); } =20 -static long -lgm_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int lgm_clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct lgm_clk_divider *divider =3D to_lgm_clk_divider(hw); =20 - return divider_round_rate(hw, rate, prate, divider->table, - divider->width, divider->flags); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, d= ivider->table, + divider->width, divider->flags); + + return 0; } =20 static int @@ -182,7 +183,7 @@ static void lgm_clk_divider_disable(struct clk_hw *hw) =20 static const struct clk_ops lgm_clk_divider_ops =3D { .recalc_rate =3D lgm_clk_divider_recalc_rate, - .round_rate =3D lgm_clk_divider_round_rate, + .determine_rate =3D lgm_clk_divider_determine_rate, .set_rate =3D lgm_clk_divider_set_rate, .enable =3D lgm_clk_divider_enable, .disable =3D lgm_clk_divider_disable, @@ -487,15 +488,14 @@ lgm_clk_ddiv_set_rate(struct clk_hw *hw, unsigned lon= g rate, return 0; } =20 -static long -lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int lgm_clk_ddiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct lgm_clk_ddiv *ddiv =3D to_lgm_clk_ddiv(hw); u32 div, ddiv1, ddiv2; u64 rate64; =20 - div =3D DIV_ROUND_CLOSEST_ULL((u64)*prate, rate); + div =3D DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, req->rate); =20 /* if predivide bit is enabled, modify div by factor of 2.5 */ if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { @@ -503,14 +503,17 @@ lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned l= ong rate, div =3D DIV_ROUND_CLOSEST_ULL((u64)div, 5); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70e6264141asm5588696d6.65.2025.08.28.17.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 17:38:55 -0700 (PDT) From: Brian Masney Date: Thu, 28 Aug 2025 20:38:27 -0400 Subject: [PATCH 8/8] clk: zynqmp: divider: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250828-clk-round-rate-v2-v1-8-b97ec8ba6cc4@redhat.com> References: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> In-Reply-To: <20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com> To: Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Piotr Wojtaszczyk , Chen Wang , Inochi Amaoto , Michal Simek , Bjorn Andersson , Heiko Stuebner , Andrea della Porta , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756427914; l=2556; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=58n95bQC3o+Nb/L33jeFcmWnqEOz/8LpB+ZJ4315jbA=; b=uy+XUWiCv9yIjSAyrE0/4I1CLGHob+UIZ+EQxuc1qyVM5xq9Nhgg1+JCuBhoLqxMKDOrEirQl MnnF6BAHL2DDr0riIPtjEh4AcWFPyXh0pP1ewj5MPPjAgu3gyCxOVpL X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/clk/zynqmp/divider.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 5a00487ae408be4ffd586704859b232e934c1f6e..c824eeacd8ebd4d670d78f1af21= 86e61008bdae2 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -118,9 +118,8 @@ static unsigned long zynqmp_clk_divider_recalc_rate(str= uct clk_hw *hw, * * Return: 0 on success else error+reason */ -static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *prate) +static int zynqmp_clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct zynqmp_clk_divider *divider =3D to_zynqmp_clk_divider(hw); const char *clk_name =3D clk_hw_get_name(hw); @@ -145,17 +144,21 @@ static long zynqmp_clk_divider_round_rate(struct clk_= hw *hw, if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) bestdiv =3D 1 << bestdiv; =20 - return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); + req->rate =3D DIV_ROUND_UP_ULL((u64)req->best_parent_rate, bestdiv); + + return 0; } =20 width =3D fls(divider->max_div); =20 - rate =3D divider_round_rate(hw, rate, prate, NULL, width, divider->flags); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + NULL, width, divider->flags); =20 - if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (= rate % *prate)) - *prate =3D rate; + if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && + (req->rate % req->best_parent_rate)) + req->best_parent_rate =3D req->rate; =20 - return rate; + return 0; } =20 /** @@ -199,13 +202,13 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw = *hw, unsigned long rate, =20 static const struct clk_ops zynqmp_clk_divider_ops =3D { .recalc_rate =3D zynqmp_clk_divider_recalc_rate, - .round_rate =3D zynqmp_clk_divider_round_rate, + .determine_rate =3D zynqmp_clk_divider_determine_rate, .set_rate =3D zynqmp_clk_divider_set_rate, }; =20 static const struct clk_ops zynqmp_clk_divider_ro_ops =3D { .recalc_rate =3D zynqmp_clk_divider_recalc_rate, - .round_rate =3D zynqmp_clk_divider_round_rate, + .determine_rate =3D zynqmp_clk_divider_determine_rate, }; =20 /** --=20 2.50.1