From nobody Fri Oct 3 16:47:19 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E306224B05 for ; Wed, 27 Aug 2025 14:55:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756306545; cv=none; b=inSLRG+59QQQzhqzUv2exjBTA1kc7jcr/vfhG/npm8DmpV5sexYc9E0025kCXlOWDIsxSX7QH8caIHtculMcp3qmzBmB4bDF6gAWPkTO8zolfgkCqqSnPO0SDCgpZmyak+cbs+q44+mrHCbD9np85i4m8DEI7ytQwEJcA5NG11g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756306545; c=relaxed/simple; bh=RASQzDEjrALc3K/YuT5UvThKt2BVAZIxpTZ+5exrzzU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=huijDajygnDPIngf5E8XKJBVDM65v1kZcfbc49UcO6tsJkc4Jd3gTwybAl27Cculsxv2G3VDE0f5rdED9TF0zBx7C+D2j//wVPF+sLdAOIG7eT8cLrz3nV8EC4bWiHrNCHZRjOLQUNY+bzszXIkrZ6rWptGy8zEGdnbwoSbx+YU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=GCh0mveR; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="GCh0mveR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1756306544; x=1787842544; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RASQzDEjrALc3K/YuT5UvThKt2BVAZIxpTZ+5exrzzU=; b=GCh0mveRmFhwL3Mt3E4lNTM8HztRQGc33ECG/JteXucpMaNg++xmlTs5 Lm3HEUiPF4hSpLJwwmI4rkckmFLW6wTkwM/dJpbL2s8yOm+8BqbjYfUTz cd5PVGlPnCTlv/7OTQcT2ePBByHLJyHrWdahdXMjSpTtTLteuoD9TyRuE jhXt9E9i9EB777oLrBLSUDOFFl05EQ8YEUAOUIqBukMiQZ4ENZ0gHd/fM YHrwVEbku0AahoEFUIian4vjcIVFA65PzD5HDrK2s/IR9G+G4HakYXMfZ yETv1Y3rgY3GZ+yyH06A+cumcLdjbsDXpxZDBl2JazTiH/L53tIXLfH4w Q==; X-CSE-ConnectionGUID: qmQ3gJioTdWJF8Sch/45rg== X-CSE-MsgGUID: FPpwuLK0SzS4wq4WK45RWQ== X-IronPort-AV: E=Sophos;i="6.18,214,1751266800"; d="scan'208";a="213136671" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 27 Aug 2025 07:55:43 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 27 Aug 2025 07:54:39 -0700 Received: from ROU-LL-M43238.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 27 Aug 2025 07:54:37 -0700 From: To: ARM Maintainers , Alexandre Belloni , Ryan Wanner , Varshini Rajendran , Claudiu Beznea CC: , , Nicolas Ferre Subject: [PATCH 1/3] ARM: at91: pm: fix .uhp_udp_mask specification for current SoCs Date: Wed, 27 Aug 2025 16:54:25 +0200 Message-ID: <20250827145427.46819-2-nicolas.ferre@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250827145427.46819-1-nicolas.ferre@microchip.com> References: <20250827145427.46819-1-nicolas.ferre@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolas Ferre All SoCs using this structure field .uhp_udp_mask in configuration index 4 don't have the bit 7 specified: sam9x60 nor sam9x75. Remove this bit from the mask definition to match register layout. This mask is used in function at91_pm_verify_clocks(). Signed-off-by: Nicolas Ferre Reviewed-by: Alexandre Belloni --- arch/arm/mach-at91/pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 3aa20038ad93..35058b99069c 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -1364,7 +1364,7 @@ static const struct pmc_info pmc_infos[] __initconst = =3D { .version =3D AT91_PMC_V1, }, { - .uhp_udp_mask =3D AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, + .uhp_udp_mask =3D AT91SAM926x_PMC_UHP, .mckr =3D 0x28, .version =3D AT91_PMC_V2, }, --=20 2.43.0 From nobody Fri Oct 3 16:47:19 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE98C224893 for ; Wed, 27 Aug 2025 14:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756306521; cv=none; b=O6MBvRFyD6kg+jOTEY8eKaiWlKQMHmvSP5z8btgmxu7iEDehFRYPpD7r3ZUXJiJLVHN9wUMynELuVKAISUMoJX7dWV1SEDdoEvp/Bl8TO9OOx/b6qJAwul3EobW+tz+m0e7IVMGLvTvQV7E4rEE0r1mraqU8lGNDjoti5gh8qGI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756306521; c=relaxed/simple; bh=uwD7I3Vk5NcXfozUcavy0K+Nxxxwd8y/BEigyn9nl4g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qCo/UAZ9eg4Y1f+Wcp+vHeDSdoxaFE6rUsJbY+VA+qfViZ5lA3wfHtN3H+2OA4JiKtMbLGjcfP1pLptchkhdsHZ9CMPUXhjF3GvYde6NAvfWDneQl18DTNMfo8Dyz5XTsp/DEBPJ1hgsl34Ux2mCxH6DI9DOlMsBObpreFppxr8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=u8Pe1lK+; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="u8Pe1lK+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1756306519; x=1787842519; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uwD7I3Vk5NcXfozUcavy0K+Nxxxwd8y/BEigyn9nl4g=; b=u8Pe1lK+xNpWS/UOpJsbS7lERhunHAhXyxYKt/Zrk7p99gXxJGaD9MEG GZiDizV2AzIL4RIBLm66+sFORhFgN1nx94iRbtleFQbYTvb9pPh/LrZAz BR3fmdvWy9dEbZ1Ihy92vBhmWUHtDsukpZlstYQsf8d2Z6ztSHhRLSWGG VL+4zA+wvhUR0byOqqGNHvz++3ErQ0XKVgGYjh4DeVpW3R5e6ylHC3wmu Ae90W+OFN5lfQPxeUKup9XQtTJgDZP0k/L2EWNQDwHRJ2kaV2DvAZHZ7g bJ8p2J0ito543GvczgE9G88b5rw+qogvyxO/RH5/1dKYinGNY7VLGqLnr Q==; X-CSE-ConnectionGUID: 4yuHX6b1S/u7TSh6v5Gw7g== X-CSE-MsgGUID: tIBq8RwESmygDYS25zfFeQ== X-IronPort-AV: E=Sophos;i="6.18,214,1751266800"; d="scan'208";a="46291226" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 27 Aug 2025 07:55:13 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 27 Aug 2025 07:54:42 -0700 Received: from ROU-LL-M43238.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 27 Aug 2025 07:54:40 -0700 From: To: ARM Maintainers , Alexandre Belloni , Ryan Wanner , Varshini Rajendran , Claudiu Beznea CC: , , Nicolas Ferre Subject: [PATCH 2/3] ARM: at91: pm: fix MCKx restore routine Date: Wed, 27 Aug 2025 16:54:26 +0200 Message-ID: <20250827145427.46819-3-nicolas.ferre@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250827145427.46819-1-nicolas.ferre@microchip.com> References: <20250827145427.46819-1-nicolas.ferre@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolas Ferre The at91_mckx_ps_restore() assembly function is responsible for setting back MCKx system bus clocks after exiting low power modes. Fix a typo and use tmp3 variable instead of tmp2 to correctly set MCKx to previously saved sate. Tmp2 was used without the needed changes in CSS and DIV. Moreover the required bit 7, telling that MCR register's content is to be changed (CMD/write), was not set. Fix function comment to match tmp variables actually used. Signed-off-by: Nicolas Ferre Fixes: 28eb1d40fe57 ("ARM: at91: pm: add support for MCK1..4 save/restore f= or ulp modes") Reviewed-by: Alexandre Belloni --- arch/arm/mach-at91/pm_suspend.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspen= d.S index e23b86834096..7e6c94f8edee 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -904,7 +904,7 @@ e_done: /** * at91_mckx_ps_restore: restore MCKx settings * - * Side effects: overwrites tmp1, tmp2 + * Side effects: overwrites tmp1, tmp2 and tmp3 */ .macro at91_mckx_ps_restore #ifdef CONFIG_SOC_SAMA7 @@ -980,7 +980,7 @@ r_ps: bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK orr tmp3, tmp3, tmp1 orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD - str tmp2, [pmc, #AT91_PMC_MCR_V2] + str tmp3, [pmc, #AT91_PMC_MCR_V2] =20 wait_mckrdy tmp1 =20 --=20 2.43.0 From nobody Fri Oct 3 16:47:19 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98BD522541B for ; Wed, 27 Aug 2025 14:55:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756306524; cv=none; b=AyYu5yvWnDLf/lKeKKOCT9+2U+0WzJOcC/29HVNKy1AVKxph581kFdntXRIakhCYoI82mAnR2U61r0X6xhx9hfPZHvH9utb5C38bMMD5rjzuwi415gV3867wp7iDiJObdCTBuuZDoUl6l8xPYhbEjv0ADN2TrabIyp1dfXtyQlA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756306524; c=relaxed/simple; bh=VVTD+gRkSYL1zFC/AuUFrbB6yo9BKBx9w+JU2+HE7nE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RkrrCA7xsJVxzlUQS4uGgM3Ip3vX+1TiIkNTdeEt1pJ5/76I6RXL8DzG+OAcsODGZ29qdJ+ATxTq3Y0etxTQdVcgnTQXKQWiUZuhrltuL2BY2D9zbhE1s8hvHXZfcqq/VjIjEBVXVBbDVr4j0soMleG9b/NDCMUwahtcp6X4K6c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=dXjBSr79; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="dXjBSr79" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1756306522; x=1787842522; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VVTD+gRkSYL1zFC/AuUFrbB6yo9BKBx9w+JU2+HE7nE=; b=dXjBSr79l1rg4y/PB85wHxPT8yWPjeLlhPs32jID3xeYn4W7YDzqFhVa p9AicCd4sa4b89FnPa5xJAmm2HaqtXZFxYy58cbxgmiITdM2kke1ny3C9 zQUOm4eJgTO8gH6SrzSMBIA9lEclUDJ54WZD/Id43yeVDyjP49KvzdnZH 3eYZgJG4MH7hVEMUQZZ7rs0lGntuEndd/96pJ+3yKZlqfe8VbJcweaBXL uolHhzMyLuXmGJGisRLIymfcdVsJflTZensjPoPmAbb+KDo1VesFbOl89 WbpLPcJDlu9r0JHnkKfO1SS1xvJ8eCJCBHGf6J4twkcjyiHoN0TW4y2/m A==; X-CSE-ConnectionGUID: 4yuHX6b1S/u7TSh6v5Gw7g== X-CSE-MsgGUID: BUnd2GltR5uNF4z6Farg4g== X-IronPort-AV: E=Sophos;i="6.18,214,1751266800"; d="scan'208";a="46291227" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 27 Aug 2025 07:55:14 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 27 Aug 2025 07:54:44 -0700 Received: from ROU-LL-M43238.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Wed, 27 Aug 2025 07:54:42 -0700 From: To: ARM Maintainers , Alexandre Belloni , Ryan Wanner , Varshini Rajendran , Claudiu Beznea CC: , , Nicolas Ferre Subject: [PATCH 3/3] ARM: at91: pm: save and restore ACR during PLL disable/enable Date: Wed, 27 Aug 2025 16:54:27 +0200 Message-ID: <20250827145427.46819-4-nicolas.ferre@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250827145427.46819-1-nicolas.ferre@microchip.com> References: <20250827145427.46819-1-nicolas.ferre@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolas Ferre Add a new word in assembly to store ACR value during the calls to at91_plla_disable/at91_plla_enable macros and use it. Signed-off-by: Nicolas Ferre [cristian.birsan@microchip.com: remove ACR_DEFAULT_PLLA loading] Signed-off-by: Cristian Birsan Reviewed-by: Alexandre Belloni --- arch/arm/mach-at91/pm_suspend.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspen= d.S index 7e6c94f8edee..aad53ec9e957 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -689,6 +689,10 @@ sr_dis_exit: bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID str tmp2, [pmc, #AT91_PMC_PLL_UPDT] =20 + /* save acr */ + ldr tmp2, [pmc, #AT91_PMC_PLL_ACR] + str tmp2, .saved_acr + /* save div. */ mov tmp1, #0 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0] @@ -758,7 +762,7 @@ sr_dis_exit: str tmp1, [pmc, #AT91_PMC_PLL_UPDT] =20 /* step 2. */ - ldr tmp1, =3DAT91_PMC_PLL_ACR_DEFAULT_PLLA + ldr tmp1, .saved_acr str tmp1, [pmc, #AT91_PMC_PLL_ACR] =20 /* step 3. */ @@ -1207,6 +1211,8 @@ ENDPROC(at91_pm_suspend_in_sram) #endif .saved_mckr: .word 0 +.saved_acr: + .word 0 .saved_pllar: .word 0 .saved_sam9_lpr: --=20 2.43.0