From nobody Wed Oct 1 20:32:41 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32BF520B7EE; Wed, 27 Aug 2025 11:40:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756294818; cv=none; b=ILLwTO/UR0dJ0y9kZcGUl1NqzRscHEDSersIUS6Xvgaa45ikwkl51exU6gxKZqWSKMARKyh8fCXgG2lB8bLb9A5CVoypfgr5Zbz9BMOJxYmZTINvxkaIuukPMfnc71RaaGPkNIE0M85NFwtxo6ysGWXWJEQCGWhMXNNNs0EsuoQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756294818; c=relaxed/simple; bh=Qk9KPWQt4bTNmxVI3gWvhUd0hvWtSFEc7GzrMMxmdnI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jHY5Zlon3qxmMco6Ar+HeYCHwobFvkSW0WpWOMIuRMrhdUdTTVNCGLTp+htlInaJnnzHEJ/5mYi4TfvkRGd5IKR/S7GVEo9ksufHVaFhUHWnUpfxo0bhLQ+mdiKVJa0DGX6GGUwG7i8f/2t2QpQ4jGevS73li+ORlUx6SUYpwW8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=siJroKyw; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="siJroKyw" X-UUID: 968b11ae833a11f0b33aeb1e7f16c2b6-20250827 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VqzEUSqWA7sXTJW9bQVqniHpSO4Qo2zMHDCuhXD+LGU=; b=siJroKywMAdK+MX/qS5kLF8/W4v6GieM0KeUs1SsCas86tPRLFMtXNHcbWHiBn0kfwESaZcoH39BFvA9dvY+3EFBmILLt4IMaVoc+UN7NEpzoFd9PRp253T6Hl5k0b8yoJd0FFPHWhcGLDswUmmGwI1ecgWOqIsaz3vJ6DYO2t0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:dce32d61-288c-4654-88f2-f1c472444163,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:f1326cf,CLOUDID:69b6ec44-18c5-4075-a135-4c0afe29f9d6,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 968b11ae833a11f0b33aeb1e7f16c2b6-20250827 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1369436969; Wed, 27 Aug 2025 19:40:10 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Wed, 27 Aug 2025 19:40:09 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Wed, 27 Aug 2025 19:40:08 +0800 From: Jason-JH Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Mauro Carvalho Chehab CC: Matthias Brugger , Nicolas Dufresne , Jason-JH Lin , Nancy Lin , Singo Chang , Paul-PL Chen , Moudy Ho , Xiandong Wang , Sirius Wang , Fei Shao , Chen-yu Tsai , , , , , , , , CK Hu Subject: [PATCH v7 08/20] mailbox: mtk-cmdq: Add driver data to support for MT8196 Date: Wed, 27 Aug 2025 19:37:40 +0800 Message-ID: <20250827114006.3310175-9-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250827114006.3310175-1-jason-jh.lin@mediatek.com> References: <20250827114006.3310175-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" MT8196 has 2 new hardware configuration compared with the previous SoC, which correspond to the 2 new driver data: 1. mminfra_offset: For GCE data path control Since GCE has been moved into mminfra, GCE needs to append the mminfra offset to the DRAM address when accessing the DRAM. 2. gce_vm: For GCE hardware virtualization control Currently, the first version of the mt8196 mailbox controller only requires setting the VM-related registers to enable the permissions of a host VM. Signed-off-by: Jason-JH Lin Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 373effbcfa40..316082938977 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -848,6 +849,16 @@ static const struct gce_plat gce_plat_mt8195 =3D { .gce_num =3D 2 }; =20 +static const struct gce_plat gce_plat_mt8196 =3D { + .thread_nr =3D 32, + .shift =3D 3, + .mminfra_offset =3D SZ_2G, + .control_by_sw =3D true, + .sw_ddr_en =3D true, + .gce_vm =3D true, + .gce_num =3D 2 +}; + static const struct of_device_id cmdq_of_ids[] =3D { {.compatible =3D "mediatek,mt6779-gce", .data =3D (void *)&gce_plat_mt677= 9}, {.compatible =3D "mediatek,mt8173-gce", .data =3D (void *)&gce_plat_mt817= 3}, @@ -856,6 +867,7 @@ static const struct of_device_id cmdq_of_ids[] =3D { {.compatible =3D "mediatek,mt8188-gce", .data =3D (void *)&gce_plat_mt818= 8}, {.compatible =3D "mediatek,mt8192-gce", .data =3D (void *)&gce_plat_mt819= 2}, {.compatible =3D "mediatek,mt8195-gce", .data =3D (void *)&gce_plat_mt819= 5}, + {.compatible =3D "mediatek,mt8196-gce", .data =3D (void *)&gce_plat_mt819= 6}, {} }; MODULE_DEVICE_TABLE(of, cmdq_of_ids); --=20 2.43.0