From nobody Wed Oct 1 20:34:03 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A7343019B3; Wed, 27 Aug 2025 11:40:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756294823; cv=none; b=FXJgAMKeNCktUpH8v/QPv3QQAUpEvA0eUTc4cDW0u8zioA6RqiFKSsJyQgEZmMOx5LhAT/caixmkMRQNbj7p1lNAtBSnSQP672j1Kdh3eNxfVCOb/Pg9IuEvuw/CBhmx8TND++dAb7sKiJ+SKKILqCS6UEZP9NhZPsmTrxY6754= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756294823; c=relaxed/simple; bh=uGfACk4IlftmTwSKDAeValxyvgSZcqT4LA/Slx2Jn3Q=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=K/9wfzqvPs6dzUWsaQfnN0LFQAsBsg01aA/RZ+ehjiKzcFWmETyYXAAnfEqSUAwc4dz3STcbC1A7nxVNyMZ/1jedpZLieZpMRSpNM0URIAqqnkohNpuHfZAMgexpGPLx3UJQ6WoVVypE7+wtbeM7X0nzus2JGHRBC+mTZpuX2+I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=hXr4O5ee; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="hXr4O5ee" X-UUID: 97358fd0833a11f0b33aeb1e7f16c2b6-20250827 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=USMUmqnBToxLKxyts77YT9p/uApoAUGjthHOKAqxpj8=; b=hXr4O5eemF/Ws0WViLk0/1e+QFB452IGrNP7ef1AzGbgRqYtGYLbRTiKPondQBb4+m3SaYHcWAcfuC5HtILqysUlTQTvC5gddSVbbbWoFdPeV3me++aK8XiDLX4m1+nUtGGqXQ0zG26iqF25HdGFLblV/AUQ9R4V0USUuGdK+xg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:2f2cf2ce-bdac-4aab-9db0-c26588bb9dd1,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:f1326cf,CLOUDID:85b6ec44-18c5-4075-a135-4c0afe29f9d6,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 97358fd0833a11f0b33aeb1e7f16c2b6-20250827 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1822932663; Wed, 27 Aug 2025 19:40:11 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Wed, 27 Aug 2025 19:40:09 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Wed, 27 Aug 2025 19:40:09 +0800 From: Jason-JH Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Mauro Carvalho Chehab CC: Matthias Brugger , Nicolas Dufresne , Jason-JH Lin , Nancy Lin , Singo Chang , Paul-PL Chen , Moudy Ho , Xiandong Wang , Sirius Wang , Fei Shao , Chen-yu Tsai , , , , , , , Subject: [PATCH v7 11/20] soc: mediatek: mtk-cmdq: Add mminfra_offset adjustment for DRAM addresses Date: Wed, 27 Aug 2025 19:37:43 +0800 Message-ID: <20250827114006.3310175-12-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250827114006.3310175-1-jason-jh.lin@mediatek.com> References: <20250827114006.3310175-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Since GCE has been moved to MMINFRA in MT8196, all transactions from MMINFRA to DRAM will have their addresses adjusted by subtracting a mminfra_offset. Therefore, the CMDQ helper driver needs to get the mminfra_offset value of the SoC from cmdq_mbox_priv of cmdq_pkt and then add it to the DRAM address when generating instructions to ensure GCE accesses the correct DRAM address. CMDQ users can then call CMDQ helper APIs as usual. Signed-off-by: Jason-JH Lin --- drivers/soc/mediatek/mtk-cmdq-helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/= mtk-cmdq-helper.c index 7e86299213d8..ced798e8d6b4 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -358,6 +358,7 @@ int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t = src_addr, dma_addr_t dst_ int ret; =20 /* read the value of src_addr into high_addr_reg_idx */ + src_addr +=3D pkt->priv.mminfra_offset; ret =3D cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(src_addr)); if (ret < 0) return ret; @@ -366,6 +367,7 @@ int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t = src_addr, dma_addr_t dst_ return ret; =20 /* write the value of value_reg_idx into dst_addr */ + dst_addr +=3D pkt->priv.mminfra_offset; ret =3D cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(dst_addr)); if (ret < 0) return ret; @@ -491,7 +493,7 @@ int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t= addr, u32 value, u32 mas inst.op =3D CMDQ_CODE_MASK; inst.dst_t =3D CMDQ_REG_TYPE; inst.sop =3D CMDQ_POLL_ADDR_GPR; - inst.value =3D addr; + inst.value =3D addr + pkt->priv.mminfra_offset; ret =3D cmdq_pkt_append_command(pkt, inst); if (ret < 0) return ret; @@ -551,7 +553,7 @@ int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t = addr, u8 shift_pa) struct cmdq_instruction inst =3D { .op =3D CMDQ_CODE_JUMP, .offset =3D CMDQ_JUMP_ABSOLUTE, - .value =3D addr >> shift_pa + .value =3D (addr + pkt->priv.mminfra_offset) >> pkt->priv.shift_pa }; return cmdq_pkt_append_command(pkt, inst); } --=20 2.43.0