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Wed, 27 Aug 2025 03:10:38 -0700 (PDT) From: Yunhui Cui To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, atish.patra@linux.dev, anup@brainfault.org, will@kernel.org, mark.rutland@arm.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, catalin.marinas@arm.com, masahiroy@kernel.org, suzuki.poulose@arm.com, cuiyunhui@bytedance.com, maz@kernel.org, zhanjie9@hisilicon.com, yangyicong@hisilicon.com, dianders@chromium.org, mingo@kernel.org, lihuafei1@huawei.com, akpm@linux-foundation.org, jpoimboe@kernel.org, rppt@kernel.org, kees@kernel.org, thomas.weissschuh@linutronix.de Subject: [PATCH 2/2] riscv: add HARDLOCKUP_DETECTOR_PERF support Date: Wed, 27 Aug 2025 18:09:59 +0800 Message-Id: <20250827100959.83023-3-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20250827100959.83023-1-cuiyunhui@bytedance.com> References: <20250827100959.83023-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reuse watchdog_hld.c to enable HARDLOCKUP_DETECTOR_PERF and add Kconfig selections for RISC-V. Signed-off-by: Yunhui Cui --- arch/riscv/Kconfig | 3 +++ drivers/perf/riscv_pmu_sbi.c | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 451eb23d86c96..214b1ead5781a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -184,6 +184,9 @@ config RISCV select HAVE_PAGE_SIZE_4KB select HAVE_PCI select HAVE_PERF_EVENTS + select PERF_EVENTS + select HAVE_PERF_EVENTS_NMI if RISCV_SSE && RISCV_PMU_SSE + select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_N= MI select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP select HAVE_POSIX_CPU_TIMERS_TASK_WORK diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8c1ac7985df6c..c5423a046d016 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -22,6 +22,7 @@ #include #include #include +#include =20 #include #include @@ -1102,6 +1103,11 @@ static int pmu_sbi_setup_sse(struct riscv_pmu *pmu) } #endif =20 +bool arch_pmu_irq_is_nmi(void) +{ + return IS_ENABLED(CONFIG_RISCV_PMU_SSE); +} + static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) { struct riscv_pmu *pmu =3D hlist_entry_safe(node, struct riscv_pmu, node); @@ -1525,6 +1531,8 @@ static int __init pmu_sbi_devinit(void) /* Notify legacy implementation that SBI pmu is available*/ riscv_pmu_legacy_skip_init(); =20 + lockup_detector_retry_init(); + return ret; } device_initcall(pmu_sbi_devinit) --=20 2.39.5