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Wed, 27 Aug 2025 02:42:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG1PEPF000082E3.mail.protection.outlook.com (10.167.240.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9073.11 via Frontend Transport; Wed, 27 Aug 2025 02:42:23 +0000 Received: from localhost.localdomain (unknown [172.16.64.196]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id F0B4241C0148; Wed, 27 Aug 2025 10:42:22 +0800 (CST) From: Gary Yang To: linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, Gary Yang Subject: [PATCH 1/3] pinctrl: cix: Add pin-controller support for sky1 Date: Wed, 27 Aug 2025 10:42:20 +0800 Message-ID: <20250827024222.588082-2-gary.yang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250827024222.588082-1-gary.yang@cixtech.com> References: <20250827024222.588082-1-gary.yang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E3:EE_|JH0PR06MB6630:EE_ X-MS-Office365-Filtering-Correlation-Id: 18eacf9a-a388-44cf-2312-08dde5135a46 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 02:42:23.6547 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18eacf9a-a388-44cf-2312-08dde5135a46 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E3.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: JH0PR06MB6630 Content-Type: text/plain; charset="utf-8" Add the pin-controller driver for Sky1 platform Signed-off-by: Gary Yang --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/cix/Kconfig | 14 + drivers/pinctrl/cix/Makefile | 4 + drivers/pinctrl/cix/pinctrl-sky1-base.c | 622 ++++++++++++++++++++++++ drivers/pinctrl/cix/pinctrl-sky1.c | 502 +++++++++++++++++++ drivers/pinctrl/cix/pinctrl-sky1.h | 55 +++ 7 files changed, 1199 insertions(+) create mode 100644 drivers/pinctrl/cix/Kconfig create mode 100644 drivers/pinctrl/cix/Makefile create mode 100644 drivers/pinctrl/cix/pinctrl-sky1-base.c create mode 100644 drivers/pinctrl/cix/pinctrl-sky1.c create mode 100644 drivers/pinctrl/cix/pinctrl-sky1.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index ddd11668457c..a5b7177be115 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -653,6 +653,7 @@ source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/cirrus/Kconfig" +source "drivers/pinctrl/cix/Kconfig" source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 909ab89a56d2..8f353fc38e0e 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_ARCH_ASPEED) +=3D aspeed/ obj-y +=3D bcm/ obj-$(CONFIG_PINCTRL_BERLIN) +=3D berlin/ obj-y +=3D cirrus/ +obj-y +=3D cix/ obj-y +=3D freescale/ obj-$(CONFIG_X86) +=3D intel/ obj-y +=3D mediatek/ diff --git a/drivers/pinctrl/cix/Kconfig b/drivers/pinctrl/cix/Kconfig new file mode 100644 index 000000000000..42e064b6e7a2 --- /dev/null +++ b/drivers/pinctrl/cix/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +config PINCTRL_SKY1_BASE + tristate + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select REGMAP + +config PINCTRL_SKY1 + tristate "Cix Sky1 pinctrl driver" + depends on ARCH_CIX + select PINCTRL_SKY1_BASE + help + Say Y here to enable the sky1 pinctrl driver diff --git a/drivers/pinctrl/cix/Makefile b/drivers/pinctrl/cix/Makefile new file mode 100644 index 000000000000..22685d6a107b --- /dev/null +++ b/drivers/pinctrl/cix/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Cix Sky1 pin control drivers +obj-$(CONFIG_PINCTRL_SKY1_BASE) +=3D pinctrl-sky1-base.o +obj-$(CONFIG_PINCTRL_SKY1) +=3D pinctrl-sky1.o diff --git a/drivers/pinctrl/cix/pinctrl-sky1-base.c b/drivers/pinctrl/cix/= pinctrl-sky1-base.c new file mode 100644 index 000000000000..a80c68fdadfc --- /dev/null +++ b/drivers/pinctrl/cix/pinctrl-sky1-base.c @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Author: Jerry Zhu + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinconf.h" +#include "../pinmux.h" +#include "pinctrl-sky1.h" + +#define SKY1_PIN_SIZE (0xc) +#define SKY1_MUX_MASK (0x180L) +#define SKY1_CONF_MASK (0x7fL) +#define PADS_FUNCS_MASK (0x3) +#define PADS_FUNCS_BITS (0x7) +#define PADS_CONFS_MASK (0x7f) + +static inline const struct group_desc *sky1_pinctrl_find_group_by_name( + struct pinctrl_dev *pctldev, + const char *name) +{ + const struct group_desc *grp =3D NULL; + int i; + + for (i =3D 0; i < pctldev->num_groups; i++) { + grp =3D pinctrl_generic_get_group(pctldev, i); + if (grp && !strcmp(grp->grp.name, name)) + break; + } + + return grp; +} + +static void sky1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file= *s, + unsigned int offset) +{ + seq_printf(s, "%s", dev_name(pctldev->dev)); +} + +static int sky1_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, unsigned int *num_maps) +{ + struct sky1_pinctrl *spctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *grp; + struct pinctrl_map *new_map; + struct device_node *parent; + struct sky1_pin *pin; + int map_num =3D 1; + int i, j; + + /* + * first find the group of this node and check if we need create + * config maps for pins + */ + grp =3D sky1_pinctrl_find_group_by_name(pctldev, np->name); + if (!grp) { + dev_err(spctl->dev, "unable to find group for node %pOFn\n", np); + return -EINVAL; + } + + map_num +=3D grp->grp.npins; + + new_map =3D kmalloc_array(map_num, sizeof(struct pinctrl_map), + GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + *map =3D new_map; + *num_maps =3D map_num; + + /* create mux map */ + parent =3D of_get_parent(np); + if (!parent) { + kfree(new_map); + return -EINVAL; + } + new_map[0].type =3D PIN_MAP_TYPE_MUX_GROUP; + new_map[0].data.mux.function =3D parent->name; + new_map[0].data.mux.group =3D np->name; + of_node_put(parent); + + /* create config map */ + new_map++; + for (i =3D j =3D 0; i < grp->grp.npins; i++) { + pin =3D &((struct sky1_pin *)(grp->data))[i]; + + new_map[j].type =3D PIN_MAP_TYPE_CONFIGS_PIN; + new_map[j].data.configs.group_or_pin =3D + pin_get_name(pctldev, pin->offset/4); + new_map[j].data.configs.configs =3D &pin->configs; + new_map[j].data.configs.num_configs =3D 1; + + j++; + } + + dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", + (*map)->data.mux.function, (*map)->data.mux.group, map_num); + + return 0; +} + +static inline const char * +sky1_pinctrl_find_pin_group(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned int *pins_in, + size_t npins_in) +{ + int i, j; + int ret; + const char *const *groups; + unsigned int num_groups; + const unsigned int *pins; + unsigned int num_pins; + + ret =3D pinmux_generic_get_function_groups(pctldev, selector, &groups, + &num_groups); + for (i =3D 0; i < num_groups; i++) { + ret =3D pinctrl_get_group_pins(pctldev, groups[i], &pins, + &num_pins); + if (npins_in !=3D num_pins) + continue; + for (j =3D 0; j < num_pins; j++) { + if (pins[j] =3D=3D pins_in[0]) + return groups[i]; + } + } + return NULL; +} + +static void sky1_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops sky1_pctrl_ops =3D { + .get_groups_count =3D pinctrl_generic_get_group_count, + .get_group_name =3D pinctrl_generic_get_group_name, + .get_group_pins =3D pinctrl_generic_get_group_pins, + .pin_dbg_show =3D sky1_pin_dbg_show, + .dt_node_to_map =3D sky1_dt_node_to_map, + .dt_free_map =3D sky1_dt_free_map, +}; + +static int sky1_pmx_set_one_pin(struct sky1_pinctrl *spctl, + struct sky1_pin *pin) +{ + u32 reg_val; + u32 *pin_reg; + + pin_reg =3D spctl->base + pin->offset; + reg_val =3D readl(pin_reg); + reg_val &=3D ~SKY1_MUX_MASK; + reg_val |=3D pin->configs & SKY1_MUX_MASK; + writel(reg_val, pin_reg); + + dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n", + pin->offset, reg_val); + return 0; +} + +static int sky1_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned int group) +{ + struct sky1_pinctrl *spctl =3D pinctrl_dev_get_drvdata(pctldev); + struct function_desc *func; + struct group_desc *grp; + struct sky1_pin *pin; + unsigned int npins; + int i, err; + + /* + * Configure the mux mode for each pin in the group for a specific + * function. + */ + grp =3D pinctrl_generic_get_group(pctldev, group); + if (!grp) + return -EINVAL; + + func =3D pinmux_generic_get_function(pctldev, selector); + if (!func) + return -EINVAL; + + npins =3D grp->grp.npins; + + dev_dbg(spctl->dev, "enable function %s group %s\n", + func->func.name, grp->grp.name); + + for (i =3D 0; i < npins; i++) { + /* + * Config for Sky1 one pin + */ + pin =3D &((struct sky1_pin *)(grp->data))[i]; + err =3D sky1_pmx_set_one_pin(spctl, pin); + if (err) + return err; + } + + return 0; +} + +static const struct pinmux_ops sky1_pmx_ops =3D { + .get_functions_count =3D pinmux_generic_get_function_count, + .get_function_name =3D pinmux_generic_get_function_name, + .get_function_groups =3D pinmux_generic_get_function_groups, + .set_mux =3D sky1_pmx_set, +}; + +static int sky1_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct sky1_pinctrl *spctl =3D pinctrl_dev_get_drvdata(pctldev); + *config =3D readl(spctl->base + spctl->pin_regs[pin_id]); + + return 0; +} + +static int sky1_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *configs, + unsigned int num_configs) +{ + struct sky1_pinctrl *spctl =3D pinctrl_dev_get_drvdata(pctldev); + u32 reg_val; + u32 *pin_reg; + int i; + + pin_reg =3D spctl->base + spctl->pin_regs[pin_id]; + + for (i =3D 0; i < num_configs; i++) { + reg_val =3D readl(pin_reg); + reg_val &=3D ~SKY1_CONF_MASK; + reg_val |=3D (configs[i] & SKY1_CONF_MASK); + writel(reg_val, pin_reg); + + dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n", + spctl->pin_regs[pin_id], reg_val); + } + + return 0; +} + +static void sky1_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin_id) +{ + struct sky1_pinctrl *spctl =3D pinctrl_dev_get_drvdata(pctldev); + u32 config; + u32 *pin_reg; + + if (spctl->pin_regs[pin_id] =3D=3D -1) { + seq_puts(s, "N/A"); + return; + } + + pin_reg =3D spctl->base + spctl->pin_regs[pin_id]; + config =3D readl(pin_reg) & SKY1_CONF_MASK; + + seq_printf(s, "0x%x", config); +} + +static void sky1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int group) +{ + struct group_desc *grp; + unsigned long config; + const char *name; + int i, pin_id, ret; + + if (group >=3D pctldev->num_groups) + return; + + seq_puts(s, "\n"); + grp =3D pinctrl_generic_get_group(pctldev, group); + if (!grp) + return; + + for (i =3D 0; i < grp->grp.npins; i++) { + struct sky1_pin *pin =3D &(((struct sky1_pin *)(grp->data))[i]); + + pin_id =3D pin->offset / 4; + name =3D pin_get_name(pctldev, pin_id); + ret =3D sky1_pinconf_get(pctldev, pin_id, &config); + if (ret) + return; + seq_printf(s, " %s: 0x%lx\n", name, config); + } +} + +static const struct pinconf_ops sky1_pinconf_ops =3D { + .pin_config_get =3D sky1_pinconf_get, + .pin_config_set =3D sky1_pinconf_set, + .pin_config_dbg_show =3D sky1_pinconf_dbg_show, + .pin_config_group_dbg_show =3D sky1_pinconf_group_dbg_show, +}; + +/* + * Each pin represented in cix,pins consists of + * a number of u32 OFFSET and a number of u32 CONFIGS, + * the total size is OFFSET + CONFIGS for each pin. + * + * Default: + * + * <4byte, 4byte> + */ + +static void sky1_pinctrl_parse_pin(struct sky1_pinctrl *spctl, + unsigned int *pin_id, + struct sky1_pin *pin, + const __be32 **list_p, + struct device_node *np) +{ + const __be32 *list =3D *list_p; + unsigned int configs0, configs1; + const struct sky1_pinctrl_soc_info *info =3D spctl->info; + + pin->offset =3D be32_to_cpu(*list++); + *pin_id =3D pin->offset / 4; + pin->pin_id =3D *pin_id; + + configs0 =3D be32_to_cpu(*list++); + configs1 =3D be32_to_cpu(*list++); + pin->configs =3D (((configs0 & PADS_FUNCS_MASK) << PADS_FUNCS_BITS) | + (configs1 & PADS_CONFS_MASK)); + spctl->pin_regs[*pin_id] =3D pin->offset; + + *list_p =3D list; + + dev_dbg(spctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name, + pin->offset, pin->configs); +} + +static int sky1_pinctrl_parse_groups(struct device_node *np, + struct group_desc *grp, + struct sky1_pinctrl *spctl, + u32 index) +{ + struct sky1_pin *pin; + int size; + const __be32 *list; + int i; + unsigned int *pins; + + dev_dbg(spctl->dev, "group(%d): %pOFn\n", index, np); + + /* Initialise group */ + grp->grp.name =3D np->name; + + /* + * the binding format is cix,pins =3D , + * do sanity check and calculate pins number + * + * First try legacy 'cix,pins' property, then fall back to the + * generic 'pinmux'. + * + * Note: for generic 'pinmux' case, there's no CONFIG part in + * the binding format. + */ + list =3D of_get_property(np, "cix,pins", &size); + if (!list) { + list =3D of_get_property(np, "pinmux", &size); + if (!list) { + dev_err(spctl->dev, + "no cix,pins and pins property in node %pOF\n", np); + return -EINVAL; + } + } + + /* we do not check return since it's safe node passed down */ + if (!size || size % SKY1_PIN_SIZE) { + dev_err(spctl->dev, "Invalid cix,pins or pins property in node %pOF\n", = np); + return -EINVAL; + } + + grp->grp.npins =3D size / SKY1_PIN_SIZE; + grp->data =3D devm_kcalloc(spctl->dev, + grp->grp.npins, sizeof(struct sky1_pin), + GFP_KERNEL); + pins =3D devm_kcalloc(spctl->dev, + grp->grp.npins, sizeof(unsigned int), + GFP_KERNEL); + if (!pins || !grp->data) + return -ENOMEM; + + for (i =3D 0; i < grp->grp.npins; i++) { + pin =3D &((struct sky1_pin *)(grp->data))[i]; + sky1_pinctrl_parse_pin(spctl, &pins[i], pin, &list, np); + } + grp->grp.pins =3D pins; + return 0; +} + +static int sky1_pinctrl_parse_functions(struct device_node *np, + struct sky1_pinctrl *spctl, + u32 index) +{ + struct pinctrl_dev *pctl =3D spctl->pctl; + struct device_node *child; + struct function_desc *func; + struct group_desc *grp; + const char **group_names; + u32 i =3D 0; + + dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np); + + func =3D pinmux_generic_get_function(pctl, index); + if (!func) + return -EINVAL; + + /* Initialise function */ + func->func.name =3D np->name; + func->func.ngroups =3D of_get_child_count(np); + if (func->func.ngroups =3D=3D 0) { + dev_err(spctl->dev, "no groups defined in %pOF\n", np); + return -EINVAL; + } + group_names =3D devm_kcalloc(spctl->dev, func->func.ngroups, + sizeof(char *), GFP_KERNEL); + if (!group_names) + return -ENOMEM; + + for_each_child_of_node(np, child) + group_names[i++] =3D child->name; + func->func.groups =3D group_names; + + i =3D 0; + for_each_child_of_node(np, child) { + grp =3D devm_kzalloc(spctl->dev, sizeof(struct group_desc), + GFP_KERNEL); + if (!grp) { + of_node_put(child); + return -ENOMEM; + } + + mutex_lock(&spctl->mutex); + radix_tree_insert(&pctl->pin_group_tree, + spctl->group_index++, grp); + mutex_unlock(&spctl->mutex); + + sky1_pinctrl_parse_groups(child, grp, spctl, i++); + } + + return 0; +} + +/* + * Check if the DT contains pins in the direct child nodes. This indicates= the + * newer DT format to store pins. This function returns true if the first = found + * cix,pins property is in a child of np. Otherwise false is returned. + */ +static bool sky1_pinctrl_dt_is_flat_functions(struct device_node *np) +{ + struct device_node *function_np; + struct device_node *pinctrl_np; + + for_each_child_of_node(np, function_np) { + if (of_property_read_bool(function_np, "cix,pins")) { + of_node_put(function_np); + return true; + } + + for_each_child_of_node(function_np, pinctrl_np) { + if (of_property_read_bool(pinctrl_np, "cix,pins")) { + of_node_put(pinctrl_np); + of_node_put(function_np); + return false; + } + } + } + + return true; +} + +static int sky1_pinctrl_probe_dt(struct platform_device *pdev, + struct sky1_pinctrl *spctl) +{ + struct device_node *np =3D pdev->dev.of_node; + struct device_node *child; + struct pinctrl_dev *pctl =3D spctl->pctl; + u32 nfuncs =3D 0; + u32 i =3D 0; + bool flat_funcs; + + if (!np) + return -ENODEV; + + flat_funcs =3D sky1_pinctrl_dt_is_flat_functions(np); + if (flat_funcs) { + nfuncs =3D 1; + } else { + nfuncs =3D of_get_child_count(np); + if (nfuncs =3D=3D 0) { + dev_err(&pdev->dev, "no functions defined\n"); + return -EINVAL; + } + } + + for (i =3D 0; i < nfuncs; i++) { + struct function_desc *function; + + function =3D devm_kzalloc(&pdev->dev, sizeof(*function), + GFP_KERNEL); + if (!function) + return -ENOMEM; + + mutex_lock(&spctl->mutex); + radix_tree_insert(&pctl->pin_function_tree, i, function); + mutex_unlock(&spctl->mutex); + } + pctl->num_functions =3D nfuncs; + + spctl->group_index =3D 0; + if (flat_funcs) { + pctl->num_groups =3D of_get_child_count(np); + } else { + pctl->num_groups =3D 0; + for_each_child_of_node(np, child) + pctl->num_groups +=3D of_get_child_count(child); + } + + if (flat_funcs) { + sky1_pinctrl_parse_functions(np, spctl, 0); + } else { + i =3D 0; + for_each_child_of_node(np, child) + sky1_pinctrl_parse_functions(child, spctl, i++); + } + + return 0; +} + +int sky1_base_pinctrl_probe(struct platform_device *pdev, + const struct sky1_pinctrl_soc_info *info) +{ + struct pinctrl_desc *sky1_pinctrl_desc; + struct sky1_pinctrl *spctl; + int ret, i; + + if (!info || !info->pins || !info->npins) { + dev_err(&pdev->dev, "wrong pinctrl info\n"); + return -EINVAL; + } + + /* Create state holders etc for this driver */ + spctl =3D devm_kzalloc(&pdev->dev, sizeof(*spctl), GFP_KERNEL); + if (!spctl) + return -ENOMEM; + + spctl->pin_regs =3D devm_kmalloc_array(&pdev->dev, info->npins, + sizeof(*spctl->pin_regs), + GFP_KERNEL); + if (!spctl->pin_regs) + return -ENOMEM; + + for (i =3D 0; i < info->npins; i++) + spctl->pin_regs[i] =3D -1; + + spctl->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(spctl->base)) + return PTR_ERR(spctl->base); + + sky1_pinctrl_desc =3D devm_kzalloc(&pdev->dev, sizeof(*sky1_pinctrl_desc), + GFP_KERNEL); + if (!sky1_pinctrl_desc) + return -ENOMEM; + + sky1_pinctrl_desc->name =3D dev_name(&pdev->dev); + sky1_pinctrl_desc->pins =3D info->pins; + sky1_pinctrl_desc->npins =3D info->npins; + sky1_pinctrl_desc->pctlops =3D &sky1_pctrl_ops; + sky1_pinctrl_desc->pmxops =3D &sky1_pmx_ops; + sky1_pinctrl_desc->confops =3D &sky1_pinconf_ops; + sky1_pinctrl_desc->owner =3D THIS_MODULE; + + mutex_init(&spctl->mutex); + + spctl->info =3D info; + spctl->dev =3D &pdev->dev; + platform_set_drvdata(pdev, spctl); + ret =3D devm_pinctrl_register_and_init(&pdev->dev, + sky1_pinctrl_desc, spctl, + &spctl->pctl); + if (ret) { + dev_err(&pdev->dev, "could not register SKY1 pinctrl driver\n"); + return ret; + } + + ret =3D sky1_pinctrl_probe_dt(pdev, spctl); + + if (ret) { + dev_err(&pdev->dev, "fail to probe dt properties\n"); + return ret; + } + + pinctrl_provide_dummies(); + dev_info(&pdev->dev, "initialized SKY1 pinctrl driver\n"); + + return pinctrl_enable(spctl->pctl); +} +EXPORT_SYMBOL_GPL(sky1_base_pinctrl_probe); + + +MODULE_AUTHOR("Jerry Zhu "); +MODULE_DESCRIPTION("Cix SKy1 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/cix/pinctrl-sky1.c b/drivers/pinctrl/cix/pinct= rl-sky1.c new file mode 100644 index 000000000000..0e184eacbc0b --- /dev/null +++ b/drivers/pinctrl/cix/pinctrl-sky1.c @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include "linux/stddef.h" + +#include "../core.h" +#include "pinctrl-sky1.h" + +enum sky1_pads_s5 { + SKY1_IOMUXC_GPIO1 =3D 0, + SKY1_IOMUXC_GPIO2 =3D 1, + SKY1_IOMUXC_GPIO3 =3D 2, + SKY1_IOMUXC_GPIO4 =3D 3, + SKY1_IOMUXC_GPIO5 =3D 4, + SKY1_IOMUXC_GPIO6 =3D 5, + SKY1_IOMUXC_GPIO7 =3D 6, + SKY1_IOMUXC_GPIO8 =3D 7, + SKY1_IOMUXC_GPIO9 =3D 8, + SKY1_IOMUXC_GPIO10 =3D 9, + SKY1_IOMUXC_GPIO11 =3D 10, + SKY1_IOMUXC_GPIO12 =3D 11, + SKY1_IOMUXC_GPIO13 =3D 12, + SKY1_IOMUXC_GPIO14 =3D 13, + SKY1_IOMUXC_RSMRST_L =3D 14, + SKY1_IOMUXC_SRST_L =3D 15, + SKY1_IOMUXC_SLP_S3_L =3D 16, + SKY1_IOMUXC_SLP_S5_L =3D 17, + SKY1_IOMUXC_PWRGD =3D 18, + SKY1_IOMUXC_PWROK =3D 19, + SKY1_IOMUXC_PWRBTN_L =3D 20, + SKY1_IOMUXC_VDD_DDRIO_GATE =3D 21, + SKY1_IOMUXC_JTAG_GPIO_L =3D 22, + SKY1_IOMUXC_JTAG_TCK =3D 23, + SKY1_IOMUXC_JTAG_TDI =3D 24, + SKY1_IOMUXC_JTAG_TDO =3D 25, + SKY1_IOMUXC_TMS =3D 26, + SKY1_IOMUXC_TRST_L =3D 27, + SKY1_IOMUXC_SFI_I2C0_SCL =3D 28, + SKY1_IOMUXC_SFI_I2C0_SDA =3D 29, + SKY1_IOMUXC_SFI_I2C1_SCL =3D 30, + SKY1_IOMUXC_SFI_I2C1_SDA =3D 31, + SKY1_IOMUXC_SFI_GPIO0 =3D 32, + SKY1_IOMUXC_SFI_GPIO1 =3D 33, + SKY1_IOMUXC_SFI_GPIO2 =3D 34, + SKY1_IOMUXC_SFI_GPIO3 =3D 35, + SKY1_IOMUXC_SFI_GPIO4 =3D 36, + SKY1_IOMUXC_SFI_GPIO5 =3D 37, + SKY1_IOMUXC_SFI_GPIO6 =3D 38, + SKY1_IOMUXC_SFI_GPIO7 =3D 39, + SKY1_IOMUXC_SFI_GPIO8 =3D 40, + SKY1_IOMUXC_SFI_GPIO9 =3D 41, + SKY1_IOMUXC_SPI1_MISO =3D 42, + SKY1_IOMUXC_SPI1_CS0 =3D 43, + SKY1_IOMUXC_SPI1_CS1 =3D 44, + SKY1_IOMUXC_SPI1_MOSI =3D 45, + SKY1_IOMUXC_SPI1_CLK =3D 46, + SKY1_IOMUXC_USB_OC0_L =3D 47, + SKY1_IOMUXC_USB_OC1_L =3D 48, + SKY1_IOMUXC_USB_OC2_L =3D 49, + SKY1_IOMUXC_USB_OC3_L =3D 50, + SKY1_IOMUXC_USB_OC4_L =3D 51, + SKY1_IOMUXC_USB_OC5_L =3D 52, + SKY1_IOMUXC_USB_OC6_L =3D 53, + SKY1_IOMUXC_USB_OC7_L =3D 54, + SKY1_IOMUXC_USB_OC8_L =3D 55, + SKY1_IOMUXC_USB_OC9_L =3D 56, + SKY1_IOMUXC_DRIVE_VBUS0 =3D 57, + SKY1_IOMUXC_DRIVE_VBUS4 =3D 58, + SKY1_IOMUXC_DRIVE_VBUS5 =3D 59, + SKY1_IOMUXC_SE_QSPI_CLK =3D 60, + SKY1_IOMUXC_SE_QSPI_CS_L =3D 61, + SKY1_IOMUXC_SE_QSPI_DATA0 =3D 62, + SKY1_IOMUXC_SE_QSPI_DATA1 =3D 63, + SKY1_IOMUXC_SE_QSPI_DATA2 =3D 64, + SKY1_IOMUXC_SE_QSPI_DATA3 =3D 65, +}; + +enum sky1_pads { + SKY1_IOMUXC_GPIO43 =3D 0, + SKY1_IOMUXC_GPIO44 =3D 1, + SKY1_IOMUXC_GPIO45 =3D 2, + SKY1_IOMUXC_GPIO46 =3D 3, + SKY1_IOMUXC_RESET_IN_L =3D 4, + SKY1_IOMUXC_PLT_RESET_L =3D 5, + SKY1_IOMUXC_THERMRIP_L =3D 6, + SKY1_IOMUXC_PROCHOT_L =3D 7, + SKY1_IOMUXC_PM_I2C0_CLK =3D 8, + SKY1_IOMUXC_PM_I2C0_DATA =3D 9, + SKY1_IOMUXC_PM_I2C1_CLK =3D 10, + SKY1_IOMUXC_PM_I2C1_DATA =3D 11, + SKY1_IOMUXC_PM_I2C2_CLK =3D 12, + SKY1_IOMUXC_PM_I2C2_DATA =3D 13, + SKY1_IOMUXC_PM_I2C3_CLK =3D 14, + SKY1_IOMUXC_PM_I2C3_DATA =3D 15, + SKY1_IOMUXC_STRAP0 =3D 16, + SKY1_IOMUXC_STRAP1 =3D 17, + SKY1_IOMUXC_DP2_DIGON =3D 18, + SKY1_IOMUXC_DP2_BLON =3D 19, + SKY1_IOMUXC_DP2_VARY_BL =3D 20, + SKY1_IOMUXC_I2C7_SCL =3D 21, + SKY1_IOMUXC_I2C7_SDA =3D 22, + SKY1_IOMUXC_UART6_CSU_SE_TXD =3D 23, + SKY1_IOMUXC_CLK_REQ1_L =3D 24, + SKY1_IOMUXC_CLK_REQ3_L =3D 25, + SKY1_IOMUXC_I2C5_SCL =3D 26, + SKY1_IOMUXC_I2C5_SDA =3D 27, + SKY1_IOMUXC_I2C6_SCL =3D 28, + SKY1_IOMUXC_I2C6_SDA =3D 29, + SKY1_IOMUXC_I2C0_CLK =3D 30, + SKY1_IOMUXC_I2C0_SDA =3D 31, + SKY1_IOMUXC_I2C1_CLK =3D 32, + SKY1_IOMUXC_I2C1_SDA =3D 33, + SKY1_IOMUXC_I2C2_SCL =3D 34, + SKY1_IOMUXC_I2C2_SDA =3D 35, + SKY1_IOMUXC_I3C0_PUR_EN_L =3D 36, + SKY1_IOMUXC_I2C3_CLK =3D 37, + SKY1_IOMUXC_I2C3_SDA =3D 38, + SKY1_IOMUXC_I3C1_PUR_EN_L =3D 39, + SKY1_IOMUXC_I2C4_CLK =3D 40, + SKY1_IOMUXC_I2C4_SDA =3D 41, + SKY1_IOMUXC_HDA_BITCLK =3D 42, + SKY1_IOMUXC_HDA_RST_L =3D 43, + SKY1_IOMUXC_HDA_SDIN0 =3D 44, + SKY1_IOMUXC_HDA_SDOUT0 =3D 45, + SKY1_IOMUXC_HDA_SYNC =3D 46, + SKY1_IOMUXC_HDA_SDIN1 =3D 47, + SKY1_IOMUXC_HDA_SDOUT1 =3D 48, + SKY1_IOMUXC_I2S1_MCLK =3D 49, + SKY1_IOMUXC_I2S1_SCK =3D 50, + SKY1_IOMUXC_I2S1_WS =3D 51, + SKY1_IOMUXC_I2S1_DATA_IN =3D 52, + SKY1_IOMUXC_I2S1_DATA_OUT =3D 53, + SKY1_IOMUXC_I2S2_MCLK =3D 54, + SKY1_IOMUXC_I2S2_RSCK =3D 55, + SKY1_IOMUXC_I2S2_RWS =3D 56, + SKY1_IOMUXC_I2S2_TSCK =3D 57, + SKY1_IOMUXC_I2S2_TWS =3D 58, + SKY1_IOMUXC_I2S2_DATA_IN0 =3D 59, + SKY1_IOMUXC_I2S2_DATA_IN1 =3D 60, + SKY1_IOMUXC_I2S2_DATA_OUT0 =3D 61, + SKY1_IOMUXC_I2S2_DATA_OUT1 =3D 62, + SKY1_IOMUXC_I2S2_DATA_OUT2 =3D 63, + SKY1_IOMUXC_I2S2_DATA_OUT3 =3D 64, + SKY1_IOMUXC_I2S3_MCLK =3D 65, + SKY1_IOMUXC_I2S3_RSCK =3D 66, + SKY1_IOMUXC_I2S3_RWS =3D 67, + SKY1_IOMUXC_I2S3_TSCK =3D 68, + SKY1_IOMUXC_I2S3_TWS =3D 69, + SKY1_IOMUXC_I2S3_DATA_IN0 =3D 70, + SKY1_IOMUXC_I2S3_DATA_IN1 =3D 71, + SKY1_IOMUXC_I2S3_DATA_OUT0 =3D 72, + SKY1_IOMUXC_I2S3_DATA_OUT1 =3D 73, + SKY1_IOMUXC_I2S4_MCLK_LB =3D 74, + SKY1_IOMUXC_I2S4_SCK_LB =3D 75, + SKY1_IOMUXC_I2S4_WS_LB =3D 76, + SKY1_IOMUXC_I2S4_DATA_IN_LB =3D 77, + SKY1_IOMUXC_I2S4_DATA_OUT_LB =3D 78, + SKY1_IOMUXC_UART0_TXD =3D 79, + SKY1_IOMUXC_UART0_RXD =3D 80, + SKY1_IOMUXC_UART0_CTS =3D 81, + SKY1_IOMUXC_UART0_RTS =3D 82, + SKY1_IOMUXC_UART1_TXD =3D 83, + SKY1_IOMUXC_UART1_RXD =3D 84, + SKY1_IOMUXC_UART1_CTS =3D 85, + SKY1_IOMUXC_UART1_RTS =3D 86, + SKY1_IOMUXC_UART2_TXD =3D 87, + SKY1_IOMUXC_UART2_RXD =3D 88, + SKY1_IOMUXC_UART3_TXD =3D 89, + SKY1_IOMUXC_UART3_RXD =3D 90, + SKY1_IOMUXC_UART3_CTS =3D 91, + SKY1_IOMUXC_UART3_RTS =3D 92, + SKY1_IOMUXC_UART4_CSU_PM_TXD =3D 93, + SKY1_IOMUXC_UART4_CSU_PM_RXD =3D 94, + SKY1_IOMUXC_UART5_CSU_SE_TXD =3D 95, + SKY1_IOMUXC_UART5_CSU_SE_RXD =3D 96, + SKY1_IOMUXC_UART6_CSU_SE_RXD =3D 97, + SKY1_IOMUXC_CLK_REQ0_L =3D 98, + SKY1_IOMUXC_CLK_REQ2_L =3D 99, + SKY1_IOMUXC_CLK_REQ4_L =3D 100, + SKY1_IOMUXC_CSI0_MCLK0 =3D 101, + SKY1_IOMUXC_CSI0_MCLK1 =3D 102, + SKY1_IOMUXC_CSI1_MCLK0 =3D 103, + SKY1_IOMUXC_CSI1_MCLK1 =3D 104, + SKY1_IOMUXC_GMAC0_REFCLK_25M =3D 105, + SKY1_IOMUXC_GMAC0_TX_CTL =3D 106, + SKY1_IOMUXC_GMAC0_TXD0 =3D 107, + SKY1_IOMUXC_GMAC0_TXD1 =3D 108, + SKY1_IOMUXC_GMAC0_TXD2 =3D 109, + SKY1_IOMUXC_GMAC0_TXD3 =3D 110, + SKY1_IOMUXC_GMAC0_TX_CLK =3D 111, + SKY1_IOMUXC_GMAC0_RX_CTL =3D 112, + SKY1_IOMUXC_GMAC0_RXD0 =3D 113, + SKY1_IOMUXC_GMAC0_RXD1 =3D 114, + SKY1_IOMUXC_GMAC0_RXD2 =3D 115, + SKY1_IOMUXC_GMAC0_RXD3 =3D 116, + SKY1_IOMUXC_GMAC0_RX_CLK =3D 117, + SKY1_IOMUXC_GMAC0_MDC =3D 118, + SKY1_IOMUXC_GMAC0_MDIO =3D 119, + SKY1_IOMUXC_GMAC1_REFCLK_25M =3D 120, + SKY1_IOMUXC_GMAC1_TX_CTL =3D 121, + SKY1_IOMUXC_GMAC1_TXD0 =3D 122, + SKY1_IOMUXC_GMAC1_TXD1 =3D 123, + SKY1_IOMUXC_GMAC1_TXD2 =3D 124, + SKY1_IOMUXC_GMAC1_TXD3 =3D 125, + SKY1_IOMUXC_GMAC1_TX_CLK =3D 126, + SKY1_IOMUXC_GMAC1_RX_CTL =3D 127, + SKY1_IOMUXC_GMAC1_RXD0 =3D 128, + SKY1_IOMUXC_GMAC1_RXD1 =3D 129, + SKY1_IOMUXC_GMAC1_RXD2 =3D 130, + SKY1_IOMUXC_GMAC1_RXD3 =3D 131, + SKY1_IOMUXC_GMAC1_RX_CLK =3D 132, + SKY1_IOMUXC_GMAC1_MDC =3D 133, + SKY1_IOMUXC_GMAC1_MDIO =3D 134, + SKY1_IOMUXC_PM_GPIO0 =3D 135, + SKY1_IOMUXC_PM_GPIO1 =3D 136, + SKY1_IOMUXC_PM_GPIO2 =3D 137, +}; + +/* Pad names for the s5 domain pinmux subsystem */ +static const struct pinctrl_pin_desc sky1_pinctrl_s5_pads[] =3D { + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO2), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO3), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO4), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO5), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO6), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO7), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO8), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO9), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO10), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO11), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO12), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO13), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO14), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_RSMRST_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SRST_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SLP_S3_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SLP_S5_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PWRGD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PWROK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PWRBTN_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_VDD_DDRIO_GATE), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_JTAG_GPIO_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_JTAG_TCK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_JTAG_TDI), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_JTAG_TDO), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_TMS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_TRST_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_I2C0_SCL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_I2C0_SDA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_I2C1_SCL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_I2C1_SDA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_GPIO0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_GPIO1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_GPIO2), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_GPIO3), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_GPIO4), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_GPIO5), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_GPIO6), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_GPIO7), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_GPIO8), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SFI_GPIO9), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SPI1_MISO), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SPI1_CS0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SPI1_CS1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SPI1_MOSI), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SPI1_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_USB_OC0_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_USB_OC1_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_USB_OC2_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_USB_OC3_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_USB_OC4_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_USB_OC5_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_USB_OC6_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_USB_OC7_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_USB_OC8_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_USB_OC9_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_DRIVE_VBUS0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_DRIVE_VBUS4), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_DRIVE_VBUS5), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SE_QSPI_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SE_QSPI_CS_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SE_QSPI_DATA0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SE_QSPI_DATA1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SE_QSPI_DATA2), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_SE_QSPI_DATA3), +}; + +/* Pad names for the s0 domain pinmux subsystem */ +static const struct pinctrl_pin_desc sky1_pinctrl_pads[] =3D { + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO43), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO44), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO45), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GPIO46), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_RESET_IN_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PLT_RESET_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_THERMRIP_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PROCHOT_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_I2C0_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_I2C0_DATA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_I2C1_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_I2C1_DATA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_I2C2_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_I2C2_DATA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_I2C3_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_I2C3_DATA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_STRAP0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_STRAP1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_DP2_DIGON), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_DP2_BLON), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_DP2_VARY_BL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C7_SCL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C7_SDA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART6_CSU_SE_TXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_CLK_REQ1_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_CLK_REQ3_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C5_SCL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C5_SDA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C6_SCL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C6_SDA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C0_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C0_SDA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C1_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C1_SDA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C2_SCL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C2_SDA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I3C0_PUR_EN_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C3_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C3_SDA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I3C1_PUR_EN_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C4_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2C4_SDA), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_HDA_BITCLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_HDA_RST_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_HDA_SDIN0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_HDA_SDOUT0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_HDA_SYNC), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_HDA_SDIN1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_HDA_SDOUT1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S1_MCLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S1_SCK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S1_WS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S1_DATA_IN), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S1_DATA_OUT), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_MCLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_RSCK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_RWS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_TSCK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_TWS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_DATA_IN0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_DATA_IN1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_DATA_OUT0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_DATA_OUT1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_DATA_OUT2), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S2_DATA_OUT3), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S3_MCLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S3_RSCK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S3_RWS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S3_TSCK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S3_TWS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S3_DATA_IN0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S3_DATA_IN1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S3_DATA_OUT0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S3_DATA_OUT1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S4_MCLK_LB), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S4_SCK_LB), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S4_WS_LB), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S4_DATA_IN_LB), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_I2S4_DATA_OUT_LB), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART0_TXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART0_RXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART0_CTS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART0_RTS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART1_TXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART1_RXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART1_CTS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART1_RTS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART2_TXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART2_RXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART3_TXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART3_RXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART3_CTS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART3_RTS), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART4_CSU_PM_TXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART4_CSU_PM_RXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART5_CSU_SE_TXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART5_CSU_SE_RXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_UART6_CSU_SE_RXD), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_CLK_REQ0_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_CLK_REQ2_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_CLK_REQ4_L), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_CSI0_MCLK0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_CSI0_MCLK1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_CSI1_MCLK0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_CSI1_MCLK1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_REFCLK_25M), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_TX_CTL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_TXD0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_TXD1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_TXD2), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_TXD3), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_TX_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_RX_CTL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_RXD0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_RXD1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_RXD2), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_RXD3), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_RX_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_MDC), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC0_MDIO), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_REFCLK_25M), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_TX_CTL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_TXD0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_TXD1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_TXD2), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_TXD3), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_TX_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_RX_CTL), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_RXD0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_RXD1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_RXD2), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_RXD3), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_RX_CLK), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_MDC), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_GMAC1_MDIO), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_GPIO0), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_GPIO1), + SKY1_PINCTRL_PIN(SKY1_IOMUXC_PM_GPIO2), +}; + +static const struct sky1_pinctrl_soc_info sky1_pinctrl_s5_info =3D { + .pins =3D sky1_pinctrl_s5_pads, + .npins =3D ARRAY_SIZE(sky1_pinctrl_s5_pads), +}; + +static const struct sky1_pinctrl_soc_info sky1_pinctrl_info =3D { + .pins =3D sky1_pinctrl_pads, + .npins =3D ARRAY_SIZE(sky1_pinctrl_pads), +}; + +static const struct of_device_id sky1_pinctrl_of_match[] =3D { + { .compatible =3D "cix,sky1-iomuxc-s5", .data =3D &sky1_pinctrl_s5_info, = }, + { .compatible =3D "cix,sky1-iomuxc", .data =3D &sky1_pinctrl_info, }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sky1_pinctrl_of_match); + +static int __maybe_unused sky1_pinctrl_suspend(struct device *dev) +{ + struct sky1_pinctrl *spctl =3D dev_get_drvdata(dev); + + return pinctrl_force_sleep(spctl->pctl); +} + +static int __maybe_unused sky1_pinctrl_resume(struct device *dev) +{ + struct sky1_pinctrl *spctl =3D dev_get_drvdata(dev); + + return pinctrl_force_default(spctl->pctl); +} + +const struct dev_pm_ops sky1_pinctrl_pm_ops =3D { + SET_LATE_SYSTEM_SLEEP_PM_OPS(sky1_pinctrl_suspend, + sky1_pinctrl_resume) +}; +EXPORT_SYMBOL_GPL(sky1_pinctrl_pm_ops); + +static int sky1_pinctrl_probe(struct platform_device *pdev) +{ + const struct sky1_pinctrl_soc_info *pinctrl_info; + + pinctrl_info =3D device_get_match_data(&pdev->dev); + if (!pinctrl_info) + return -ENODEV; + + return sky1_base_pinctrl_probe(pdev, pinctrl_info); +} + +static struct platform_driver sky1_pinctrl_driver =3D { + .driver =3D { + .name =3D "sky1-pinctrl", + .of_match_table =3D of_match_ptr(sky1_pinctrl_of_match), + .pm =3D &sky1_pinctrl_pm_ops, + }, + .probe =3D sky1_pinctrl_probe, +}; + +static int __init sky1_pinctrl_init(void) +{ + return platform_driver_register(&sky1_pinctrl_driver); +} +arch_initcall(sky1_pinctrl_init); + +MODULE_AUTHOR("Jerry Zhu "); +MODULE_DESCRIPTION("Cix Sky1 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/cix/pinctrl-sky1.h b/drivers/pinctrl/cix/pinct= rl-sky1.h new file mode 100644 index 000000000000..09b25dbb6db3 --- /dev/null +++ b/drivers/pinctrl/cix/pinctrl-sky1.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Author: Jerry Zhu + */ + +#ifndef __DRIVERS_PINCTRL_SKY1_H +#define __DRIVERS_PINCTRL_SKY1_H + +#include +#include + +/** + * struct sky1_pin - describes a single SKY1 pin + * @pin_id: the pin id of this pin + * @offest: the iomux register offset + * @configs: the mux and config value for pin + */ +struct sky1_pin { + unsigned int pin_id; + unsigned int offset; + unsigned long configs; +}; + +/** + * sky1_pin_reg contains 32 bits + * bit7:bit8 for function select + * bit0:bit6 for pad configuration + */ +typedef u32 sky1_pin_reg; + +/** + * @dev: a pointer back to containing device + * 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27 Aug 2025 10:42:23 +0800 (CST) From: Gary Yang To: linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, Gary Yang Subject: [PATCH 2/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl Date: Wed, 27 Aug 2025 10:42:21 +0800 Message-ID: <20250827024222.588082-3-gary.yang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250827024222.588082-1-gary.yang@cixtech.com> References: <20250827024222.588082-1-gary.yang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E5:EE_|KL1PR06MB6109:EE_ X-MS-Office365-Filtering-Correlation-Id: 7a5b9731-7337-462a-a7ac-08dde5135aee X-MS-Exchange-SenderADCheck: 1 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text/plain; charset="utf-8" Add dt-bindings docs Signed-off-by: Gary Yang --- .../bindings/pinctrl/cix,sky1-pinctrl.yaml | 77 +++ include/dt-bindings/pinctrl/pads-sky1.h | 592 ++++++++++++++++++ 2 files changed, 669 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/cix,sky1-pinc= trl.yaml create mode 100644 include/dt-bindings/pinctrl/pads-sky1.h diff --git a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yam= l b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml new file mode 100644 index 000000000000..10a4a292188e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 Pin Controller + +maintainers: + - Gary Yang + +description: + Please refer to pinctrl-bindings.txt in this directory for common + binding part and usage. + +properties: + compatible: + enum: + - cix,sky1-iomuxc + - cix,sky1-iomuxc-s5 + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + + properties: + cix,pins: + description: + each entry consists of 3 integers and represents the mux and con= fig + setting for one pin. The first 2 integers are + specified using a CIX_PAD_* macro.The last integer CONFIG is the= pad + setting value like pull-up on this pin. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of register. + - description: | + "func_num" indicates the mux value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be + applied. + + required: + - cix,pins + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + # Pinmux controller node + - | + #include + iomuxc: pinctrl@4170000 { + compatible =3D "cix,sky1-iomuxc"; + reg =3D <0x4170000 0x1000>; + + pinctrl_hog: hog-pins { + cix,pins =3D + ; + }; + }; diff --git a/include/dt-bindings/pinctrl/pads-sky1.h b/include/dt-bindings/= pinctrl/pads-sky1.h new file mode 100644 index 000000000000..44550e4105b3 --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-sky1.h @@ -0,0 +1,592 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2024-2025 Cix Technology Group Co., Ltd. + */ + +#ifndef __SKY1_PADS_H +#define __SKY1_PADS_H + +#define CIX_PAD_GPIO001_OFFSET 0x0 +#define CIX_PAD_GPIO002_OFFSET 0x4 +#define CIX_PAD_GPIO003_OFFSET 0x8 +#define CIX_PAD_GPIO004_OFFSET 0xc +#define CIX_PAD_GPIO005_OFFSET 0x10 +#define CIX_PAD_GPIO006_OFFSET 0x14 +#define CIX_PAD_GPIO007_OFFSET 0x18 +#define CIX_PAD_GPIO008_OFFSET 0x1c +#define CIX_PAD_GPIO009_OFFSET 0x20 +#define CIX_PAD_GPIO010_OFFSET 0x24 +#define CIX_PAD_GPIO011_OFFSET 0x28 +#define CIX_PAD_GPIO012_OFFSET 0x2c +#define CIX_PAD_GPIO013_OFFSET 0x30 +#define CIX_PAD_GPIO014_OFFSET 0x34 +#define CIX_PAD_SFI_I2C0_SCL_OFFSET 0x70 +#define CIX_PAD_SFI_I2C0_SDA_OFFSET 0x74 +#define CIX_PAD_SFI_I2C1_SCL_OFFSET 0x78 +#define CIX_PAD_SFI_I2C1_SDA_OFFSET 0x7c +#define CIX_PAD_SFI_GPIO0_OFFSET 0x80 +#define CIX_PAD_SFI_GPIO1_OFFSET 0x84 +#define CIX_PAD_SFI_GPIO2_OFFSET 0x88 +#define CIX_PAD_GPIO018_OFFSET 0x8c +#define CIX_PAD_GPIO019_OFFSET 0x90 +#define CIX_PAD_GPIO020_OFFSET 0x94 +#define CIX_PAD_GPIO021_OFFSET 0x98 +#define CIX_PAD_GPIO022_OFFSET 0x9c +#define CIX_PAD_GPIO023_OFFSET 0xa0 +#define CIX_PAD_GPIO024_OFFSET 0xa4 +#define CIX_PAD_SPI1_MISO_OFFSET 0xa8 +#define CIX_PAD_SPI1_CS0_OFFSET 0xac +#define CIX_PAD_SPI1_CS1_OFFSET 0xb0 +#define CIX_PAD_SPI1_MOSI_OFFSET 0xb4 +#define CIX_PAD_SPI1_CLK_OFFSET 0xb8 +#define CIX_PAD_GPIO030_OFFSET 0xbc +#define CIX_PAD_GPIO031_OFFSET 0xc0 +#define CIX_PAD_GPIO032_OFFSET 0xc4 +#define CIX_PAD_GPIO033_OFFSET 0xc8 +#define CIX_PAD_GPIO034_OFFSET 0xcc +#define CIX_PAD_GPIO035_OFFSET 0xd0 +#define CIX_PAD_GPIO036_OFFSET 0xd4 +#define CIX_PAD_GPIO037_OFFSET 0xd8 +#define CIX_PAD_GPIO038_OFFSET 0xdc +#define CIX_PAD_GPIO039_OFFSET 0xe0 +#define CIX_PAD_GPIO040_OFFSET 0xe4 +#define CIX_PAD_GPIO041_OFFSET 0xe8 +#define CIX_PAD_GPIO042_OFFSET 0xec +#define CIX_PAD_SE_QSPI_CLK_OFFSET 0xf0 +#define CIX_PAD_SE_QSPI_CS_L_OFFSET 0xf4 +#define CIX_PAD_SE_QSPI_DATA0_OFFSET 0xf8 +#define CIX_PAD_SE_QSPI_DATA1_OFFSET 0xfc +#define CIX_PAD_SE_QSPI_DATA2_OFFSET 0x100 +#define CIX_PAD_SE_QSPI_DATA3_OFFSET 0x104 +#define CIX_PAD_GPIO043_OFFSET 0x0 +#define CIX_PAD_GPIO044_OFFSET 0x4 +#define CIX_PAD_GPIO045_OFFSET 0x8 +#define CIX_PAD_GPIO046_OFFSET 0xc +#define CIX_PAD_DP2_DIGON_OFFSET 0x48 +#define CIX_PAD_DP2_BLON_OFFSET 0x4c +#define CIX_PAD_DP2_VARY_BL_OFFSET 0x50 +#define CIX_PAD_I2C7_SCL_OFFSET 0x54 +#define CIX_PAD_I2C7_SDA_OFFSET 0x58 +#define CIX_PAD_I2C5_SCL_OFFSET 0x68 +#define CIX_PAD_I2C5_SDA_OFFSET 0x6c +#define CIX_PAD_I2C6_SCL_OFFSET 0x70 +#define CIX_PAD_I2C6_SDA_OFFSET 0x74 +#define CIX_PAD_I2C0_CLK_OFFSET 0x78 +#define CIX_PAD_I2C0_SDA_OFFSET 0x7c +#define CIX_PAD_I2C1_CLK_OFFSET 0x80 +#define CIX_PAD_I2C1_SDA_OFFSET 0x84 +#define CIX_PAD_I2C2_SCL_OFFSET 0x88 +#define CIX_PAD_I2C2_SDA_OFFSET 0x8c +#define CIX_PAD_GPIO057_OFFSET 0x90 +#define CIX_PAD_I2C3_CLK_OFFSET 0x94 +#define CIX_PAD_I2C3_SDA_OFFSET 0x98 +#define CIX_PAD_GPIO060_OFFSET 0x9c +#define CIX_PAD_I2C4_CLK_OFFSET 0xa0 +#define CIX_PAD_I2C4_SDA_OFFSET 0xa4 +#define CIX_PAD_HDA_BITCLK_OFFSET 0xa8 +#define CIX_PAD_HDA_RST_L_OFFSET 0xac +#define CIX_PAD_HDA_SDIN0_OFFSET 0xb0 +#define CIX_PAD_HDA_SDOUT0_OFFSET 0xb4 +#define CIX_PAD_HDA_SYNC_OFFSET 0xb8 +#define CIX_PAD_HDA_SDIN1_OFFSET 0xbc +#define CIX_PAD_HDA_SDOUT1_OFFSET 0xc0 +#define CIX_PAD_I2S1_MCLK_OFFSET 0xc4 +#define CIX_PAD_I2S1_SCK_OFFSET 0xc8 +#define CIX_PAD_I2S1_WS_OFFSET 0xcc +#define CIX_PAD_I2S1_DATA_IN_OFFSET 0xd0 +#define CIX_PAD_I2S1_DATA_OUT_OFFSET 0xd4 +#define CIX_PAD_I2S2_MCLK_OFFSET 0xd8 +#define CIX_PAD_I2S2_RSCK_OFFSET 0xdc +#define CIX_PAD_I2S2_RWS_OFFSET 0xe0 +#define CIX_PAD_I2S2_TSCK_OFFSET 0xe4 +#define CIX_PAD_I2S2_TWS_OFFSET 0xe8 +#define CIX_PAD_I2S2_DATA_IN0_OFFSET 0xec +#define CIX_PAD_I2S2_DATA_IN1_OFFSET 0xf0 +#define CIX_PAD_I2S2_DATA_OUT0_OFFSET 0xf4 +#define CIX_PAD_I2S2_DATA_OUT1_OFFSET 0xf8 +#define CIX_PAD_I2S2_DATA_OUT2_OFFSET 0xfc +#define CIX_PAD_I2S2_DATA_OUT3_OFFSET 0x100 +#define CIX_PAD_I2S3_MCLK_OFFSET 0x104 +#define CIX_PAD_I2S3_RSCK_OFFSET 0x108 +#define CIX_PAD_I2S3_RWS_OFFSET 0x10c +#define CIX_PAD_I2S3_TSCK_OFFSET 0x110 +#define CIX_PAD_I2S3_TWS_OFFSET 0x114 +#define CIX_PAD_I2S3_DATA_IN0_OFFSET 0x118 +#define CIX_PAD_I2S3_DATA_IN1_OFFSET 0x11c +#define CIX_PAD_I2S3_DATA_OUT0_OFFSET 0x120 +#define CIX_PAD_I2S3_DATA_OUT1_OFFSET 0x124 +#define CIX_PAD_GPIO090_OFFSET 0x128 +#define CIX_PAD_GPIO091_OFFSET 0x12c +#define CIX_PAD_GPIO092_OFFSET 0x130 +#define CIX_PAD_GPIO093_OFFSET 0x134 +#define CIX_PAD_GPIO094_OFFSET 0x138 +#define CIX_PAD_UART0_TXD_OFFSET 0x13c +#define CIX_PAD_UART0_RXD_OFFSET 0x140 +#define CIX_PAD_UART0_CTS_OFFSET 0x144 +#define CIX_PAD_UART0_RTS_OFFSET 0x148 +#define CIX_PAD_UART1_TXD_OFFSET 0x14c +#define CIX_PAD_UART1_RXD_OFFSET 0x150 +#define CIX_PAD_UART1_CTS_OFFSET 0x154 +#define CIX_PAD_UART1_RTS_OFFSET 0x158 +#define CIX_PAD_UART2_TXD_OFFSET 0x15c +#define CIX_PAD_UART2_RXD_OFFSET 0x160 +#define CIX_PAD_UART3_TXD_OFFSET 0x164 +#define CIX_PAD_UART3_RXD_OFFSET 0x168 +#define CIX_PAD_UART3_CTS_OFFSET 0x16c +#define CIX_PAD_UART3_RTS_OFFSET 0x170 +#define CIX_PAD_UART4_CSU_PM_TXD_OFFSET 0x174 +#define CIX_PAD_UART4_CSU_PM_RXD_OFFSET 0x178 +#define CIX_PAD_UART5_CSU_SE_TXD_OFFSET 0x17c +#define CIX_PAD_UART5_CSU_SE_RXD_OFFSET 0x180 +#define CIX_PAD_UART6_CSU_SE_RXD_OFFSET 0x184 +#define CIX_PAD_CLK_REQ0_L_OFFSET 0x188 +#define CIX_PAD_CLK_REQ2_L_OFFSET 0x18c +#define CIX_PAD_CLK_REQ4_L_OFFSET 0x190 +#define CIX_PAD_CSI0_MCLK0_OFFSET 0x194 +#define CIX_PAD_CSI0_MCLK1_OFFSET 0x198 +#define CIX_PAD_CSI1_MCLK0_OFFSET 0x19c +#define CIX_PAD_CSI1_MCLK1_OFFSET 0x1a0 +#define CIX_PAD_GPIO121_OFFSET 0x1a4 +#define CIX_PAD_GPIO122_OFFSET 0x1a8 +#define CIX_PAD_GPIO123_OFFSET 0x1ac +#define CIX_PAD_GPIO124_OFFSET 0x1b0 +#define CIX_PAD_GPIO125_OFFSET 0x1b4 +#define CIX_PAD_GPIO126_OFFSET 0x1b8 +#define CIX_PAD_GPIO127_OFFSET 0x1bc +#define CIX_PAD_GPIO128_OFFSET 0x1c0 +#define CIX_PAD_GPIO129_OFFSET 0x1c4 +#define CIX_PAD_GPIO130_OFFSET 0x1c8 +#define CIX_PAD_GPIO131_OFFSET 0x1cc +#define CIX_PAD_GPIO132_OFFSET 0x1d0 +#define CIX_PAD_GPIO133_OFFSET 0x1d4 +#define CIX_PAD_GPIO134_OFFSET 0x1d8 +#define CIX_PAD_GPIO135_OFFSET 0x1dc +#define CIX_PAD_GPIO136_OFFSET 0x1e0 +#define CIX_PAD_GPIO137_OFFSET 0x1e4 +#define CIX_PAD_GPIO138_OFFSET 0x1e8 +#define CIX_PAD_GPIO139_OFFSET 0x1ec +#define CIX_PAD_GPIO140_OFFSET 0x1f0 +#define CIX_PAD_GPIO141_OFFSET 0x1f4 +#define CIX_PAD_GPIO142_OFFSET 0x1f8 +#define CIX_PAD_GPIO143_OFFSET 0x1fc +#define CIX_PAD_GPIO144_OFFSET 0x200 +#define CIX_PAD_GPIO145_OFFSET 0x204 +#define CIX_PAD_GPIO146_OFFSET 0x208 +#define CIX_PAD_GPIO147_OFFSET 0x20c +#define CIX_PAD_GPIO148_OFFSET 0x210 +#define CIX_PAD_GPIO149_OFFSET 0x214 +#define CIX_PAD_GPIO150_OFFSET 0x218 +#define CIX_PAD_GPIO151_OFFSET 0x21c +#define CIX_PAD_GPIO152_OFFSET 0x220 +#define CIX_PAD_GPIO153_OFFSET 0x224 + +#define CIX_PAD_GPIO001_FUNC_GPIO001 0x0 +#define CIX_PAD_GPIO002_FUNC_GPIO002 0x0 +#define CIX_PAD_GPIO003_FUNC_GPIO003 0x0 +#define CIX_PAD_GPIO004_FUNC_GPIO004 0x0 +#define CIX_PAD_GPIO005_FUNC_GPIO005 0x0 +#define CIX_PAD_GPIO006_FUNC_GPIO006 0x0 +#define CIX_PAD_GPIO007_FUNC_GPIO007 0x0 +#define CIX_PAD_GPIO008_FUNC_GPIO008 0x0 +#define CIX_PAD_GPIO009_FUNC_GPIO009 0x0 +#define CIX_PAD_GPIO010_FUNC_GPIO010 0x0 +#define CIX_PAD_GPIO011_FUNC_GPIO011 0x0 +#define CIX_PAD_GPIO012_FUNC_GPIO012 0x0 +#define CIX_PAD_GPIO013_FUNC_GPIO013 0x0 +#define CIX_PAD_GPIO014_FUNC_GPIO014 0x0 +#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I2C0_SCL 0x0 +#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I3C0_SCL 0x1 +#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I2C0_SDA 0x0 +#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I3C0_SDA 0x1 +#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I2C1_SCL 0x0 +#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I3C1_SCL 0x1 +#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_SPI_CS0 0x2 +#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I2C1_SDA 0x0 +#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I3C1_SDA 0x1 +#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_SPI_CS1 0x2 +#define CIX_PAD_SFI_GPIO0_FUNC_GPIO015 0x0 +#define CIX_PAD_SFI_GPIO0_FUNC_SFI_SPI_SCK 0x1 +#define CIX_PAD_SFI_GPIO0_FUNC_SFI_GPIO0 0x2 +#define CIX_PAD_SFI_GPIO1_FUNC_GPIO016 0x0 +#define CIX_PAD_SFI_GPIO1_FUNC_SFI_SPI_MOSI 0x1 +#define CIX_PAD_SFI_GPIO1_FUNC_SFI_GPIO1 0x2 +#define CIX_PAD_SFI_GPIO2_FUNC_GPIO017 0x0 +#define CIX_PAD_SFI_GPIO2_FUNC_SFI_SPI_MISO 0x1 +#define CIX_PAD_SFI_GPIO2_FUNC_SFI_GPIO2 0x2 +#define CIX_PAD_GPIO018_FUNC_SFI_GPIO3 0x0 +#define CIX_PAD_GPIO018_FUNC_GPIO018 0x1 +#define CIX_PAD_GPIO019_FUNC_SFI_GPIO4 0x0 +#define CIX_PAD_GPIO019_FUNC_GPIO019 0x1 +#define CIX_PAD_GPIO020_FUNC_SFI_GPIO5 0x0 +#define CIX_PAD_GPIO020_FUNC_GPIO020 0x1 +#define CIX_PAD_GPIO021_FUNC_SFI_GPIO6 0x0 +#define CIX_PAD_GPIO021_FUNC_GPIO021 0x1 +#define CIX_PAD_GPIO022_FUNC_SFI_GPIO7 0x0 +#define CIX_PAD_GPIO022_FUNC_GPIO022 0x1 +#define CIX_PAD_GPIO023_FUNC_SFI_GPIO8 0x0 +#define CIX_PAD_GPIO023_FUNC_GPIO023 0x1 +#define CIX_PAD_GPIO023_FUNC_SFI_I3C0_PUR_EN_L 0x2 +#define CIX_PAD_GPIO024_FUNC_SFI_GPIO9 0x0 +#define CIX_PAD_GPIO024_FUNC_GPIO024 0x1 +#define CIX_PAD_GPIO024_FUNC_SFI_I3C1_PUR_EN_L 0x2 +#define CIX_PAD_SPI1_MISO_FUNC_SPI1_MISO 0x0 +#define CIX_PAD_SPI1_MISO_FUNC_GPIO025 0x1 +#define CIX_PAD_SPI1_CS0_FUNC_SPI1_CS0 0x0 +#define CIX_PAD_SPI1_CS0_FUNC_GPIO026 0x1 +#define CIX_PAD_SPI1_CS1_FUNC_SPI1_CS1 0x0 +#define CIX_PAD_SPI1_CS1_FUNC_GPIO027 0x1 +#define CIX_PAD_SPI1_MOSI_FUNC_SPI1_MOSI 0x0 +#define CIX_PAD_SPI1_MOSI_FUNC_GPIO028 0x1 +#define CIX_PAD_SPI1_CLK_FUNC_SPI1_CLK 0x0 +#define CIX_PAD_SPI1_CLK_FUNC_GPIO029 0x1 +#define CIX_PAD_GPIO030_FUNC_GPIO030 0x0 +#define CIX_PAD_GPIO030_FUNC_USB_OC0_L 0x1 +#define CIX_PAD_GPIO031_FUNC_GPIO031 0x0 +#define CIX_PAD_GPIO031_FUNC_USB_OC1_L 0x1 +#define CIX_PAD_GPIO032_FUNC_GPIO032 0x0 +#define CIX_PAD_GPIO032_FUNC_USB_OC2_L 0x1 +#define CIX_PAD_GPIO033_FUNC_GPIO033 0x0 +#define CIX_PAD_GPIO033_FUNC_USB_OC3_L 0x1 +#define CIX_PAD_GPIO034_FUNC_GPIO034 0x0 +#define CIX_PAD_GPIO034_FUNC_USB_OC4_L 0x1 +#define CIX_PAD_GPIO035_FUNC_GPIO035 0x0 +#define CIX_PAD_GPIO035_FUNC_USB_OC5_L 0x1 +#define CIX_PAD_GPIO036_FUNC_GPIO036 0x0 +#define CIX_PAD_GPIO036_FUNC_USB_OC6_L 0x1 +#define CIX_PAD_GPIO037_FUNC_GPIO037 0x0 +#define CIX_PAD_GPIO037_FUNC_USB_OC7_L 0x1 +#define CIX_PAD_GPIO038_FUNC_GPIO038 0x0 +#define CIX_PAD_GPIO038_FUNC_USB_OC8_L 0x1 +#define CIX_PAD_GPIO039_FUNC_GPIO039 0x0 +#define CIX_PAD_GPIO039_FUNC_USB_OC9_L 0x1 +#define CIX_PAD_GPIO040_FUNC_GPIO040 0x0 +#define CIX_PAD_GPIO040_FUNC_USB_DRIVE_VBUS0 0x1 +#define CIX_PAD_GPIO041_FUNC_GPIO041 0x0 +#define CIX_PAD_GPIO041_FUNC_USB_DRIVE_VBUS4 0x1 +#define CIX_PAD_GPIO042_FUNC_GPIO042 0x0 +#define CIX_PAD_GPIO042_FUNC_USB_DRIVE_VBUS5 0x1 +#define CIX_PAD_SE_QSPI_CLK_FUNC_SE_QSPI_CLK 0x0 +#define CIX_PAD_SE_QSPI_CLK_FUNC_QSPI_CLK 0x1 +#define CIX_PAD_SE_QSPI_CS_L_FUNC_SE_QSPI_CS_L 0x0 +#define CIX_PAD_SE_QSPI_CS_L_FUNC_QSPI_CS_L 0x1 +#define CIX_PAD_SE_QSPI_DATA0_FUNC_SE_QSPI_DATA0 0x0 +#define CIX_PAD_SE_QSPI_DATA0_FUNC_QSPI_DATA0 0x1 +#define CIX_PAD_SE_QSPI_DATA1_FUNC_SE_QSPI_DATA1 0x0 +#define CIX_PAD_SE_QSPI_DATA1_FUNC_QSPI_DATA1 0x1 +#define CIX_PAD_SE_QSPI_DATA2_FUNC_SE_QSPI_DATA2 0x0 +#define CIX_PAD_SE_QSPI_DATA2_FUNC_QSPI_DATA2 0x1 +#define CIX_PAD_SE_QSPI_DATA3_FUNC_SE_QSPI_DATA3 0x0 +#define CIX_PAD_SE_QSPI_DATA3_FUNC_QSPI_DATA3 0x1 +#define CIX_PAD_GPIO043_FUNC_GPIO043 0x0 +#define CIX_PAD_GPIO044_FUNC_GPIO044 0x0 +#define CIX_PAD_GPIO045_FUNC_GPIO045 0x0 +#define CIX_PAD_GPIO046_FUNC_GPIO046 0x0 +#define CIX_PAD_DP2_DIGON_FUNC_DP2_DIGON 0x0 +#define CIX_PAD_DP2_BLON_FUNC_DP2_BLON 0x0 +#define CIX_PAD_DP2_VARY_BL_FUNC_DP2_VARY_BL 0x0 +#define CIX_PAD_I2C7_SCL_FUNC_I2C7_SCL 0x0 +#define CIX_PAD_I2C7_SDA_FUNC_I2C7_SDA 0x0 +#define CIX_PAD_I2C5_SCL_FUNC_I2C5_SCL 0x0 +#define CIX_PAD_I2C5_SCL_FUNC_GPIO047 0x1 +#define CIX_PAD_I2C5_SDA_FUNC_I2C5_SDA 0x0 +#define CIX_PAD_I2C5_SDA_FUNC_GPIO048 0x1 +#define CIX_PAD_I2C6_SCL_FUNC_I2C6_SCL 0x0 +#define CIX_PAD_I2C6_SCL_FUNC_GPIO049 0x1 +#define CIX_PAD_I2C6_SDA_FUNC_I2C6_SDA 0x0 +#define CIX_PAD_I2C6_SDA_FUNC_GPIO050 0x1 +#define CIX_PAD_I2C0_CLK_FUNC_I2C0_CLK 0x0 +#define CIX_PAD_I2C0_CLK_FUNC_GPIO051 0x1 +#define CIX_PAD_I2C0_SDA_FUNC_I2C0_SDA 0x0 +#define CIX_PAD_I2C0_SDA_FUNC_GPIO052 0x1 +#define CIX_PAD_I2C1_CLK_FUNC_I2C1_CLK 0x0 +#define CIX_PAD_I2C1_CLK_FUNC_GPIO053 0x1 +#define CIX_PAD_I2C1_SDA_FUNC_I2C1_SDA 0x0 +#define CIX_PAD_I2C1_SDA_FUNC_GPIO054 0x1 +#define CIX_PAD_I2C2_SCL_FUNC_I2C2_SCL 0x0 +#define CIX_PAD_I2C2_SCL_FUNC_I3C0_SCL 0x1 +#define CIX_PAD_I2C2_SCL_FUNC_GPIO055 0x2 +#define CIX_PAD_I2C2_SDA_FUNC_I2C2_SDA 0x0 +#define CIX_PAD_I2C2_SDA_FUNC_I3C0_SDA 0x1 +#define CIX_PAD_I2C2_SDA_FUNC_GPIO056 0x2 +#define CIX_PAD_GPIO057_FUNC_GPIO057 0x0 +#define CIX_PAD_GPIO057_FUNC_I3C0_PUR_EN_L 0x1 +#define CIX_PAD_I2C3_CLK_FUNC_I2C3_CLK 0x0 +#define CIX_PAD_I2C3_CLK_FUNC_I3C1_CLK 0x1 +#define CIX_PAD_I2C3_CLK_FUNC_GPIO058 0x2 +#define CIX_PAD_I2C3_SDA_FUNC_I2C3_SDA 0x0 +#define CIX_PAD_I2C3_SDA_FUNC_I3C1_SDA 0x1 +#define CIX_PAD_I2C3_SDA_FUNC_GPIO059 0x2 +#define CIX_PAD_GPIO060_FUNC_GPIO060 0x0 +#define CIX_PAD_GPIO060_FUNC_I3C1_PUR_EN_L 0x1 +#define CIX_PAD_I2C4_CLK_FUNC_I2C4_CLK 0x0 +#define CIX_PAD_I2C4_CLK_FUNC_GPIO061 0x1 +#define CIX_PAD_I2C4_SDA_FUNC_I2C4_SDA 0x0 +#define CIX_PAD_I2C4_SDA_FUNC_GPIO062 0x1 +#define CIX_PAD_HDA_BITCLK_FUNC_HDA_BITCLK 0x0 +#define CIX_PAD_HDA_BITCLK_FUNC_I2S0_SCK 0x1 +#define CIX_PAD_HDA_BITCLK_FUNC_I2S9_RSCK_DBG 0x2 +#define CIX_PAD_HDA_RST_L_FUNC_HDA_RST_L 0x0 +#define CIX_PAD_HDA_RST_L_FUNC_I2S0_DATA_IN 0x1 +#define CIX_PAD_HDA_RST_L_FUNC_I2S9_DATA_IN0_DBG 0x2 +#define CIX_PAD_HDA_SDIN0_FUNC_HDA_SDIN0 0x0 +#define CIX_PAD_HDA_SDIN0_FUNC_I2S0_MCLK 0x1 +#define CIX_PAD_HDA_SDIN0_FUNC_I2S9_TSCK_DBG 0x2 +#define CIX_PAD_HDA_SDOUT0_FUNC_HDA_SDOUT0 0x0 +#define CIX_PAD_HDA_SDOUT0_FUNC_I2S0_DATA_OUT 0x1 +#define CIX_PAD_HDA_SDOUT0_FUNC_I2S9_TWS_DBG 0x2 +#define CIX_PAD_HDA_SYNC_FUNC_HDA_SYNC 0x0 +#define CIX_PAD_HDA_SYNC_FUNC_I2S0_WS 0x1 +#define CIX_PAD_HDA_SYNC_FUNC_I2S9_RWS_DBG 0x2 +#define CIX_PAD_HDA_SDIN1_FUNC_HDA_SDIN1 0x0 +#define CIX_PAD_HDA_SDIN1_FUNC_GPIO063 0x1 +#define CIX_PAD_HDA_SDIN1_FUNC_I2S9_DATA_IN1_DBG 0x2 +#define CIX_PAD_HDA_SDOUT1_FUNC_HDA_SDOUT1 0x0 +#define CIX_PAD_HDA_SDOUT1_FUNC_GPIO064 0x1 +#define CIX_PAD_HDA_SDOUT1_FUNC_I2S9_DATA_OUT0_DBG 0x2 +#define CIX_PAD_I2S1_MCLK_FUNC_I2S1_MCLK 0x0 +#define CIX_PAD_I2S1_MCLK_FUNC_GPIO065 0x1 +#define CIX_PAD_I2S1_SCK_FUNC_I2S1_SCK 0x0 +#define CIX_PAD_I2S1_SCK_FUNC_GPIO066 0x1 +#define CIX_PAD_I2S1_WS_FUNC_I2S1_WS 0x0 +#define CIX_PAD_I2S1_WS_FUNC_GPIO067 0x1 +#define CIX_PAD_I2S1_DATA_IN_FUNC_I2S1_DATA_IN 0x0 +#define CIX_PAD_I2S1_DATA_IN_FUNC_GPIO068 0x1 +#define CIX_PAD_I2S1_DATA_OUT_FUNC_I2S1_DATA_OUT 0x0 +#define CIX_PAD_I2S1_DATA_OUT_FUNC_GPIO069 0x1 +#define CIX_PAD_I2S2_MCLK_FUNC_I2S2_MCLK 0x0 +#define CIX_PAD_I2S2_MCLK_FUNC_GPIO070 0x1 +#define CIX_PAD_I2S2_RSCK_FUNC_I2S2_RSCK 0x0 +#define CIX_PAD_I2S2_RSCK_FUNC_GPIO071 0x1 +#define CIX_PAD_I2S2_RSCK_FUNC_I2S5_RSCK_DBG 0x2 +#define CIX_PAD_I2S2_RSCK_FUNC_I2S6_RSCK_DBG 0x3 +#define CIX_PAD_I2S2_RWS_FUNC_I2S2_RWS 0x0 +#define CIX_PAD_I2S2_RWS_FUNC_GPIO072 0x1 +#define CIX_PAD_I2S2_RWS_FUNC_I2S5_RWS_DBG 0x2 +#define CIX_PAD_I2S2_RWS_FUNC_I2S6_RWS_DBG 0x3 +#define CIX_PAD_I2S2_TSCK_FUNC_I2S2_TSCK 0x0 +#define CIX_PAD_I2S2_TSCK_FUNC_GPIO073 0x1 +#define CIX_PAD_I2S2_TSCK_FUNC_I2S5_TSCK_DBG 0x2 +#define CIX_PAD_I2S2_TSCK_FUNC_I2S6_TSCK_DBG 0x3 +#define CIX_PAD_I2S2_TWS_FUNC_I2S2_TWS 0x0 +#define CIX_PAD_I2S2_TWS_FUNC_GPIO074 0x1 +#define CIX_PAD_I2S2_TWS_FUNC_I2S5_TWS_DBG 0x2 +#define CIX_PAD_I2S2_TWS_FUNC_I2S6_TWS_DBG 0x3 +#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S2_DATA_IN0 0x0 +#define CIX_PAD_I2S2_DATA_IN0_FUNC_GPIO075 0x1 +#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S5_DATA_IN0_DBG 0x2 +#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S6_DATA_IN0_DBG 0x3 +#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S2_DATA_IN1 0x0 +#define CIX_PAD_I2S2_DATA_IN1_FUNC_GPIO076 0x1 +#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S5_DATA_IN1_DBG 0x2 +#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S6_DATA_IN1_DBG 0x3 +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S2_DATA_OUT0 0x0 +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_GPIO077 0x1 +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S5_DATA_OUT0_DBG 0x2 +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S6_DATA_OUT0_DBG 0x3 +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S2_DATA_OUT1 0x0 +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_GPIO078 0x1 +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S5_DATA_OUT1_DBG 0x2 +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S6_DATA_OUT1_DBG 0x3 +#define CIX_PAD_I2S2_DATA_OUT2_FUNC_I2S2_DATA_OUT2 0x0 +#define CIX_PAD_I2S2_DATA_OUT2_FUNC_GPIO079 0x1 +#define CIX_PAD_I2S2_DATA_OUT3_FUNC_I2S2_DATA_OUT3 0x0 +#define CIX_PAD_I2S2_DATA_OUT3_FUNC_GPIO080 0x1 +#define CIX_PAD_I2S2_DATA_OUT3_FUNC_I2S9_DATA_OUT1_DBG 0x2 +#define CIX_PAD_I2S3_MCLK_FUNC_I2S3_MCLK 0x0 +#define CIX_PAD_I2S3_MCLK_FUNC_GPIO081 0x1 +#define CIX_PAD_I2S3_RSCK_FUNC_I2S3_RSCK 0x0 +#define CIX_PAD_I2S3_RSCK_FUNC_GPIO082 0x1 +#define CIX_PAD_I2S3_RSCK_FUNC_I2S7_RSCK_DBG 0x2 +#define CIX_PAD_I2S3_RSCK_FUNC_I2S8_RSCK_DBG 0x3 +#define CIX_PAD_I2S3_RWS_FUNC_I2S3_RWS 0x0 +#define CIX_PAD_I2S3_RWS_FUNC_GPIO083 0x1 +#define CIX_PAD_I2S3_RWS_FUNC_I2S7_RWS_DBG 0x2 +#define CIX_PAD_I2S3_RWS_FUNC_I2S8_RWS_DBG 0x3 +#define CIX_PAD_I2S3_TSCK_FUNC_I2S3_TSCK 0x0 +#define CIX_PAD_I2S3_TSCK_FUNC_GPIO084 0x1 +#define CIX_PAD_I2S3_TSCK_FUNC_I2S7_TSCK_DBG 0x2 +#define CIX_PAD_I2S3_TSCK_FUNC_I2S8_TSCK_DBG 0x3 +#define CIX_PAD_I2S3_TWS_FUNC_I2S3_TWS 0x0 +#define CIX_PAD_I2S3_TWS_FUNC_GPIO085 0x1 +#define CIX_PAD_I2S3_TWS_FUNC_I2S7_TWS_DBG 0x2 +#define CIX_PAD_I2S3_TWS_FUNC_I2S8_TWS_DBG 0x3 +#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S3_DATA_IN0 0x0 +#define CIX_PAD_I2S3_DATA_IN0_FUNC_GPIO086 0x1 +#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S7_DATA_IN0_DBG 0x2 +#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S8_DATA_IN0_DBG 0x3 +#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S3_DATA_IN1 0x0 +#define CIX_PAD_I2S3_DATA_IN1_FUNC_GPIO087 0x1 +#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S7_DATA_IN1_DBG 0x2 +#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S8_DATA_IN1_DBG 0x3 +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S3_DATA_OUT0 0x0 +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_GPIO088 0x1 +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S7_DATA_OUT0_DBG 0x2 +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S8_DATA_OUT0_DBG 0x3 +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S3_DATA_OUT1 0x0 +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_GPIO089 0x1 +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S7_DATA_OUT1_DBG 0x2 +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S8_DATA_OUT1_DBG 0x3 +#define CIX_PAD_GPIO090_FUNC_GPIO090 0x0 +#define CIX_PAD_GPIO090_FUNC_I2S4_MCLK_LB 0x1 +#define CIX_PAD_GPIO091_FUNC_GPIO091 0x0 +#define CIX_PAD_GPIO091_FUNC_I2S4_SCK_LB 0x1 +#define CIX_PAD_GPIO092_FUNC_GPIO092 0x0 +#define CIX_PAD_GPIO092_FUNC_I2S4_WS_LB 0x1 +#define CIX_PAD_GPIO093_FUNC_GPIO093 0x0 +#define CIX_PAD_GPIO093_FUNC_I2S4_DATA_IN_LB 0x1 +#define CIX_PAD_GPIO094_FUNC_GPIO094 0x0 +#define CIX_PAD_GPIO094_FUNC_I2S4_DATA_OUT_LB 0x1 +#define CIX_PAD_UART0_TXD_FUNC_UART0_TXD 0x0 +#define CIX_PAD_UART0_TXD_FUNC_PWM0 0x1 +#define CIX_PAD_UART0_TXD_FUNC_GPIO095 0x2 +#define CIX_PAD_UART0_RXD_FUNC_UART0_RXD 0x0 +#define CIX_PAD_UART0_RXD_FUNC_PWM1 0x1 +#define CIX_PAD_UART0_RXD_FUNC_GPIO096 0x2 +#define CIX_PAD_UART0_CTS_FUNC_UART0_CTS 0x0 +#define CIX_PAD_UART0_CTS_FUNC_FAN_OUT2 0x1 +#define CIX_PAD_UART0_CTS_FUNC_GPIO097 0x2 +#define CIX_PAD_UART0_RTS_FUNC_UART0_RTS 0x0 +#define CIX_PAD_UART0_RTS_FUNC_FAN_TACH2 0x1 +#define CIX_PAD_UART0_RTS_FUNC_GPIO098 0x2 +#define CIX_PAD_UART1_TXD_FUNC_UART1_TXD 0x0 +#define CIX_PAD_UART1_TXD_FUNC_FAN_OUT0 0x1 +#define CIX_PAD_UART1_TXD_FUNC_GPIO099 0x2 +#define CIX_PAD_UART1_RXD_FUNC_UART1_RXD 0x0 +#define CIX_PAD_UART1_RXD_FUNC_FAN_TACH0 0x1 +#define CIX_PAD_UART1_RXD_FUNC_GPIO100 0x2 +#define CIX_PAD_UART1_CTS_FUNC_UART1_CTS 0x0 +#define CIX_PAD_UART1_CTS_FUNC_FAN_OUT1 0x1 +#define CIX_PAD_UART1_CTS_FUNC_GPIO101 0x2 +#define CIX_PAD_UART1_RTS_FUNC_UART1_RTS 0x0 +#define CIX_PAD_UART1_RTS_FUNC_FAN_TACH1 0x1 +#define CIX_PAD_UART1_RTS_FUNC_GPIO102 0x2 +#define CIX_PAD_UART2_TXD_FUNC_UART2_TXD 0x0 +#define CIX_PAD_UART2_TXD_FUNC_GPIO103 0x1 +#define CIX_PAD_UART2_RXD_FUNC_UART2_RXD 0x0 +#define CIX_PAD_UART2_RXD_FUNC_GPIO104 0x1 +#define CIX_PAD_UART3_TXD_FUNC_UART3_TXD 0x0 +#define CIX_PAD_UART3_TXD_FUNC_GPIO105 0x1 +#define CIX_PAD_UART3_RXD_FUNC_UART3_RXD 0x0 +#define CIX_PAD_UART3_RXD_FUNC_GPIO106 0x1 +#define CIX_PAD_UART3_CTS_FUNC_UART3_CTS 0x0 +#define CIX_PAD_UART3_CTS_FUNC_GPIO107 0x1 +#define CIX_PAD_UART3_CTS_FUNC_TRIGIN0 0x2 +#define CIX_PAD_UART3_RTS_FUNC_UART3_RTS 0x0 +#define CIX_PAD_UART3_RTS_FUNC_GPIO108 0x1 +#define CIX_PAD_UART3_RTS_FUNC_TRIGIN1 0x2 +#define CIX_PAD_UART4_CSU_PM_TXD_FUNC_UART4_CSU_PM_TXD 0x0 +#define CIX_PAD_UART4_CSU_PM_TXD_FUNC_GPIO109 0x1 +#define CIX_PAD_UART4_CSU_PM_RXD_FUNC_UART4_CSU_PM_RXD 0x0 +#define CIX_PAD_UART4_CSU_PM_RXD_FUNC_GPIO110 0x1 +#define CIX_PAD_UART5_CSU_SE_TXD_FUNC_UART5_CSU_SE_TXD 0x0 +#define CIX_PAD_UART5_CSU_SE_TXD_FUNC_GPIO111 0x1 +#define CIX_PAD_UART5_CSU_SE_RXD_FUNC_UART5_CSU_SE_RXD 0x0 +#define CIX_PAD_UART5_CSU_SE_RXD_FUNC_GPIO112 0x1 +#define CIX_PAD_UART6_CSU_SE_RXD_FUNC_UART6_CSU_SE_RXD 0x0 +#define CIX_PAD_UART6_CSU_SE_RXD_FUNC_GPIO113 0x1 +#define CIX_PAD_CLK_REQ0_L_FUNC_CLK_REQ0_L 0x0 +#define CIX_PAD_CLK_REQ0_L_FUNC_GPIO114 0x1 +#define CIX_PAD_CLK_REQ2_L_FUNC_CLK_REQ2_L 0x0 +#define CIX_PAD_CLK_REQ2_L_FUNC_GPIO115 0x1 +#define CIX_PAD_CLK_REQ4_L_FUNC_CLK_REQ4_L 0x0 +#define CIX_PAD_CLK_REQ4_L_FUNC_GPIO116 0x1 +#define CIX_PAD_CSI0_MCLK0_FUNC_CSI0_MCLK0 0x0 +#define CIX_PAD_CSI0_MCLK0_FUNC_GPIO117 0x1 +#define CIX_PAD_CSI0_MCLK1_FUNC_CSI0_MCLK1 0x0 +#define CIX_PAD_CSI0_MCLK1_FUNC_GPIO118 0x1 +#define CIX_PAD_CSI1_MCLK0_FUNC_CSI1_MCLK0 0x0 +#define CIX_PAD_CSI1_MCLK0_FUNC_GPIO119 0x1 +#define CIX_PAD_CSI1_MCLK1_FUNC_CSI1_MCLK1 0x0 +#define CIX_PAD_CSI1_MCLK1_FUNC_GPIO120 0x1 +#define CIX_PAD_GPIO121_FUNC_GPIO121 0x0 +#define CIX_PAD_GPIO121_FUNC_GMAC0_REFCLK_25M 0x1 +#define CIX_PAD_GPIO122_FUNC_GPIO122 0x0 +#define CIX_PAD_GPIO122_FUNC_GMAC0_TX_CTL 0x1 +#define CIX_PAD_GPIO123_FUNC_GPIO123 0x0 +#define CIX_PAD_GPIO123_FUNC_GMAC0_TXD0 0x1 +#define CIX_PAD_GPIO124_FUNC_GPIO124 0x0 +#define CIX_PAD_GPIO124_FUNC_GMAC0_TXD1 0x1 +#define CIX_PAD_GPIO125_FUNC_GPIO125 0x0 +#define CIX_PAD_GPIO125_FUNC_GMAC0_TXD2 0x1 +#define CIX_PAD_GPIO126_FUNC_GPIO126 0x0 +#define CIX_PAD_GPIO126_FUNC_GMAC0_TXD3 0x1 +#define CIX_PAD_GPIO127_FUNC_GPIO127 0x0 +#define CIX_PAD_GPIO127_FUNC_GMAC0_TX_CLK 0x1 +#define CIX_PAD_GPIO128_FUNC_GPIO128 0x0 +#define CIX_PAD_GPIO128_FUNC_GMAC0_RX_CTL 0x1 +#define CIX_PAD_GPIO129_FUNC_GPIO129 0x0 +#define CIX_PAD_GPIO129_FUNC_GMAC0_RXD0 0x1 +#define CIX_PAD_GPIO130_FUNC_GPIO130 0x0 +#define CIX_PAD_GPIO130_FUNC_GMAC0_RXD1 0x1 +#define CIX_PAD_GPIO131_FUNC_GPIO131 0x0 +#define CIX_PAD_GPIO131_FUNC_GMAC0_RXD2 0x1 +#define CIX_PAD_GPIO132_FUNC_GPIO132 0x0 +#define CIX_PAD_GPIO132_FUNC_GMAC0_RXD3 0x1 +#define CIX_PAD_GPIO133_FUNC_GPIO133 0x0 +#define CIX_PAD_GPIO133_FUNC_GMAC0_RX_CLK 0x1 +#define CIX_PAD_GPIO134_FUNC_GPIO134 0x0 +#define CIX_PAD_GPIO134_FUNC_GMAC0_MDC 0x1 +#define CIX_PAD_GPIO135_FUNC_GPIO135 0x0 +#define CIX_PAD_GPIO135_FUNC_GMAC0_MDIO 0x1 +#define CIX_PAD_GPIO136_FUNC_GPIO136 0x0 +#define CIX_PAD_GPIO136_FUNC_GMAC1_REFCLK_25M 0x1 +#define CIX_PAD_GPIO137_FUNC_GPIO137 0x0 +#define CIX_PAD_GPIO137_FUNC_GMAC1_TX_CTL 0x1 +#define CIX_PAD_GPIO138_FUNC_GPIO138 0x0 +#define CIX_PAD_GPIO138_FUNC_GMAC1_TXD0 0x1 +#define CIX_PAD_GPIO138_FUNC_SPI2_MISO 0x2 +#define CIX_PAD_GPIO139_FUNC_GPIO139 0x0 +#define CIX_PAD_GPIO139_FUNC_GMAC1_TXD1 0x1 +#define CIX_PAD_GPIO139_FUNC_SPI2_CS0 0x2 +#define CIX_PAD_GPIO140_FUNC_GPIO140 0x0 +#define CIX_PAD_GPIO140_FUNC_GMAC1_TXD2 0x1 +#define CIX_PAD_GPIO140_FUNC_SPI2_CS1 0x2 +#define CIX_PAD_GPIO141_FUNC_GPIO141 0x0 +#define CIX_PAD_GPIO141_FUNC_GMAC1_TXD3 0x1 +#define CIX_PAD_GPIO141_FUNC_SPI2_MOSI 0x2 +#define CIX_PAD_GPIO142_FUNC_GPIO142 0x0 +#define CIX_PAD_GPIO142_FUNC_GMAC1_TX_CLK 0x1 +#define CIX_PAD_GPIO142_FUNC_SPI2_CLK 0x2 +#define CIX_PAD_GPIO143_FUNC_GPIO143 0x0 +#define CIX_PAD_GPIO143_FUNC_GMAC1_RX_CTL 0x1 +#define CIX_PAD_GPIO144_FUNC_GPIO144 0x0 +#define CIX_PAD_GPIO144_FUNC_GMAC1_RXD0 0x1 +#define CIX_PAD_GPIO145_FUNC_GPIO145 0x0 +#define CIX_PAD_GPIO145_FUNC_GMAC1_RXD1 0x1 +#define CIX_PAD_GPIO146_FUNC_GPIO146 0x0 +#define CIX_PAD_GPIO146_FUNC_GMAC1_RXD2 0x1 +#define CIX_PAD_GPIO147_FUNC_GPIO147 0x0 +#define CIX_PAD_GPIO147_FUNC_GMAC1_RXD3 0x1 +#define CIX_PAD_GPIO148_FUNC_GPIO148 0x0 +#define CIX_PAD_GPIO148_FUNC_GMAC1_RX_CLK 0x1 +#define CIX_PAD_GPIO149_FUNC_GPIO149 0x0 +#define CIX_PAD_GPIO149_FUNC_GMAC1_MDC 0x1 +#define CIX_PAD_GPIO150_FUNC_GPIO150 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[172.16.64.196]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 1F30441C014B; Wed, 27 Aug 2025 10:42:23 +0800 (CST) From: Gary Yang To: linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, Gary Yang Subject: [PATCH 3/3] arm64: dts: cix: Add pinctrl nodes for sky1 Date: Wed, 27 Aug 2025 10:42:22 +0800 Message-ID: <20250827024222.588082-4-gary.yang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250827024222.588082-1-gary.yang@cixtech.com> References: <20250827024222.588082-1-gary.yang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CB:EE_|TYZPR06MB6144:EE_ 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OSA0EPF000000CB.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB6144 Content-Type: text/plain; charset="utf-8" Add the pin-controller nodes for Sky1 platform. Signed-off-by: Gary Yang --- arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 28 +++++++++++++++++++++++ arch/arm64/boot/dts/cix/sky1.dtsi | 10 ++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dt= s/cix/sky1-orion-o6.dts index d74964d53c3b..8fab0c3b36b3 100644 --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -7,6 +7,9 @@ /dts-v1/; =20 #include "sky1.dtsi" + +#include + / { model =3D "Radxa Orion O6"; compatible =3D "radxa,orion-o6", "cix,sky1"; @@ -34,6 +37,31 @@ linux,cma { =20 }; =20 +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_hog: hog-pins { + cix,pins =3D < + CIX_PAD_GPIO144_OFFSET CIX_PAD_GPIO144_FUNC_GPIO144 (PULL_DOWN|DS_LEVEL= 4) + CIX_PAD_GPIO145_OFFSET CIX_PAD_GPIO145_FUNC_GPIO145 (PULL_DOWN|DS_LEVEL= 4) + CIX_PAD_GPIO146_OFFSET CIX_PAD_GPIO146_FUNC_GPIO146 (PULL_DOWN|DS_LEVEL= 4) + CIX_PAD_GPIO147_OFFSET CIX_PAD_GPIO147_FUNC_GPIO147 (PULL_DOWN|DS_LEVEL= 4) + >; + }; +}; + +&iomuxc_s5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog_s5>; + + pinctrl_hog_s5: hog-s5-pins { + cix,pins =3D < + CIX_PAD_GPIO014_OFFSET CIX_PAD_GPIO014_FUNC_GPIO014 (PULL_UP|DS_LEVEL4) + >; + }; +}; + &uart2 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 7dfe7677e649..bfe34e5311e8 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -316,6 +316,16 @@ ppi_partition1: interrupt-partition-1 { }; }; }; + + iomuxc: pinctrl@4170000 { + compatible =3D "cix,sky1-iomuxc"; + reg =3D <0x0 0x04170000 0x0 0x1000>; + }; + + iomuxc_s5: pinctrl@16007000 { + compatible =3D "cix,sky1-iomuxc-s5"; + reg =3D <0x0 0x16007000 0x0 0x1000>; + }; }; =20 timer { --=20 2.49.0