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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:36:30.8553 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8570c809-5f44-4e82-a499-08dde50a2634 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9434 Content-Type: text/plain; charset="utf-8" cxl_handle_rdport_cor_ras() and cxl_handle_rdport_ras() are specific to Restricted CXL Host (RCH) handling. Improve readability and maintainability by replacing these and instead using the common cxl_handle_cor_ras() and cxl_handle_ras() functions. Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Dave Jiang --- Changes in v10->v11: - New patch --- drivers/cxl/core/ras.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 544a0d8773fa..0875ce8116ff 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -233,12 +233,6 @@ static void header_log_copy(void __iomem *ras_base, u3= 2 *log) } } =20 -static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, - struct cxl_dport *dport) -{ - return cxl_handle_cor_ras(cxlds, dport->regs.ras); -} - /* * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. @@ -276,12 +270,6 @@ static bool cxl_handle_ras(struct cxl_dev_state *cxlds= , void __iomem *ras_base) return true; } =20 -static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, - struct cxl_dport *dport) -{ - return cxl_handle_ras(cxlds, dport->regs.ras); -} - /* * Copy the AER capability registers using 32 bit read accesses. * This is necessary because RCRB AER capability is MMIO mapped. Clear the @@ -350,9 +338,9 @@ static void cxl_handle_rdport_errors(struct cxl_dev_sta= te *cxlds) =20 pci_print_aer(pdev, severity, &aer_regs); if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_rdport_cor_ras(cxlds, dport); + cxl_handle_cor_ras(cxlds, dport->regs.ras); else - cxl_handle_rdport_ras(cxlds, dport); + cxl_handle_ras(cxlds, dport->regs.ras); } =20 void cxl_cor_error_detected(struct pci_dev *pdev) --=20 2.51.0.rc2.21.ge5ab6b3e5a