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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:35:57.1133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da22ec8d-62ad-43fe-f33f-08dde50a1217 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8104 Content-Type: text/plain; charset="utf-8" From: Dave Jiang Create new config CONFIG_CXL_RAS and put all CXL RAS items behind the config. The config will depend on CPER and PCIE AER to build. Move the related RAS code from core/pci.c to core/ras.c. Cc: Robert Richter Cc: Terry Bowman Reviewed-by: Joshua Hahn Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang Reviewed-by: Dan Williams Reviewed-by: Alison Schofield Signed-off-by: Terry Bowman Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- - Updated by Terry Bowman to use (ACPI_APEI_GHES && PCIEAER_CXL) dependency in Kconfig. Otherwise checks will be reauired for CONFIG_PCIEAER because AER driver functions are called. --- drivers/cxl/Kconfig | 3 + drivers/cxl/core/Makefile | 2 +- drivers/cxl/core/core.h | 12 ++ drivers/cxl/core/pci.c | 319 -------------------------------------- drivers/cxl/core/ras.c | 311 +++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 8 - drivers/cxl/cxlpci.h | 16 ++ tools/testing/cxl/Kbuild | 2 +- 8 files changed, 344 insertions(+), 329 deletions(-) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 48b7314afdb8..1c7c8989fd8b 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -233,4 +233,7 @@ config CXL_MCE def_bool y depends on X86_MCE && MEMORY_FAILURE =20 +config CXL_RAS + def_bool y + depends on ACPI_APEI_GHES && PCIEAER_CXL endif diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 5ad8fef210b5..b2930cc54f8b 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -14,9 +14,9 @@ cxl_core-y +=3D pci.o cxl_core-y +=3D hdm.o cxl_core-y +=3D pmu.o cxl_core-y +=3D cdat.o -cxl_core-y +=3D ras.o cxl_core-$(CONFIG_TRACING) +=3D trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D region.o cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o +cxl_core-$(CONFIG_CXL_RAS) +=3D ras.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 2669f251d677..2c81a43d7b05 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -143,8 +143,20 @@ bool cxl_need_node_perf_attrs_update(int nid); int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, struct access_coordinate *c); =20 +#ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); +#else +static inline int cxl_ras_init(void) +{ + return 0; +} + +static inline void cxl_ras_exit(void) +{ +} +#endif // CONFIG_CXL_RAS + int cxl_gpf_port_setup(struct cxl_dport *dport); =20 #ifdef CONFIG_CXL_FEATURES diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index b50551601c2e..a3aef78f903a 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -664,324 +663,6 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); =20 -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) -{ - void __iomem *addr; - u32 status; - - if (!ras_base) - return; - - addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; - status =3D readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); - } -} - -static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); -} - -/* CXL spec rev3.0 8.2.4.16.1 */ -static void header_log_copy(void __iomem *ras_base, u32 *log) -{ - void __iomem *addr; - u32 *log_addr; - int i, log_u32_size =3D CXL_HEADERLOG_SIZE / sizeof(u32); - - addr =3D ras_base + CXL_RAS_HEADER_LOG_OFFSET; - log_addr =3D log; - - for (i =3D 0; i < log_u32_size; i++) { - *log_addr =3D readl(addr); - log_addr++; - addr +=3D sizeof(u32); - } -} - -/* - * Log the state of the RAS status registers and prepare them to log the - * next error status. Return 1 if reset needed. - */ -static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) -{ - u32 hl[CXL_HEADERLOG_SIZE_U32]; - void __iomem *addr; - u32 status; - u32 fe; - - if (!ras_base) - return false; - - addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; - status =3D readl(addr); - if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) - return false; - - /* If multiple errors, log header points to first error from ctrl reg */ - if (hweight32(status) > 1) { - void __iomem *rcc_addr =3D - ras_base + CXL_RAS_CAP_CONTROL_OFFSET; - - fe =3D BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, - readl(rcc_addr))); - } else { - fe =3D status; - } - - header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); - writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); - - return true; -} - -static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_ras(cxlds, cxlds->regs.ras); -} - -#ifdef CONFIG_PCIEAER_CXL - -static void cxl_dport_map_rch_aer(struct cxl_dport *dport) -{ - resource_size_t aer_phys; - struct device *host; - u16 aer_cap; - - aer_cap =3D cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base); - if (aer_cap) { - host =3D dport->reg_map.host; - aer_phys =3D aer_cap + dport->rcrb.base; - dport->regs.dport_aer =3D devm_cxl_iomap_block(host, aer_phys, - sizeof(struct aer_capability_regs)); - } -} - -static void cxl_dport_map_ras(struct cxl_dport *dport) -{ - struct cxl_register_map *map =3D &dport->reg_map; - struct device *dev =3D dport->dport_dev; - - if (!map->component_map.ras.valid) - dev_dbg(dev, "RAS registers not found\n"); - else if (cxl_map_component_regs(map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) - dev_dbg(dev, "Failed to map RAS capability.\n"); -} - -static void cxl_disable_rch_root_ints(struct cxl_dport *dport) -{ - void __iomem *aer_base =3D dport->regs.dport_aer; - u32 aer_cmd_mask, aer_cmd; - - if (!aer_base) - return; - - /* - * Disable RCH root port command interrupts. - * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors - * - * This sequence may not be necessary. CXL spec states disabling - * the root cmd register's interrupts is required. But, PCI spec - * shows these are disabled by default on reset. - */ - aer_cmd_mask =3D (PCI_ERR_ROOT_CMD_COR_EN | - PCI_ERR_ROOT_CMD_NONFATAL_EN | - PCI_ERR_ROOT_CMD_FATAL_EN); - aer_cmd =3D readl(aer_base + PCI_ERR_ROOT_COMMAND); - aer_cmd &=3D ~aer_cmd_mask; - writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); -} - -/** - * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport - * @dport: the cxl_dport that needs to be initialized - * @host: host device for devm operations - */ -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) -{ - dport->reg_map.host =3D host; - cxl_dport_map_ras(dport); - - if (dport->rch) { - struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); - - if (!host_bridge->native_aer) - return; - - cxl_dport_map_rch_aer(dport); - cxl_disable_rch_root_ints(dport); - } -} -EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); - -static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, - struct cxl_dport *dport) -{ - return __cxl_handle_cor_ras(cxlds, dport->regs.ras); -} - -static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, - struct cxl_dport *dport) -{ - return __cxl_handle_ras(cxlds, dport->regs.ras); -} - -/* - * Copy the AER capability registers using 32 bit read accesses. - * This is necessary because RCRB AER capability is MMIO mapped. Clear the - * status after copying. - * - * @aer_base: base address of AER capability block in RCRB - * @aer_regs: destination for copying AER capability - */ -static bool cxl_rch_get_aer_info(void __iomem *aer_base, - struct aer_capability_regs *aer_regs) -{ - int read_cnt =3D sizeof(struct aer_capability_regs) / sizeof(u32); - u32 *aer_regs_buf =3D (u32 *)aer_regs; - int n; - - if (!aer_base) - return false; - - /* Use readl() to guarantee 32-bit accesses */ - for (n =3D 0; n < read_cnt; n++) - aer_regs_buf[n] =3D readl(aer_base + n * sizeof(u32)); - - writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS); - writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS); - - return true; -} - -/* Get AER severity. Return false if there is no error. */ -static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, - int *severity) -{ - if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { - if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) - *severity =3D AER_FATAL; - else - *severity =3D AER_NONFATAL; - return true; - } - - if (aer_regs->cor_status & ~aer_regs->cor_mask) { - *severity =3D AER_CORRECTABLE; - return true; - } - - return false; -} - -static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) -{ - struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); - struct aer_capability_regs aer_regs; - struct cxl_dport *dport; - int severity; - - struct cxl_port *port __free(put_cxl_port) =3D - cxl_pci_find_port(pdev, &dport); - if (!port) - return; - - if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs)) - return; - - if (!cxl_rch_get_aer_severity(&aer_regs, &severity)) - return; - - pci_print_aer(pdev, severity, &aer_regs); - - if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_rdport_cor_ras(cxlds, dport); - else - cxl_handle_rdport_ras(cxlds, dport); -} - -#else -static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { } -#endif - -void cxl_cor_error_detected(struct pci_dev *pdev) -{ - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct device *dev =3D &cxlds->cxlmd->dev; - - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return; - } - - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - - cxl_handle_endpoint_cor_ras(cxlds); - } -} -EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); - -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) -{ - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlmd->dev; - bool ue; - - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; - } - - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. - */ - ue =3D cxl_handle_endpoint_ras(cxlds); - } - - - switch (state) { - case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: - dev_warn(&pdev->dev, - "%s: frozen state error detected, disable CXL.mem\n", - dev_name(dev)); - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - dev_warn(&pdev->dev, - "failure state error detected, request disconnect\n"); - return PCI_ERS_RESULT_DISCONNECT; - } - return PCI_ERS_RESULT_NEED_RESET; -} -EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); - static int cxl_flit_size(struct pci_dev *pdev) { if (cxl_pci_flit_256(pdev)) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 2731ba3a0799..c4f0fa7e40aa 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "trace.h" =20 static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev, @@ -124,3 +125,313 @@ void cxl_ras_exit(void) cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); cancel_work_sync(&cxl_cper_prot_err_work); } + +static void cxl_dport_map_rch_aer(struct cxl_dport *dport) +{ + resource_size_t aer_phys; + struct device *host; + u16 aer_cap; + + aer_cap =3D cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base); + if (aer_cap) { + host =3D dport->reg_map.host; + aer_phys =3D aer_cap + dport->rcrb.base; + dport->regs.dport_aer =3D devm_cxl_iomap_block(host, aer_phys, + sizeof(struct aer_capability_regs)); + } +} + +static void cxl_dport_map_ras(struct cxl_dport *dport) +{ + struct cxl_register_map *map =3D &dport->reg_map; + struct device *dev =3D dport->dport_dev; + + if (!map->component_map.ras.valid) + dev_dbg(dev, "RAS registers not found\n"); + else if (cxl_map_component_regs(map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(dev, "Failed to map RAS capability.\n"); +} + +static void cxl_disable_rch_root_ints(struct cxl_dport *dport) +{ + void __iomem *aer_base =3D dport->regs.dport_aer; + u32 aer_cmd_mask, aer_cmd; + + if (!aer_base) + return; + + /* + * Disable RCH root port command interrupts. + * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors + * + * This sequence may not be necessary. CXL spec states disabling + * the root cmd register's interrupts is required. But, PCI spec + * shows these are disabled by default on reset. + */ + aer_cmd_mask =3D (PCI_ERR_ROOT_CMD_COR_EN | + PCI_ERR_ROOT_CMD_NONFATAL_EN | + PCI_ERR_ROOT_CMD_FATAL_EN); + aer_cmd =3D readl(aer_base + PCI_ERR_ROOT_COMMAND); + aer_cmd &=3D ~aer_cmd_mask; + writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); +} + + +/** + * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport + * @dport: the cxl_dport that needs to be initialized + * @host: host device for devm operations + */ +void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) +{ + dport->reg_map.host =3D host; + cxl_dport_map_ras(dport); + + if (dport->rch) { + struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); + + if (!host_bridge->native_aer) + return; + + cxl_dport_map_rch_aer(dport); + cxl_disable_rch_root_ints(dport); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); + +static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem= *ras_base) +{ + void __iomem *addr; + u32 status; + + if (!ras_base) + return; + + addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; + status =3D readl(addr); + if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + } +} + +/* CXL spec rev3.0 8.2.4.16.1 */ +static void header_log_copy(void __iomem *ras_base, u32 *log) +{ + void __iomem *addr; + u32 *log_addr; + int i, log_u32_size =3D CXL_HEADERLOG_SIZE / sizeof(u32); + + addr =3D ras_base + CXL_RAS_HEADER_LOG_OFFSET; + log_addr =3D log; + + for (i =3D 0; i < log_u32_size; i++) { + *log_addr =3D readl(addr); + log_addr++; + addr +=3D sizeof(u32); + } +} + +static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, + struct cxl_dport *dport) +{ + return __cxl_handle_cor_ras(cxlds, dport->regs.ras); +} + +/* + * Log the state of the RAS status registers and prepare them to log the + * next error status. Return 1 if reset needed. + */ +static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ra= s_base) +{ + u32 hl[CXL_HEADERLOG_SIZE_U32]; + void __iomem *addr; + u32 status; + u32 fe; + + if (!ras_base) + return false; + + addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; + status =3D readl(addr); + if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) + return false; + + /* If multiple errors, log header points to first error from ctrl reg */ + if (hweight32(status) > 1) { + void __iomem *rcc_addr =3D + ras_base + CXL_RAS_CAP_CONTROL_OFFSET; + + fe =3D BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, + readl(rcc_addr))); + } else { + fe =3D status; + } + + header_log_copy(ras_base, hl); + trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); + writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); + + return true; +} + +static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, + struct cxl_dport *dport) +{ + return __cxl_handle_ras(cxlds, dport->regs.ras); +} + +/* + * Copy the AER capability registers using 32 bit read accesses. + * This is necessary because RCRB AER capability is MMIO mapped. Clear the + * status after copying. + * + * @aer_base: base address of AER capability block in RCRB + * @aer_regs: destination for copying AER capability + */ +static bool cxl_rch_get_aer_info(void __iomem *aer_base, + struct aer_capability_regs *aer_regs) +{ + int read_cnt =3D sizeof(struct aer_capability_regs) / sizeof(u32); + u32 *aer_regs_buf =3D (u32 *)aer_regs; + int n; + + if (!aer_base) + return false; + + /* Use readl() to guarantee 32-bit accesses */ + for (n =3D 0; n < read_cnt; n++) + aer_regs_buf[n] =3D readl(aer_base + n * sizeof(u32)); + + writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS); + writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS); + + return true; +} + +/* Get AER severity. Return false if there is no error. */ +static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, + int *severity) +{ + if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { + if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) + *severity =3D AER_FATAL; + else + *severity =3D AER_NONFATAL; + return true; + } + + if (aer_regs->cor_status & ~aer_regs->cor_mask) { + *severity =3D AER_CORRECTABLE; + return true; + } + + return false; +} + +static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) +{ + struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); + struct aer_capability_regs aer_regs; + struct cxl_dport *dport; + int severity; + + struct cxl_port *port __free(put_cxl_port) =3D + cxl_pci_find_port(pdev, &dport); + if (!port) + return; + + if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs)) + return; + + if (!cxl_rch_get_aer_severity(&aer_regs, &severity)) + return; + + pci_print_aer(pdev, severity, &aer_regs); + if (severity =3D=3D AER_CORRECTABLE) + cxl_handle_rdport_cor_ras(cxlds, dport); + else + cxl_handle_rdport_ras(cxlds, dport); +} + +static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) +{ + return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); +} + +static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) +{ + return __cxl_handle_ras(cxlds, cxlds->regs.ras); +} + +void cxl_cor_error_detected(struct pci_dev *pdev) +{ + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct device *dev =3D &cxlds->cxlmd->dev; + + scoped_guard(device, dev) { + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + cxl_handle_endpoint_cor_ras(cxlds); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); + +pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct cxl_memdev *cxlmd =3D cxlds->cxlmd; + struct device *dev =3D &cxlmd->dev; + bool ue; + + scoped_guard(device, dev) { + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return PCI_ERS_RESULT_DISCONNECT; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + /* + * A frozen channel indicates an impending reset which is fatal to + * CXL.mem operation, and will likely crash the system. On the off + * chance the situation is recoverable dump the status of the RAS + * capability registers and bounce the active state of the memdev. + */ + ue =3D cxl_handle_endpoint_ras(cxlds); + } + + + switch (state) { + case pci_channel_io_normal: + if (ue) { + device_release_driver(dev); + return PCI_ERS_RESULT_NEED_RESET; + } + return PCI_ERS_RESULT_CAN_RECOVER; + case pci_channel_io_frozen: + dev_warn(&pdev->dev, + "%s: frozen state error detected, disable CXL.mem\n", + dev_name(dev)); + device_release_driver(dev); + return PCI_ERS_RESULT_NEED_RESET; + case pci_channel_io_perm_failure: + dev_warn(&pdev->dev, + "failure state error detected, request disconnect\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + return PCI_ERS_RESULT_NEED_RESET; +} +EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index b7111e3568d0..8f6224ac6785 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -761,14 +761,6 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_po= rt *port, struct device *dport_dev, int port_id, resource_size_t rcrb); =20 -#ifdef CONFIG_PCIEAER_CXL -void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); -#else -static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, - struct device *host) { } -#endif - struct cxl_decoder *to_cxl_decoder(struct device *dev); struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 54e219b0049e..3959fa7e2ead 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -132,7 +132,23 @@ struct cxl_dev_state; int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhd= m, struct cxl_endpoint_dvsec_info *info); void read_cdat_data(struct cxl_port *port); + +#ifdef CONFIG_CXL_RAS void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); +#else +static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } + +static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + return PCI_ERS_RESULT_NONE; +} + +static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, + struct device *host) { } +#endif + #endif /* __CXL_PCI_H__ */ diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index d07f14cb7aa4..385301aeaeb3 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -61,12 +61,12 @@ cxl_core-y +=3D $(CXL_CORE_SRC)/pci.o cxl_core-y +=3D $(CXL_CORE_SRC)/hdm.o cxl_core-y +=3D $(CXL_CORE_SRC)/pmu.o cxl_core-y +=3D $(CXL_CORE_SRC)/cdat.o -cxl_core-y +=3D $(CXL_CORE_SRC)/ras.o cxl_core-$(CONFIG_TRACING) +=3D $(CXL_CORE_SRC)/trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D $(CXL_CORE_SRC)/region.o cxl_core-$(CONFIG_CXL_MCE) +=3D $(CXL_CORE_SRC)/mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D $(CXL_CORE_SRC)/features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D $(CXL_CORE_SRC)/edac.o +cxl_core-$(CONFIG_CXL_RAS) +=3D $(CXL_CORE_SRC)/ras.o cxl_core-y +=3D config_check.o cxl_core-y +=3D cxl_core_test.o cxl_core-y +=3D cxl_core_exports.o --=20 2.51.0.rc2.21.ge5ab6b3e5a From nobody Fri Oct 3 18:01:56 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2062.outbound.protection.outlook.com [40.107.94.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C80251F8747; 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Tue, 26 Aug 2025 20:36:06 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v11 02/23] CXL/AER: Remove CONFIG_PCIEAER_CXL and replace with CONFIG_CXL_RAS Date: Tue, 26 Aug 2025 20:35:17 -0500 Message-ID: <20250827013539.903682-3-terry.bowman@amd.com> X-Mailer: git-send-email 2.51.0.rc2.21.ge5ab6b3e5a In-Reply-To: <20250827013539.903682-1-terry.bowman@amd.com> References: <20250827013539.903682-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE5:EE_|CH3PR12MB7572:EE_ X-MS-Office365-Filtering-Correlation-Id: 9cf547ee-3428-42cc-76e4-08dde50a1888 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024|921020|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:36:07.9154 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9cf547ee-3428-42cc-76e4-08dde50a1888 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7572 Content-Type: text/plain; charset="utf-8" CXL RAS compilation is enabled using CONFIG_CXL_RAS while the AER CXL logic uses CONFIG_PCIEAER_CXL. The 2 share the same dependencies and can be combined. The 2 kernel configs are unnecessary and are problematic for the user because of the duplication. Replace occurrences of CONFIG_PCIEAER_CXL to be CONFIG_CXL_RAS. Update the CONFIG_CXL_RAS Kconfig definition to include dependencies 'PCIEA= ER && CXL_PCI' taken from the CONFIG_PCIEAER_CXL definition. Remove the Kconfig CONFIG_PCIEAER_CXL definition. Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10 -> v11: - New patch --- drivers/pci/pcie/Kconfig | 9 --------- drivers/pci/pcie/aer.c | 2 +- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig index 17919b99fa66..207c2deae35f 100644 --- a/drivers/pci/pcie/Kconfig +++ b/drivers/pci/pcie/Kconfig @@ -49,15 +49,6 @@ config PCIEAER_INJECT gotten from: https://github.com/intel/aer-inject.git =20 -config PCIEAER_CXL - bool "PCI Express CXL RAS support" - default y - depends on PCIEAER && CXL_PCI - help - Enables CXL error handling. - - If unsure, say Y. - # # PCI Express ECRC # diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 70ac66188367..7fe9f883f5c5 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1086,7 +1086,7 @@ static bool find_source_device(struct pci_dev *parent, return true; } =20 -#ifdef CONFIG_PCIEAER_CXL +#ifdef CONFIG_CXL_RAS =20 /** * pci_aer_unmask_internal_errors - unmask internal errors --=20 2.51.0.rc2.21.ge5ab6b3e5a From nobody Fri Oct 3 18:01:56 2025 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2074.outbound.protection.outlook.com [40.107.223.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 984091C1F12; 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Tue, 26 Aug 2025 20:36:18 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v11 03/23] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Date: Tue, 26 Aug 2025 20:35:18 -0500 Message-ID: <20250827013539.903682-4-terry.bowman@amd.com> X-Mailer: git-send-email 2.51.0.rc2.21.ge5ab6b3e5a In-Reply-To: <20250827013539.903682-1-terry.bowman@amd.com> References: <20250827013539.903682-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|SA1PR12MB6774:EE_ X-MS-Office365-Filtering-Correlation-Id: 76c100bc-9e0f-493b-88f3-08dde50a1f51 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|7416014|30052699003|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:36:19.3006 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76c100bc-9e0f-493b-88f3-08dde50a1f51 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6774 Content-Type: text/plain; charset="utf-8" The CXL driver's cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras() are unnecessary helper functions used only for Endpoints. Remove these functions as they are not common for all CXL devices and do not provide value for EP handling. Rename __cxl_handle_ras to cxl_handle_ras() and __cxl_handle_cor_ras() to cxl_handle_cor_ras(). Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - None --- drivers/cxl/core/ras.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index c4f0fa7e40aa..544a0d8773fa 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -200,7 +200,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt, struct device *host) } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem= *ras_base) +static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *= ras_base) { void __iomem *addr; u32 status; @@ -236,14 +236,14 @@ static void header_log_copy(void __iomem *ras_base, u= 32 *log) static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_cor_ras(cxlds, dport->regs.ras); + return cxl_handle_cor_ras(cxlds, dport->regs.ras); } =20 /* * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ra= s_base) +static bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_= base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -279,7 +279,7 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxld= s, void __iomem *ras_base static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_ras(cxlds, dport->regs.ras); + return cxl_handle_ras(cxlds, dport->regs.ras); } =20 /* @@ -355,16 +355,6 @@ static void cxl_handle_rdport_errors(struct cxl_dev_st= ate *cxlds) cxl_handle_rdport_ras(cxlds, dport); } =20 -static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); -} - -static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_ras(cxlds, cxlds->regs.ras); -} - void cxl_cor_error_detected(struct pci_dev *pdev) { struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); @@ -381,7 +371,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_endpoint_cor_ras(cxlds); + cxl_handle_cor_ras(cxlds, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -410,7 +400,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_endpoint_ras(cxlds); + ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); } =20 =20 --=20 2.51.0.rc2.21.ge5ab6b3e5a From nobody Fri Oct 3 18:01:56 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2086.outbound.protection.outlook.com [40.107.244.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CACDC1D63F5; Wed, 27 Aug 2025 01:36:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 26 Aug 2025 20:36:29 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v11 04/23] cxl/pci: Remove unnecessary CXL RCH handling helper functions Date: Tue, 26 Aug 2025 20:35:19 -0500 Message-ID: <20250827013539.903682-5-terry.bowman@amd.com> X-Mailer: git-send-email 2.51.0.rc2.21.ge5ab6b3e5a In-Reply-To: <20250827013539.903682-1-terry.bowman@amd.com> References: <20250827013539.903682-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE4:EE_|DM3PR12MB9434:EE_ X-MS-Office365-Filtering-Correlation-Id: 8570c809-5f44-4e82-a499-08dde50a2634 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:36:30.8553 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8570c809-5f44-4e82-a499-08dde50a2634 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9434 Content-Type: text/plain; charset="utf-8" cxl_handle_rdport_cor_ras() and cxl_handle_rdport_ras() are specific to Restricted CXL Host (RCH) handling. Improve readability and maintainability by replacing these and instead using the common cxl_handle_cor_ras() and cxl_handle_ras() functions. Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Dave Jiang Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - New patch --- drivers/cxl/core/ras.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 544a0d8773fa..0875ce8116ff 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -233,12 +233,6 @@ static void header_log_copy(void __iomem *ras_base, u3= 2 *log) } } =20 -static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, - struct cxl_dport *dport) -{ - return cxl_handle_cor_ras(cxlds, dport->regs.ras); -} - /* * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. @@ -276,12 +270,6 @@ static bool cxl_handle_ras(struct cxl_dev_state *cxlds= , void __iomem *ras_base) return true; } =20 -static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, - struct cxl_dport *dport) -{ - return cxl_handle_ras(cxlds, dport->regs.ras); -} - /* * Copy the AER capability registers using 32 bit read accesses. * This is necessary because RCRB AER capability is MMIO mapped. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:36:41.6442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 84f663e9-4f2a-4e33-0ddd-08dde50a2ca3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6712 Content-Type: text/plain; charset="utf-8" Restricted CXL Host (RCH) protocol error handling uses a procedure distinct from the CXL Virtual Hierarchy (VH) handling. This is because of the differences in the RCH and VH topologies. Improve the maintainability and add ability to enable/disable RCH handling. Move and combine the RCH handling code into a single block conditionally compiled with the CONFIG_CXL_RCH_RAS kernel config. Signed-off-by: Terry Bowman Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- v10->v11: - New patch --- drivers/cxl/core/ras.c | 175 +++++++++++++++++++++-------------------- 1 file changed, 90 insertions(+), 85 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 0875ce8116ff..f42f9a255ef8 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -126,6 +126,7 @@ void cxl_ras_exit(void) cancel_work_sync(&cxl_cper_prot_err_work); } =20 +#ifdef CONFIG_CXL_RCH_RAS static void cxl_dport_map_rch_aer(struct cxl_dport *dport) { resource_size_t aer_phys; @@ -141,18 +142,6 @@ static void cxl_dport_map_rch_aer(struct cxl_dport *dp= ort) } } =20 -static void cxl_dport_map_ras(struct cxl_dport *dport) -{ - struct cxl_register_map *map =3D &dport->reg_map; - struct device *dev =3D dport->dport_dev; - - if (!map->component_map.ras.valid) - dev_dbg(dev, "RAS registers not found\n"); - else if (cxl_map_component_regs(map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) - dev_dbg(dev, "Failed to map RAS capability.\n"); -} - static void cxl_disable_rch_root_ints(struct cxl_dport *dport) { void __iomem *aer_base =3D dport->regs.dport_aer; @@ -177,6 +166,95 @@ static void cxl_disable_rch_root_ints(struct cxl_dport= *dport) writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } =20 +/* + * Copy the AER capability registers using 32 bit read accesses. + * This is necessary because RCRB AER capability is MMIO mapped. Clear the + * status after copying. + * + * @aer_base: base address of AER capability block in RCRB + * @aer_regs: destination for copying AER capability + */ +static bool cxl_rch_get_aer_info(void __iomem *aer_base, + struct aer_capability_regs *aer_regs) +{ + int read_cnt =3D sizeof(struct aer_capability_regs) / sizeof(u32); + u32 *aer_regs_buf =3D (u32 *)aer_regs; + int n; + + if (!aer_base) + return false; + + /* Use readl() to guarantee 32-bit accesses */ + for (n =3D 0; n < read_cnt; n++) + aer_regs_buf[n] =3D readl(aer_base + n * sizeof(u32)); + + writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS); + writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS); + + return true; +} + +/* Get AER severity. Return false if there is no error. */ +static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, + int *severity) +{ + if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { + if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) + *severity =3D AER_FATAL; + else + *severity =3D AER_NONFATAL; + return true; + } + + if (aer_regs->cor_status & ~aer_regs->cor_mask) { + *severity =3D AER_CORRECTABLE; + return true; + } + + return false; +} + +static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) +{ + struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); + struct aer_capability_regs aer_regs; + struct cxl_dport *dport; + int severity; + + struct cxl_port *port __free(put_cxl_port) =3D + cxl_pci_find_port(pdev, &dport); + if (!port) + return; + + if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs)) + return; + + if (!cxl_rch_get_aer_severity(&aer_regs, &severity)) + return; + + pci_print_aer(pdev, severity, &aer_regs); + if (severity =3D=3D AER_CORRECTABLE) + cxl_handle_cor_ras(cxlds, dport->regs.ras); + else + cxl_handle_ras(cxlds, dport->regs.ras); +} +#else +static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } +static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } +static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } +#endif + +static void cxl_dport_map_ras(struct cxl_dport *dport) +{ + struct cxl_register_map *map =3D &dport->reg_map; + struct device *dev =3D dport->dport_dev; + + if (!map->component_map.ras.valid) + dev_dbg(dev, "RAS registers not found\n"); + else if (cxl_map_component_regs(map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(dev, "Failed to map RAS capability.\n"); +} =20 /** * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport @@ -270,79 +348,6 @@ static bool cxl_handle_ras(struct cxl_dev_state *cxlds= , void __iomem *ras_base) return true; } =20 -/* - * Copy the AER capability registers using 32 bit read accesses. - * This is necessary because RCRB AER capability is MMIO mapped. Clear the - * status after copying. - * - * @aer_base: base address of AER capability block in RCRB - * @aer_regs: destination for copying AER capability - */ -static bool cxl_rch_get_aer_info(void __iomem *aer_base, - struct aer_capability_regs *aer_regs) -{ - int read_cnt =3D sizeof(struct aer_capability_regs) / sizeof(u32); - u32 *aer_regs_buf =3D (u32 *)aer_regs; - int n; - - if (!aer_base) - return false; - - /* Use readl() to guarantee 32-bit accesses */ - for (n =3D 0; n < read_cnt; n++) - aer_regs_buf[n] =3D readl(aer_base + n * sizeof(u32)); - - writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS); - writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS); - - return true; -} - -/* Get AER severity. Return false if there is no error. */ -static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, - int *severity) -{ - if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { - if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) - *severity =3D AER_FATAL; - else - *severity =3D AER_NONFATAL; - return true; - } - - if (aer_regs->cor_status & ~aer_regs->cor_mask) { - *severity =3D AER_CORRECTABLE; - return true; - } - - return false; -} - -static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) -{ - struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); - struct aer_capability_regs aer_regs; - struct cxl_dport *dport; - int severity; - - struct cxl_port *port __free(put_cxl_port) =3D - cxl_pci_find_port(pdev, &dport); - if (!port) - return; - - if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs)) - return; - - if (!cxl_rch_get_aer_severity(&aer_regs, &severity)) - return; - - pci_print_aer(pdev, severity, &aer_regs); - if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(cxlds, dport->regs.ras); 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CEA.mail.protection.outlook.com (10.167.242.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.9073.11 via Frontend Transport; Wed, 27 Aug 2025 01:36:52 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 26 Aug 2025 20:36:51 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v11 06/23] CXL/AER: Introduce rch_aer.c into AER driver for handling CXL RCH errors Date: Tue, 26 Aug 2025 20:35:21 -0500 Message-ID: <20250827013539.903682-7-terry.bowman@amd.com> X-Mailer: git-send-email 2.51.0.rc2.21.ge5ab6b3e5a In-Reply-To: <20250827013539.903682-1-terry.bowman@amd.com> References: <20250827013539.903682-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|LV8PR12MB9261:EE_ X-MS-Office365-Filtering-Correlation-Id: 5fc53df3-0ea0-429e-df91-08dde50a3337 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|7416014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:36:52.6873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5fc53df3-0ea0-429e-df91-08dde50a3337 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9261 Content-Type: text/plain; charset="utf-8" The restricted CXL Host (RCH) AER error handling logic currently resides in the AER driver file, drivers/pci/pcie/aer.c. CXL specific changes are conditionally compiled using #ifdefs. Improve the AER driver maintainability by separating the RCH specific logic from the AER driver's core functionality and removing the ifdefs. Introduce drivers/pci/pcie/rch_aer.c for moving the RCH AER logic into. Move the CXL logic into the new file but leave helper functions in aer.c for now as they will be moved in future patch for CXL virtual hierarchy handling. 2 changes are required to maintain compilation after the move. Change cxl_rch_handle_error() & cxl_rch_enable_rcec() to be non-static inorder for accessing from the AER driver in aer.c. Introduce CONFIG_CXL_RCH_RAS in cxl/Kconfig. Update pcie/pcie/Makefile to conditionally compile rch_aer.c file using CONFIG_CXL_RCH_RAS. Signed-off-by: Terry Bowman Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - Remove changes in code-split and move to earlier, new patch - Add #include to cxl_ras.c - Move cxl_rch_handle_error() & cxl_rch_enable_rcec() declarations from pci= .h to aer.h, more localized. - Introduce CONFIG_CXL_RCH_RAS, includes Makefile changes, ras.c ifdef chan= ges --- drivers/cxl/Kconfig | 9 +++- drivers/cxl/core/ras.c | 3 ++ drivers/pci/pci.h | 20 +++++++ drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/aer.c | 108 +++---------------------------------- drivers/pci/pcie/rch_aer.c | 99 ++++++++++++++++++++++++++++++++++ 6 files changed, 138 insertions(+), 102 deletions(-) create mode 100644 drivers/pci/pcie/rch_aer.c diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 1c7c8989fd8b..028201e24523 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -235,5 +235,12 @@ config CXL_MCE =20 config CXL_RAS def_bool y - depends on ACPI_APEI_GHES && PCIEAER_CXL + depends on ACPI_APEI_GHES && PCIEAER && CXL_PCI + +config CXL_RCH_RAS + bool "CXL: Restricted CXL Host (RCH) protocol error handling" + def_bool n + depends on CXL_RAS + help + RAS support for Restricted CXL Host (RCH) defined in CXL1.1. endif diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index f42f9a255ef8..c9f2f0335bfd 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -126,6 +126,9 @@ void cxl_ras_exit(void) cancel_work_sync(&cxl_cper_prot_err_work); } =20 +static bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_= base); +static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *= ras_base); + #ifdef CONFIG_CXL_RCH_RAS static void cxl_dport_map_rch_aer(struct cxl_dport *dport) { diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 12215ee72afb..c8a0c0ec0073 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1159,4 +1159,24 @@ static inline int pci_msix_write_tph_tag(struct pci_= dev *pdev, unsigned int inde (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ PCI_CONF1_EXT_REG(reg)) =20 +struct aer_err_info; + +#ifdef CONFIG_CXL_RCH_RAS +void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info); +void cxl_rch_enable_rcec(struct pci_dev *rcec); +#else +static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_er= r_info *info) { } +static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { } +#endif + +#ifdef CONFIG_CXL_RAS +void pci_aer_unmask_internal_errors(struct pci_dev *dev); +bool cxl_error_is_native(struct pci_dev *dev); +bool is_internal_error(struct aer_err_info *info); +#else +static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } +static inline bool cxl_error_is_native(struct pci_dev *dev) { return false= ; } +static inline bool is_internal_error(struct aer_err_info *info) { return f= alse; } +#endif + #endif /* DRIVERS_PCI_H */ diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 173829aa02e6..07c299dbcdd7 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PCIEPORTBUS) +=3D pcieportdrv.o bwctrl.o =20 obj-y +=3D aspm.o obj-$(CONFIG_PCIEAER) +=3D aer.o err.o tlp.o +obj-$(CONFIG_CXL_RCH_RAS) +=3D rch_aer.o obj-$(CONFIG_PCIEAER_INJECT) +=3D aer_inject.o obj-$(CONFIG_PCIE_PME) +=3D pme.o obj-$(CONFIG_PCIE_DPC) +=3D dpc.o diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 7fe9f883f5c5..29de7ee861f7 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1098,7 +1098,7 @@ static bool find_source_device(struct pci_dev *parent, * Note: AER must be enabled and supported by the device which must be * checked in advance, e.g. with pcie_aer_is_native(). */ -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) +void pci_aer_unmask_internal_errors(struct pci_dev *dev) { int aer =3D dev->aer_cap; u32 mask; @@ -1111,119 +1111,25 @@ static void pci_aer_unmask_internal_errors(struct = pci_dev *dev) mask &=3D ~PCI_ERR_COR_INTERNAL; pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); } +EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL"); =20 -static bool is_cxl_mem_dev(struct pci_dev *dev) -{ - /* - * The capability, status, and control fields in Device 0, - * Function 0 DVSEC control the CXL functionality of the - * entire device (CXL 3.0, 8.1.3). - */ - if (dev->devfn !=3D PCI_DEVFN(0, 0)) - return false; - - /* - * CXL Memory Devices must have the 502h class code set (CXL - * 3.0, 8.1.12.1). - */ - if ((dev->class >> 8) !=3D PCI_CLASS_MEMORY_CXL) - return false; - - return true; -} - -static bool cxl_error_is_native(struct pci_dev *dev) +bool cxl_error_is_native(struct pci_dev *dev) { struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); =20 return (pcie_ports_native || host->native_aer); } +EXPORT_SYMBOL_NS_GPL(cxl_error_is_native, "CXL"); =20 -static bool is_internal_error(struct aer_err_info *info) +bool is_internal_error(struct aer_err_info *info) { if (info->severity =3D=3D AER_CORRECTABLE) return info->status & PCI_ERR_COR_INTERNAL; =20 return info->status & PCI_ERR_UNC_INTN; } - -static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) -{ - struct aer_err_info *info =3D (struct aer_err_info *)data; - const struct pci_error_handlers *err_handler; - - if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) - return 0; - - /* Protect dev->driver */ - device_lock(&dev->dev); - - err_handler =3D dev->driver ? dev->driver->err_handler : NULL; - if (!err_handler) - goto out; - - if (info->severity =3D=3D AER_CORRECTABLE) { - if (err_handler->cor_error_detected) - err_handler->cor_error_detected(dev); - } else if (err_handler->error_detected) { - if (info->severity =3D=3D AER_NONFATAL) - err_handler->error_detected(dev, pci_channel_io_normal); - else if (info->severity =3D=3D AER_FATAL) - err_handler->error_detected(dev, pci_channel_io_frozen); - } -out: - device_unlock(&dev->dev); - return 0; -} - -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info = *info) -{ - /* - * Internal errors of an RCEC indicate an AER error in an - * RCH's downstream port. Check and handle them in the CXL.mem - * device driver. - */ - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && - is_internal_error(info)) - pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); -} - -static int handles_cxl_error_iter(struct pci_dev *dev, void *data) -{ - bool *handles_cxl =3D data; - - if (!*handles_cxl) - *handles_cxl =3D is_cxl_mem_dev(dev) && cxl_error_is_native(dev); - - /* Non-zero terminates iteration */ - return *handles_cxl; -} - -static bool handles_cxl_errors(struct pci_dev *rcec) -{ - bool handles_cxl =3D false; - - if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); - - return handles_cxl; -} - -static void cxl_rch_enable_rcec(struct pci_dev *rcec) -{ - if (!handles_cxl_errors(rcec)) - return; - - pci_aer_unmask_internal_errors(rcec); - pci_info(rcec, "CXL: Internal errors unmasked"); -} - -#else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } -static inline void cxl_rch_handle_error(struct pci_dev *dev, - struct aer_err_info *info) { } -#endif +EXPORT_SYMBOL_NS_GPL(is_internal_error, "CXL"); +#endif /* CONFIG_CXL_RAS */ =20 /** * pci_aer_handle_error - handle logging error into an event log diff --git a/drivers/pci/pcie/rch_aer.c b/drivers/pci/pcie/rch_aer.c new file mode 100644 index 000000000000..bfe071eebf67 --- /dev/null +++ b/drivers/pci/pcie/rch_aer.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2025 AMD Corporation. All rights reserved. */ + +#include +#include +#include +#include "../pci.h" + +static bool is_cxl_mem_dev(struct pci_dev *dev) +{ + /* + * The capability, status, and control fields in Device 0, + * Function 0 DVSEC control the CXL functionality of the + * entire device (CXL 3.0, 8.1.3). + */ + if (dev->devfn !=3D PCI_DEVFN(0, 0)) + return false; + + /* + * CXL Memory Devices must have the 502h class code set (CXL + * 3.0, 8.1.12.1). + */ + if ((dev->class >> 8) !=3D PCI_CLASS_MEMORY_CXL) + return false; + + return true; +} + +static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) +{ + struct aer_err_info *info =3D (struct aer_err_info *)data; + const struct pci_error_handlers *err_handler; + + if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) + return 0; + + /* Protect dev->driver */ + device_lock(&dev->dev); + + err_handler =3D dev->driver ? dev->driver->err_handler : NULL; + if (!err_handler) + goto out; + + if (info->severity =3D=3D AER_CORRECTABLE) { + if (err_handler->cor_error_detected) + err_handler->cor_error_detected(dev); + } else if (err_handler->error_detected) { + if (info->severity =3D=3D AER_NONFATAL) + err_handler->error_detected(dev, pci_channel_io_normal); + else if (info->severity =3D=3D AER_FATAL) + err_handler->error_detected(dev, pci_channel_io_frozen); + } +out: + device_unlock(&dev->dev); + return 0; +} + +void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) +{ + /* + * Internal errors of an RCEC indicate an AER error in an + * RCH's downstream port. Check and handle them in the CXL.mem + * device driver. + */ + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && + is_internal_error(info)) + pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); +} + +static int handles_cxl_error_iter(struct pci_dev *dev, void *data) +{ + bool *handles_cxl =3D data; + + if (!*handles_cxl) + *handles_cxl =3D is_cxl_mem_dev(dev) && cxl_error_is_native(dev); + + /* Non-zero terminates iteration */ + return *handles_cxl; +} + +static bool handles_cxl_errors(struct pci_dev *rcec) +{ + bool handles_cxl =3D false; + + if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && + pcie_aer_is_native(rcec)) + pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + + return handles_cxl; +} + +void cxl_rch_enable_rcec(struct pci_dev *rcec) +{ + if (!handles_cxl_errors(rcec)) + return; + + pci_aer_unmask_internal_errors(rcec); + pci_info(rcec, "CXL: Internal errors unmasked"); +} --=20 2.51.0.rc2.21.ge5ab6b3e5a From nobody Fri Oct 3 18:01:56 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2067.outbound.protection.outlook.com [40.107.243.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B8301F9F73; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:37:12.0100 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c529a13c-b439-4fd4-b961-08dde50a3ebc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8553 Content-Type: text/plain; charset="utf-8" The CXL DVSECs are currently defined in cxl/core/cxlpci.h. These are not accessible to other subsystems. Change DVSEC name formatting to follow the existing PCI format in pci_regs.h. The current format uses CXL_DVSEC_XYZ. Change to be PCI_DVSEC_C= XL_XYZ. Update existing occurrences to match the name change. Update the inline documentation to refer to latest CXL spec version. Signed-off-by: Terry Bowman Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- drivers/cxl/core/pci.c | 62 +++++++++++++++++------------------ drivers/cxl/core/regs.c | 12 +++---- drivers/cxl/cxlpci.h | 53 ------------------------------ drivers/cxl/pci.c | 2 +- drivers/pci/pci.c | 18 +++++----- include/uapi/linux/pci_regs.h | 60 ++++++++++++++++++++++++++++++--- 6 files changed, 104 insertions(+), 103 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a3aef78f903a..d677691f8a05 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -110,19 +110,19 @@ static int cxl_dvsec_mem_range_valid(struct cxl_dev_s= tate *cxlds, int id) int rc, i; u32 temp; =20 - if (id > CXL_DVSEC_RANGE_MAX) + if (id > PCI_DVSEC_CXL_RANGE_MAX) return -EINVAL; =20 /* Check MEM INFO VALID bit first, give up after 1s */ i =3D 1; do { rc =3D pci_read_config_dword(pdev, - d + CXL_DVSEC_RANGE_SIZE_LOW(id), + d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id), &temp); if (rc) return rc; =20 - valid =3D FIELD_GET(CXL_DVSEC_MEM_INFO_VALID, temp); + valid =3D FIELD_GET(PCI_DVSEC_CXL_MEM_INFO_VALID, temp); if (valid) break; msleep(1000); @@ -146,17 +146,17 @@ static int cxl_dvsec_mem_range_active(struct cxl_dev_= state *cxlds, int id) int rc, i; u32 temp; =20 - if (id > CXL_DVSEC_RANGE_MAX) + if (id > PCI_DVSEC_CXL_RANGE_MAX) return -EINVAL; =20 /* Check MEM ACTIVE bit, up to 60s timeout by default */ for (i =3D media_ready_timeout; i; i--) { rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(id), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id), &temp); if (rc) return rc; =20 - active =3D FIELD_GET(CXL_DVSEC_MEM_ACTIVE, temp); + active =3D FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE, temp); if (active) break; msleep(1000); @@ -185,11 +185,11 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds) u16 cap; =20 rc =3D pci_read_config_word(pdev, - d + CXL_DVSEC_CAP_OFFSET, &cap); + d + PCI_DVSEC_CXL_CAP_OFFSET, &cap); if (rc) return rc; =20 - hdm_count =3D FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + hdm_count =3D FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT_MASK, cap); for (i =3D 0; i < hdm_count; i++) { rc =3D cxl_dvsec_mem_range_valid(cxlds, i); if (rc) @@ -217,16 +217,16 @@ static int cxl_set_mem_enable(struct cxl_dev_state *c= xlds, u16 val) u16 ctrl; int rc; =20 - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL_OFFSET, &ctrl); if (rc < 0) return rc; =20 - if ((ctrl & CXL_DVSEC_MEM_ENABLE) =3D=3D val) + if ((ctrl & PCI_DVSEC_CXL_MEM_ENABLE) =3D=3D val) return 1; - ctrl &=3D ~CXL_DVSEC_MEM_ENABLE; + ctrl &=3D ~PCI_DVSEC_CXL_MEM_ENABLE; ctrl |=3D val; =20 - rc =3D pci_write_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, ctrl); + rc =3D pci_write_config_word(pdev, d + PCI_DVSEC_CXL_CTRL_OFFSET, ctrl); if (rc < 0) return rc; =20 @@ -242,7 +242,7 @@ static int devm_cxl_enable_mem(struct device *host, str= uct cxl_dev_state *cxlds) { int rc; =20 - rc =3D cxl_set_mem_enable(cxlds, CXL_DVSEC_MEM_ENABLE); + rc =3D cxl_set_mem_enable(cxlds, PCI_DVSEC_CXL_MEM_ENABLE); if (rc < 0) return rc; if (rc > 0) @@ -304,11 +304,11 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, return -ENXIO; } =20 - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CAP_OFFSET, &cap); if (rc) return rc; =20 - if (!(cap & CXL_DVSEC_MEM_CAPABLE)) { + if (!(cap & PCI_DVSEC_CXL_MEM_CAPABLE)) { dev_dbg(dev, "Not MEM Capable\n"); return -ENXIO; } @@ -319,7 +319,7 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, * driver is for a spec defined class code which must be CXL.mem * capable, there is no point in continuing to enable CXL.mem. */ - hdm_count =3D FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + hdm_count =3D FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT_MASK, cap); if (!hdm_count || hdm_count > 2) return -EINVAL; =20 @@ -328,11 +328,11 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, * disabled, and they will remain moot after the HDM Decoder * capability is enabled. */ - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL_OFFSET, &ctrl); if (rc) return rc; =20 - info->mem_enabled =3D FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); + info->mem_enabled =3D FIELD_GET(PCI_DVSEC_CXL_MEM_ENABLE, ctrl); if (!info->mem_enabled) return 0; =20 @@ -345,35 +345,35 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, return rc; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i), &temp); if (rc) return rc; =20 size =3D (u64)temp << 32; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(i), &temp); if (rc) return rc; =20 - size |=3D temp & CXL_DVSEC_MEM_SIZE_LOW_MASK; + size |=3D temp & PCI_DVSEC_CXL_MEM_SIZE_LOW_MASK; if (!size) { continue; } =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_BASE_HIGH(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_BASE_HIGH(i), &temp); if (rc) return rc; =20 base =3D (u64)temp << 32; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_BASE_LOW(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_BASE_LOW(i), &temp); if (rc) return rc; =20 - base |=3D temp & CXL_DVSEC_MEM_BASE_LOW_MASK; + base |=3D temp & PCI_DVSEC_CXL_MEM_BASE_LOW_MASK; =20 info->dvsec_range[ranges++] =3D (struct range) { .start =3D base, @@ -781,7 +781,7 @@ u16 cxl_gpf_get_dvsec(struct device *dev) is_port =3D false; =20 dvsec =3D pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, - is_port ? CXL_DVSEC_PORT_GPF : CXL_DVSEC_DEVICE_GPF); + is_port ? PCI_DVSEC_CXL_PORT_GPF : PCI_DVSEC_CXL_DEVICE_GPF); if (!dvsec) dev_warn(dev, "%s GPF DVSEC not present\n", is_port ? "Port" : "Device"); @@ -797,14 +797,14 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev= , int dvsec, int phase) =20 switch (phase) { case 1: - offset =3D CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET; - base =3D CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK; - scale =3D CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK; + offset =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL_OFFSET; + base =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE_MASK; + scale =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE_MASK; break; case 2: - offset =3D CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET; - base =3D CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK; - scale =3D CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK; + offset =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL_OFFSET; + base =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE_MASK; + scale =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE_MASK; break; default: return -EINVAL; diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 5ca7b0eed568..fb70ffbba72d 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -271,10 +271,10 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_device_regs, "CXL"); static bool cxl_decode_regblock(struct pci_dev *pdev, u32 reg_lo, u32 reg_= hi, struct cxl_register_map *map) { - u8 reg_type =3D FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo); - int bar =3D FIELD_GET(CXL_DVSEC_REG_LOCATOR_BIR_MASK, reg_lo); + u8 reg_type =3D FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID_MASK, reg_lo= ); + int bar =3D FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BIR_MASK, reg_lo); u64 offset =3D ((u64)reg_hi << 32) | - (reg_lo & CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK); + (reg_lo & PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW_MASK); =20 if (offset > pci_resource_len(pdev, bar)) { dev_warn(&pdev->dev, @@ -311,15 +311,15 @@ static int __cxl_find_regblock_instance(struct pci_de= v *pdev, enum cxl_regloc_ty }; =20 regloc =3D pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, - CXL_DVSEC_REG_LOCATOR); + PCI_DVSEC_CXL_REG_LOCATOR); if (!regloc) return -ENXIO; =20 pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); regloc_size =3D FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); =20 - regloc +=3D CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET; - regblocks =3D (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8; + regloc +=3D PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1_OFFSET; + regblocks =3D (regloc_size - PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1_OFFSET) / 8; =20 for (i =3D 0; i < regblocks; i++, regloc +=3D 8) { u32 reg_lo, reg_hi; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 3959fa7e2ead..ad24d81e9eaa 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -7,59 +7,6 @@ =20 #define CXL_MEMORY_PROGIF 0x10 =20 -/* - * See section 8.1 Configuration Space Registers in the CXL 2.0 - * Specification. Names are taken straight from the specification with "CX= L" and - * "DVSEC" redundancies removed. When obvious, abbreviations may be used. - */ -#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20) - -/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ -#define CXL_DVSEC_PCIE_DEVICE 0 -#define CXL_DVSEC_CAP_OFFSET 0xA -#define CXL_DVSEC_MEM_CAPABLE BIT(2) -#define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4) -#define CXL_DVSEC_CTRL_OFFSET 0xC -#define CXL_DVSEC_MEM_ENABLE BIT(2) -#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) -#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) -#define CXL_DVSEC_MEM_INFO_VALID BIT(0) -#define CXL_DVSEC_MEM_ACTIVE BIT(1) -#define CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28) -#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) -#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) -#define CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28) - -#define CXL_DVSEC_RANGE_MAX 2 - -/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */ -#define CXL_DVSEC_FUNCTION_MAP 2 - -/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */ -#define CXL_DVSEC_PORT_EXTENSIONS 3 - -/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */ -#define CXL_DVSEC_PORT_GPF 4 -#define CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C -#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK GENMASK(3, 0) -#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK GENMASK(11, 8) -#define CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE -#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK GENMASK(3, 0) -#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK GENMASK(11, 8) - -/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */ -#define CXL_DVSEC_DEVICE_GPF 5 - -/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */ -#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7 - -/* CXL 2.0 8.1.9: Register Locator DVSEC */ -#define CXL_DVSEC_REG_LOCATOR 8 -#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC -#define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0) -#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8) -#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16) - /* * NOTE: Currently all the functions which are enabled for CXL require the= ir * vectors to be in the first 16. Use this as the default max. diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bd100ac31672..bd95be1f3d5c 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -933,7 +933,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) cxlds->rcd =3D is_cxl_restricted(pdev); cxlds->serial =3D pci_get_dsn(pdev); cxlds->cxl_dvsec =3D pci_find_dvsec_capability( - pdev, PCI_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + pdev, PCI_VENDOR_ID_CXL, PCI_DVSEC_CXL_DEVICE); if (!cxlds->cxl_dvsec) dev_warn(&pdev->dev, "Device DVSEC not present, skip CXL.mem init\n"); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 9e42090fb108..d775ed37a79b 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5031,7 +5031,7 @@ static int pci_dev_reset_slot_function(struct pci_dev= *dev, bool probe) static u16 cxl_port_dvsec(struct pci_dev *dev) { return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, - PCI_DVSEC_CXL_PORT); + PCI_DVSEC_CXL_PORT_EXT); } =20 static bool cxl_sbr_masked(struct pci_dev *dev) @@ -5043,7 +5043,9 @@ static bool cxl_sbr_masked(struct pci_dev *dev) if (!dvsec) return false; =20 - rc =3D pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®); + rc =3D pci_read_config_word(dev, + dvsec + PCI_DVSEC_CXL_PORT_EXT_CTL_OFFSET, + ®); if (rc || PCI_POSSIBLE_ERROR(reg)) return false; =20 @@ -5052,7 +5054,7 @@ static bool cxl_sbr_masked(struct pci_dev *dev) * bit in Bridge Control has no effect. When 1, the Port generates * hot reset when the SBR bit is set to 1. */ - if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR) + if (reg & PCI_DVSEC_CXL_PORT_EXT_CTL_UNMASK_SBR) return false; =20 return true; @@ -5097,22 +5099,22 @@ static int cxl_reset_bus_function(struct pci_dev *d= ev, bool probe) if (probe) return 0; =20 - rc =3D pci_read_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®); + rc =3D pci_read_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_EXT_CTL_OF= FSET, ®); if (rc) return -ENOTTY; =20 - if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR) { + if (reg & PCI_DVSEC_CXL_PORT_EXT_CTL_UNMASK_SBR) { val =3D reg; } else { - val =3D reg | PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR; - pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, + val =3D reg | PCI_DVSEC_CXL_PORT_EXT_CTL_UNMASK_SBR; + pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_EXT_CTL_OFFSET, val); } =20 rc =3D pci_reset_bus_function(dev, probe); =20 if (reg !=3D val) - pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, + pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_EXT_CTL_OFFSET, reg); =20 return rc; diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index a3a3e942dedf..b03244d55aea 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1225,9 +1225,61 @@ /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE = */ #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_= RSP_3_TYPE =20 -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ -#define PCI_DVSEC_CXL_PORT 3 -#define PCI_DVSEC_CXL_PORT_CTL 0x0c -#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 +/* Compute Express Link (CXL r3.2, sec 8.1) + * + * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state + * is "disconnected" (CXL r3.2, sec 9.12.3). Re-enumerate these + * registers on downstream link-up events. + */ + +#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20) + +/* CXL 3.2 8.1.3: PCIe DVSEC for CXL Device */ +#define PCI_DVSEC_CXL_DEVICE 0 +#define PCI_DVSEC_CXL_CAP_OFFSET 0xA +#define PCI_DVSEC_CXL_MEM_CAPABLE BIT(2) +#define PCI_DVSEC_CXL_HDM_COUNT_MASK GENMASK(5, 4) +#define PCI_DVSEC_CXL_CTRL_OFFSET 0xC +#define PCI_DVSEC_CXL_MEM_ENABLE BIT(2) +#define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) +#define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) +#define PCI_DVSEC_CXL_MEM_INFO_VALID BIT(0) +#define PCI_DVSEC_CXL_MEM_ACTIVE BIT(1) +#define PCI_DVSEC_CXL_MEM_SIZE_LOW_MASK GENMASK(31, 28) +#define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) +#define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) +#define PCI_DVSEC_CXL_MEM_BASE_LOW_MASK GENMASK(31, 28) + +#define PCI_DVSEC_CXL_RANGE_MAX 2 + +/* CXL 3.2 8.1.4: Non-CXL Function Map DVSEC */ +#define PCI_DVSEC_CXL_FUNCTION_MAP 2 + +/* CXL 3.2 8.1.5: Extensions DVSEC for Ports */ +#define PCI_DVSEC_CXL_PORT_EXT 3 +#define PCI_DVSEC_CXL_PORT_EXT_CTL_OFFSET 0x0c +#define PCI_DVSEC_CXL_PORT_EXT_CTL_UNMASK_SBR 0x00000001 + +/* CXL 3.2 8.1.6: GPF DVSEC for CXL Port */ +#define PCI_DVSEC_CXL_PORT_GPF 4 +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE_MASK GENMASK(3, 0) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE_MASK GENMASK(11, 8) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE_MASK GENMASK(3, 0) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE_MASK GENMASK(11, 8) + +/* CXL 3.2 8.1.7: GPF DVSEC for CXL Device */ +#define PCI_DVSEC_CXL_DEVICE_GPF 5 + +/* CXL 3.2 8.1.8: PCIe DVSEC for Flex Bus Port */ +#define PCI_DVSEC_CXL_FLEXBUS_PORT 7 + +/* CXL 3.2 8.1.9: Register Locator DVSEC */ +#define PCI_DVSEC_CXL_REG_LOCATOR 8 +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1_OFFSET 0xC +#define PCI_DVSEC_CXL_REG_LOCATOR_BIR_MASK GENMASK(2, 0) +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8) +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16) =20 #endif /* LINUX_PCI_REGS_H */ --=20 2.51.0.rc2.21.ge5ab6b3e5a From nobody Fri Oct 3 18:01:56 2025 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2065.outbound.protection.outlook.com [40.107.95.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 665542080C8; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:37:14.4930 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c1672f36-a613-437b-946d-08dde50a4037 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8049 Content-Type: text/plain; charset="utf-8" CXL and AER drivers need the ability to identify CXL devices. Introduce set_pcie_cxl() with logic checking for CXL.mem or CXL.cache status in the CXL Flexbus DVSEC status register. The CXL Flexbus DVSEC presence is used because it is required for all the CXL PCIe devices.[1] Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL CXL.cache and CXl.mem status. In the case the device is an EP or USP, call set_pcie_cxl() on behalf of the parent downstream device. This will make certain the correct state is cached. Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'. [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment, Table 8-2 Signed-off-by: Terry Bowman Reviewed-by: Ira Weiny Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Alejandro Lucero Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - Amended set_pcie_cxl() to check for Upstream Port's and EP's parent downstream port by calling set_pcie_cxl(). (Dan) - Retitle patch: 'Add' -> 'Introduce' - Add check for CXL.mem and CXL.cache (Alejandro, Dan) --- drivers/pci/probe.c | 25 +++++++++++++++++++++++++ include/linux/pci.h | 6 ++++++ include/uapi/linux/pci_regs.h | 3 +++ 3 files changed, 34 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4b8693ec9e4c..b08cd0346136 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1691,6 +1691,29 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) dev->is_thunderbolt =3D 1; } =20 +static void set_pcie_cxl(struct pci_dev *dev) +{ + struct pci_dev *parent; + u16 dvsec =3D pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_FLEXBUS_PORT); + if (dvsec) { + u16 cap; + + pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_FLEXBUS_STATUS_OFFSET, &= cap); + + dev->is_cxl =3D FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_STATUS_CACHE_MASK, cap) = || + FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_STATUS_MEM_MASK, cap); + } + + if (!pci_is_pcie(dev) || + !(pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ENDPOINT || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_UPSTREAM)) + return; + + parent =3D pci_upstream_bridge(dev); + set_pcie_cxl(parent); +} + static void set_pcie_untrusted(struct pci_dev *dev) { struct pci_dev *parent =3D pci_upstream_bridge(dev); @@ -2021,6 +2044,8 @@ int pci_setup_device(struct pci_dev *dev) /* Need to have dev->cfg_size ready */ set_pcie_thunderbolt(dev); =20 + set_pcie_cxl(dev); + set_pcie_untrusted(dev); =20 if (pci_is_pcie(dev)) diff --git a/include/linux/pci.h b/include/linux/pci.h index 05e68f35f392..79878243b681 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -453,6 +453,7 @@ struct pci_dev { unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ + unsigned int is_cxl:1; /* Compute Express Link (CXL) */ /* * Devices marked being untrusted are the ones that can potentially * execute DMA attacks and similar. They are typically connected @@ -744,6 +745,11 @@ static inline bool pci_is_vga(struct pci_dev *pdev) return false; } =20 +static inline bool pcie_is_cxl(struct pci_dev *pci_dev) +{ + return pci_dev->is_cxl; +} + #define for_each_pci_bridge(dev, bus) \ list_for_each_entry(dev, &bus->devices, bus_list) \ if (!pci_is_bridge(dev)) {} else diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index b03244d55aea..252c06402b13 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1274,6 +1274,9 @@ =20 /* CXL 3.2 8.1.8: PCIe DVSEC for Flex Bus Port */ #define PCI_DVSEC_CXL_FLEXBUS_PORT 7 +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_OFFSET 0xE +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_CACHE_MASK BIT(0) +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_MEM_MASK BIT(2) =20 /* CXL 3.2 8.1.9: Register Locator DVSEC */ #define PCI_DVSEC_CXL_REG_LOCATOR 8 --=20 2.51.0.rc2.21.ge5ab6b3e5a From nobody Fri Oct 3 18:01:56 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2073.outbound.protection.outlook.com [40.107.237.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A92B20B80A; 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Tue, 26 Aug 2025 20:37:24 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v11 09/23] PCI/AER: Report CXL or PCIe bus error type in trace logging Date: Tue, 26 Aug 2025 20:35:24 -0500 Message-ID: <20250827013539.903682-10-terry.bowman@amd.com> X-Mailer: git-send-email 2.51.0.rc2.21.ge5ab6b3e5a In-Reply-To: <20250827013539.903682-1-terry.bowman@amd.com> References: <20250827013539.903682-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|SJ0PR12MB8167:EE_ X-MS-Office365-Filtering-Correlation-Id: 568d924e-68ec-4d58-b27c-08dde50a47b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|36860700013|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:37:27.0775 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 568d924e-68ec-4d58-b27c-08dde50a47b7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8167 Content-Type: text/plain; charset="utf-8" The AER service driver and aer_event tracing currently log 'PCIe Bus Type' for all errors. Update the driver and aer_event tracing to log 'CXL Bus Type' for CXL device errors. This requires the AER can identify and distinguish between PCIe errors and CXL errors. Introduce boolean 'is_cxl' to 'struct aer_err_info'. Add assignment in aer_get_device_error_info() and pci_print_aer(). Update the aer_event trace routine to accept a bus type string parameter. Signed-off-by: Terry Bowman Reviewed-by: Ira Weiny Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Jonathan Cameron Reviewed-by: Dan Williams Reviewed-by: Dave Jiang Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - Remove duplicate call to trace_aer_event() (Shiju) - Added Dan William's and Dave Jiang's reviewed-by --- drivers/pci/pci.h | 6 ++++++ drivers/pci/pcie/aer.c | 18 ++++++++++++------ include/ras/ras_event.h | 9 ++++++--- 3 files changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index c8a0c0ec0073..417a088d815f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -608,6 +608,7 @@ struct aer_err_info { int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; int error_dev_num; const char *level; /* printk level */ + bool is_cxl; =20 unsigned int id:16; =20 @@ -628,6 +629,11 @@ struct aer_err_info { int aer_get_device_error_info(struct aer_err_info *info, int i); void aer_print_error(struct aer_err_info *info, int i); =20 +static inline const char *aer_err_bus(struct aer_err_info *info) +{ + return info->is_cxl ? "CXL" : "PCIe"; +} + int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, unsigned int tlp_len, bool flit, struct pcie_tlp_log *log); diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 29de7ee861f7..1b5f5b0cdc4f 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -837,6 +837,7 @@ void aer_print_error(struct aer_err_info *info, int i) struct pci_dev *dev; int layer, agent, id; const char *level =3D info->level; + const char *bus_type =3D aer_err_bus(info); =20 if (WARN_ON_ONCE(i >=3D AER_MAX_MULTI_ERR_DEVICES)) return; @@ -845,23 +846,23 @@ void aer_print_error(struct aer_err_info *info, int i) id =3D pci_dev_id(dev); =20 pci_dev_aer_stats_incr(dev, info); - trace_aer_event(pci_name(dev), (info->status & ~info->mask), + trace_aer_event(pci_name(dev), bus_type, (info->status & ~info->mask), info->severity, info->tlp_header_valid, &info->tlp); =20 if (!info->ratelimit_print[i]) return; =20 if (!info->status) { - pci_err(dev, "PCIe Bus Error: severity=3D%s, type=3DInaccessible, (Unreg= istered Agent ID)\n", - aer_error_severity_string[info->severity]); + pci_err(dev, "%s Bus Error: severity=3D%s, type=3DInaccessible, (Unregis= tered Agent ID)\n", + bus_type, aer_error_severity_string[info->severity]); goto out; } =20 layer =3D AER_GET_LAYER_ERROR(info->severity, info->status); agent =3D AER_GET_AGENT(info->severity, info->status); =20 - aer_printk(level, dev, "PCIe Bus Error: severity=3D%s, type=3D%s, (%s)\n", - aer_error_severity_string[info->severity], + aer_printk(level, dev, "%s Bus Error: severity=3D%s, type=3D%s, (%s)\n", + bus_type, aer_error_severity_string[info->severity], aer_error_layer[layer], aer_agent_string[agent]); =20 aer_printk(level, dev, " device [%04x:%04x] error status/mask=3D%08x/%08= x\n", @@ -895,6 +896,7 @@ EXPORT_SYMBOL_GPL(cper_severity_to_aer); void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer) { + const char *bus_type; int layer, agent, tlp_header_valid =3D 0; u32 status, mask; struct aer_err_info info =3D { @@ -915,9 +917,12 @@ void pci_print_aer(struct pci_dev *dev, int aer_severi= ty, =20 info.status =3D status; info.mask =3D mask; + info.is_cxl =3D pcie_is_cxl(dev); + + bus_type =3D aer_err_bus(&info); =20 pci_dev_aer_stats_incr(dev, &info); - trace_aer_event(pci_name(dev), (status & ~mask), + trace_aer_event(pci_name(dev), bus_type, (status & ~mask), aer_severity, tlp_header_valid, &aer->header_log); =20 if (!aer_ratelimit(dev, info.severity)) @@ -1277,6 +1282,7 @@ int aer_get_device_error_info(struct aer_err_info *in= fo, int i) /* Must reset in this function */ info->status =3D 0; info->tlp_header_valid =3D 0; + info->is_cxl =3D pcie_is_cxl(dev); =20 /* The device might not support AER */ if (!aer) diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index 14c9f943d53f..080829d59c36 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -297,15 +297,17 @@ TRACE_EVENT(non_standard_event, =20 TRACE_EVENT(aer_event, TP_PROTO(const char *dev_name, + const char *bus_type, const u32 status, const u8 severity, const u8 tlp_header_valid, struct pcie_tlp_log *tlp), =20 - TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp), + TP_ARGS(dev_name, bus_type, status, severity, tlp_header_valid, tlp), =20 TP_STRUCT__entry( __string( dev_name, dev_name ) + __string( bus_type, bus_type ) __field( u32, status ) __field( u8, severity ) __field( u8, tlp_header_valid) @@ -314,6 +316,7 @@ TRACE_EVENT(aer_event, =20 TP_fast_assign( __assign_str(dev_name); + __assign_str(bus_type); __entry->status =3D status; __entry->severity =3D severity; __entry->tlp_header_valid =3D tlp_header_valid; @@ -325,8 +328,8 @@ TRACE_EVENT(aer_event, } ), =20 - TP_printk("%s PCIe Bus Error: severity=3D%s, %s, TLP Header=3D%s\n", - __get_str(dev_name), + TP_printk("%s %s Bus Error: severity=3D%s, %s, TLP Header=3D%s\n", + __get_str(dev_name), __get_str(bus_type), __entry->severity =3D=3D AER_CORRECTABLE ? "Corrected" : __entry->severity =3D=3D AER_FATAL ? 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:37:37.1066 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 628f6649-a5df-4516-1934-08dde50a4db2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4040 Content-Type: text/plain; charset="utf-8" Update the AER driver's is_cxl_mem_dev() to use FIELD_GET() while checking for a CXL Endpoint class code. Introduce a genmask bitmask for checking PCI class codes and locate in include/uapi/linux/pci_regs.h. Update the function documentation to reference the latest CXL specification. Signed-off-by: Terry Bowman Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - Add #include to cxl_ras.c - Removed line wrapping at "(CXL 3.2, 8.1.12.1)". --- drivers/pci/pcie/aer.c | 1 + drivers/pci/pcie/rch_aer.c | 6 +++--- include/uapi/linux/pci_regs.h | 2 ++ 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 1b5f5b0cdc4f..ed1de9256898 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/pci/pcie/rch_aer.c b/drivers/pci/pcie/rch_aer.c index bfe071eebf67..c3e2d4cbe8cc 100644 --- a/drivers/pci/pcie/rch_aer.c +++ b/drivers/pci/pcie/rch_aer.c @@ -17,10 +17,10 @@ static bool is_cxl_mem_dev(struct pci_dev *dev) return false; =20 /* - * CXL Memory Devices must have the 502h class code set (CXL - * 3.0, 8.1.12.1). + * CXL Memory Devices must have the 502h class code set + * (CXL 3.2, 8.1.12.1). */ - if ((dev->class >> 8) !=3D PCI_CLASS_MEMORY_CXL) + if (FIELD_GET(PCI_CLASS_CODE_MASK, dev->class) !=3D PCI_CLASS_MEMORY_CXL) return false; =20 return true; diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 252c06402b13..c7b635f6cf36 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -73,6 +73,8 @@ #define PCI_CLASS_PROG 0x09 /* Reg. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:37:47.9892 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9424bea5-4643-4f47-6334-08dde50a542e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4461 Content-Type: text/plain; charset="utf-8" CXL PCIe Port Protocol Error handling support will be added to the CXL drivers in the future. In preparation, rename the existing interfaces to support handling all CXL PCIe Port Protocol Errors. The driver's RAS support functions currently rely on a 'struct cxl_dev_state' type parameter, which is not available for CXL Port devices. However, since the same CXL RAS capability structure is needed across most CXL components and devices, a common handling approach should be adopted. To accommodate this, update the __cxl_handle_cor_ras() and __cxl_handle_ras() functions to use a `struct device` instead of `struct cxl_dev_state`. No functional changes are introduced. [1] CXL 3.1 Spec, 8.2.4 CXL.cache and CXL.mem Registers Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - None --- drivers/cxl/core/ras.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index c9f2f0335bfd..f65557e7bfa6 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -126,8 +126,8 @@ void cxl_ras_exit(void) cancel_work_sync(&cxl_cper_prot_err_work); } =20 -static bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_= base); -static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *= ras_base); +static bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); +static void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); =20 #ifdef CONFIG_CXL_RCH_RAS static void cxl_dport_map_rch_aer(struct cxl_dport *dport) @@ -237,9 +237,9 @@ static void cxl_handle_rdport_errors(struct cxl_dev_sta= te *cxlds) =20 pci_print_aer(pdev, severity, &aer_regs); if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(cxlds, dport->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras); else - cxl_handle_ras(cxlds, dport->regs.ras); + cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras); } #else static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } @@ -281,7 +281,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt, struct device *host) } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 -static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *= ras_base) +static void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { void __iomem *addr; u32 status; @@ -293,7 +293,7 @@ static void cxl_handle_cor_ras(struct cxl_dev_state *cx= lds, void __iomem *ras_ba status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); } } =20 @@ -318,7 +318,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_= base) +static bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -345,7 +345,7 @@ static bool cxl_handle_ras(struct cxl_dev_state *cxlds,= void __iomem *ras_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -367,7 +367,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_cor_ras(cxlds, cxlds->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -396,7 +396,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:37:59.2759 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9b390d8d-cbee-404f-8e34-08dde50a5ae8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7379 Content-Type: text/plain; charset="utf-8" The CXL RAS handlers do not currently log if the RAS registers are unmapped. This is needed in order to help debug CXL error handling. Update the CXL driver to log a warning message if the RAS register block is unmapped during RAS error handling. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes v10->v11: - Added Dave Jiang review-by --- drivers/cxl/core/ras.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index f65557e7bfa6..3454cf1a118d 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -286,8 +286,10 @@ static void cxl_handle_cor_ras(struct device *dev, voi= d __iomem *ras_base) void __iomem *addr; u32 status; =20 - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return; + } =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); @@ -325,8 +327,10 @@ static bool cxl_handle_ras(struct device *dev, void __= iomem *ras_base) u32 status; u32 fe; =20 - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:38:13.9124 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa8631f0-2ecc-4092-15e9-08dde50a63a2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7524 Content-Type: text/plain; charset="utf-8" CXL currently has separate trace routines for CXL Port errors and CXL Endpoint errors. This is inconvenient for the user because they must enable 2 sets of trace routines. Make updates to the trace logging such that a single trace routine logs both CXL Endpoint and CXL Port protocol errors. Keep the trace log fields 'memdev' and 'host'. While these are not accurate for non-Endpoints the fields will remain as-is to prevent breaking userspace RAS trace consumers. Add serial number parameter to the trace logging. This is used for EPs and 0 is provided for CXL port devices without a serial number. Leave the correctable and uncorrectable trace routines' TP_STRUCT__entry() unchanged with respect to member data types and order. Below is output of correctable and uncorrectable protocol error logging. CXL Root Port and CXL Endpoint examples are included below. Root Port: cxl_aer_correctable_error: memdev=3D0000:0c:00.0 host=3Dpci0000:0c serial: = 0 status=3D'CRC Threshold Hit' cxl_aer_uncorrectable_error: memdev=3D0000:0c:00.0 host=3Dpci0000:0c serial= : 0 status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enabl= e Parity Error' Endpoint: cxl_aer_correctable_error: memdev=3Dmem3 host=3D0000:0f:00.0 serial=3D0 sta= tus=3D'CRC Threshold Hit' cxl_aer_uncorrectable_error: memdev=3Dmem3 host=3D0000:0f:00.0 serial: 0 st= atus: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Pari= ty Error' Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Shiju Jose , Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - Updated CE and UCE trace routines to maintain consistent TP_Struct ABI and unchanged TP_printk() logging. --- drivers/cxl/core/ras.c | 35 +++++++++++---------- drivers/cxl/core/trace.h | 68 +++++++--------------------------------- 2 files changed, 30 insertions(+), 73 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 3454cf1a118d..fda3b0a64dab 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -13,7 +13,7 @@ static void cxl_cper_trace_corr_port_prot_err(struct pci_= dev *pdev, { u32 status =3D ras_cap.cor_status & ~ras_cap.cor_mask; =20 - trace_cxl_port_aer_correctable_error(&pdev->dev, status); + trace_cxl_aer_correctable_error(&pdev->dev, status, 0); } =20 static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev, @@ -28,8 +28,8 @@ static void cxl_cper_trace_uncorr_port_prot_err(struct pc= i_dev *pdev, else fe =3D status; =20 - trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe, - ras_cap.header_log); + trace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe, + ras_cap.header_log, 0); } =20 static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd, @@ -37,7 +37,8 @@ static void cxl_cper_trace_corr_prot_err(struct cxl_memde= v *cxlmd, { u32 status =3D ras_cap.cor_status & ~ras_cap.cor_mask; =20 - trace_cxl_aer_correctable_error(cxlmd, status); + trace_cxl_aer_correctable_error(&cxlmd->dev, cxlmd->cxlds->serial, + status); } =20 static void @@ -45,6 +46,7 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, struct cxl_ras_capability_regs ras_cap) { u32 status =3D ras_cap.uncor_status & ~ras_cap.uncor_mask; + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; u32 fe; =20 if (hweight32(status) > 1) @@ -53,8 +55,9 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, else fe =3D status; =20 - trace_cxl_aer_uncorrectable_error(cxlmd, status, fe, - ras_cap.header_log); + trace_cxl_aer_uncorrectable_error(&cxlmd->dev, status, fe, + ras_cap.header_log, + cxlds->serial); } =20 static int match_memdev_by_parent(struct device *dev, const void *uport) @@ -126,8 +129,8 @@ void cxl_ras_exit(void) cancel_work_sync(&cxl_cper_prot_err_work); } =20 -static bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); -static void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); +static bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *r= as_base); +static void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iome= m *ras_base); =20 #ifdef CONFIG_CXL_RCH_RAS static void cxl_dport_map_rch_aer(struct cxl_dport *dport) @@ -237,9 +240,9 @@ static void cxl_handle_rdport_errors(struct cxl_dev_sta= te *cxlds) =20 pci_print_aer(pdev, severity, &aer_regs); if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, dport->regs.ras); else - cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, dport->regs.ras); } #else static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } @@ -281,7 +284,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt, struct device *host) } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 -static void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) +static void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iome= m *ras_base) { void __iomem *addr; u32 status; @@ -295,7 +298,7 @@ static void cxl_handle_cor_ras(struct device *dev, void= __iomem *ras_base) status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); + trace_cxl_aer_correctable_error(dev, status, serial); } } =20 @@ -320,7 +323,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) +static bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *r= as_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -349,7 +352,7 @@ static bool cxl_handle_ras(struct device *dev, void __i= omem *ras_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -371,7 +374,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -400,7 +403,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); + ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras= ); } =20 =20 diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index a53ec4798b12..60b49beb5e3f 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -48,40 +48,13 @@ { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ ) =20 -TRACE_EVENT(cxl_port_aer_uncorrectable_error, - TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), - TP_ARGS(dev, status, fe, hl), - TP_STRUCT__entry( - __string(device, dev_name(dev)) - __string(host, dev_name(dev->parent)) - __field(u32, status) - __field(u32, first_error) - __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) - ), - TP_fast_assign( - __assign_str(device); - __assign_str(host); - __entry->status =3D status; - __entry->first_error =3D fe; - /* - * Embed the 512B headerlog data for user app retrieval and - * parsing, but no need to print this in the trace buffer. - */ - memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); - ), - TP_printk("device=3D%s host=3D%s status: '%s' first_error: '%s'", - __get_str(device), __get_str(host), - show_uc_errs(__entry->status), - show_uc_errs(__entry->first_error) - ) -); - TRACE_EVENT(cxl_aer_uncorrectable_error, - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), - TP_ARGS(cxlmd, status, fe, hl), + TP_PROTO(const struct device *cxlmd, u32 status, u32 fe, u32 *hl, + u64 serial), + TP_ARGS(cxlmd, status, fe, hl, serial), TP_STRUCT__entry( - __string(memdev, dev_name(&cxlmd->dev)) - __string(host, dev_name(cxlmd->dev.parent)) + __string(memdev, dev_name(cxlmd)) + __string(host, dev_name(cxlmd->parent)) __field(u64, serial) __field(u32, status) __field(u32, first_error) @@ -90,7 +63,7 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, TP_fast_assign( __assign_str(memdev); __assign_str(host); - __entry->serial =3D cxlmd->cxlds->serial; + __entry->serial =3D serial; __entry->status =3D status; __entry->first_error =3D fe; /* @@ -124,38 +97,19 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ ) =20 -TRACE_EVENT(cxl_port_aer_correctable_error, - TP_PROTO(struct device *dev, u32 status), - TP_ARGS(dev, status), - TP_STRUCT__entry( - __string(device, dev_name(dev)) - __string(host, dev_name(dev->parent)) - __field(u32, status) - ), - TP_fast_assign( - __assign_str(device); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:38:21.6048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df1455ad-6662-4a79-8a54-08dde50a6838 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9616 Content-Type: text/plain; charset="utf-8" Update cxl_handle_cor_ras() to exit early in the case there is no RAS errors detected after applying the status mask. This change will make the correctable handler's implementation consistent with the uncorrectable handler, cxl_handle_ras(). Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes v10->v11: - Added Dave Jiang and Jonathan Cameron's review-by - Changes moved to core/ras.c --- drivers/cxl/core/ras.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index fda3b0a64dab..69559043b772 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -296,10 +296,11 @@ static void cxl_handle_cor_ras(struct device *dev, u6= 4 serial, void __iomem *ras =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(dev, status, serial); - } + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) + return; + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:38:32.8743 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9ebfa68-24c4-4e38-4534-08dde50a6eef X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFD911547FB Content-Type: text/plain; charset="utf-8" CXL Endpoint (EP) Ports may include Root Ports (RP) or Downstream Switch Ports (DSP). CXL RPs and DSPs contain RAS registers that require memory mapping to enable RAS logging. This initialization is currently missing and must be added for CXL RPs and DSPs. Update cxl_dport_init_ras_reporting() to support RP and DSP RAS mapping. Add alongside the existing Restricted CXL Host Downstream Port RAS mapping. Update cxl_endpoint_port_probe() to invoke cxl_dport_init_ras_reporting(). This will initiate the RAS mapping for CXL RPs and DSPs when each CXL EP is created and added to the EP port. Signed-off-by: Terry Bowman Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - Use local pointer for readability in cxl_switch_port_init_ras() (Jonathan= Cameron) - Rename port to be ep in cxl_endpoint_port_init_ras() (Dave Jiang) - Rename dport to be parent_dport in cxl_endpoint_port_init_ras() and cxl_switch_port_init_ras() (Dave Jiang) - Port helper changes were in cxl/port.c, now in core/ras.c (Dave Jiang) --- drivers/cxl/core/core.h | 7 ++++++ drivers/cxl/core/ras.c | 47 +++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 2 ++ drivers/cxl/cxlpci.h | 4 ---- drivers/cxl/mem.c | 4 +++- drivers/cxl/port.c | 5 +++++ 6 files changed, 64 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 2c81a43d7b05..2fa76a913264 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -146,6 +146,9 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port= *port, #ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); +void cxl_switch_port_init_ras(struct cxl_port *port); +void cxl_endpoint_port_init_ras(struct cxl_port *ep); +void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); #else static inline int cxl_ras_init(void) { @@ -155,6 +158,10 @@ static inline int cxl_ras_init(void) static inline void cxl_ras_exit(void) { } +static inline void cxl_switch_port_init_ras(struct cxl_port *port) { } +static inline void cxl_endpoint_port_init_ras(struct cxl_port *ep) { } +static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, + struct device *host) { } #endif // CONFIG_CXL_RAS =20 int cxl_gpf_port_setup(struct cxl_dport *dport); diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 69559043b772..42b6e0b092d5 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -284,6 +284,53 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dp= ort, struct device *host) } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 +static void cxl_uport_init_ras_reporting(struct cxl_port *port, + struct device *host) +{ + struct cxl_register_map *map =3D &port->reg_map; + + map->host =3D host; + if (cxl_map_component_regs(map, &port->uport_regs, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(&port->dev, "Failed to map RAS capability\n"); +} + +void cxl_switch_port_init_ras(struct cxl_port *port) +{ + struct cxl_dport *parent_dport =3D port->parent_dport; + + if (is_cxl_root(to_cxl_port(port->dev.parent))) + return; + + /* May have parent DSP or RP */ + if (parent_dport && dev_is_pci(parent_dport->dport_dev)) { + struct pci_dev *pdev =3D to_pci_dev(parent_dport->dport_dev); + + if ((pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) || + (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM)) + cxl_dport_init_ras_reporting(parent_dport, &port->dev); + } + + cxl_uport_init_ras_reporting(port, &port->dev); +} +EXPORT_SYMBOL_NS_GPL(cxl_switch_port_init_ras, "CXL"); + +void cxl_endpoint_port_init_ras(struct cxl_port *ep) +{ + struct cxl_dport *parent_dport; + struct cxl_memdev *cxlmd =3D to_cxl_memdev(ep->uport_dev); + struct cxl_port *parent_port __free(put_cxl_port) =3D + cxl_mem_find_port(cxlmd, &parent_dport); + + if (!parent_dport || !dev_is_pci(parent_dport->dport_dev)) { + dev_err(&ep->dev, "CXL port topology not found\n"); + return; + } + + cxl_dport_init_ras_reporting(parent_dport, cxlmd->cxlds->dev); +} +EXPORT_SYMBOL_NS_GPL(cxl_endpoint_port_init_ras, "CXL"); + static void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iome= m *ras_base) { void __iomem *addr; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 8f6224ac6785..32fccad9a7f6 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -586,6 +586,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @uport_regs: mapped component registers * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation orde= ring * @commit_end: cursor to track highest committed decoder for commit order= ing @@ -606,6 +607,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + struct cxl_component_regs uport_regs; int nr_dports; int hdm_end; int commit_end; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index ad24d81e9eaa..a6da0abfa506 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -84,7 +84,6 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); #else static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } =20 @@ -93,9 +92,6 @@ static inline pci_ers_result_t cxl_error_detected(struct = pci_dev *pdev, { return PCI_ERS_RESULT_NONE; } - -static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, - struct device *host) { } #endif =20 #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 6e6777b7bafb..f7dc0ba8905d 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -7,6 +7,7 @@ =20 #include "cxlmem.h" #include "cxlpci.h" +#include "core/core.h" =20 /** * DOC: cxl mem @@ -166,7 +167,8 @@ static int cxl_mem_probe(struct device *dev) else endpoint_parent =3D &parent_port->dev; =20 - cxl_dport_init_ras_reporting(dport, dev); + if (dport->rch) + cxl_dport_init_ras_reporting(dport, dev); =20 scoped_guard(device, endpoint_parent) { if (!endpoint_parent->driver) { diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index fe4b593331da..e66c7f2e1955 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -6,6 +6,7 @@ =20 #include "cxlmem.h" #include "cxlpci.h" +#include "core/core.h" =20 /** * DOC: cxl port @@ -71,6 +72,8 @@ static int cxl_switch_port_probe(struct cxl_port *port) =20 cxl_switch_parse_cdat(port); =20 + cxl_switch_port_init_ras(port); + cxlhdm =3D devm_cxl_setup_hdm(port, NULL); if (!IS_ERR(cxlhdm)) return devm_cxl_enumerate_decoders(cxlhdm, NULL); @@ -125,6 +128,8 @@ static int cxl_endpoint_port_probe(struct cxl_port *por= t) if (rc) return rc; =20 + cxl_endpoint_port_init_ras(port); + /* * Now that all endpoint decoders are successfully enumerated, try to * assemble regions from committed decoders --=20 2.51.0.rc2.21.ge5ab6b3e5a From nobody Fri Oct 3 18:01:56 2025 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2045.outbound.protection.outlook.com [40.107.101.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1A5F35966; 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Tue, 26 Aug 2025 20:38:42 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v11 16/23] cxl/pci: Introduce CXL Endpoint protocol error handlers Date: Tue, 26 Aug 2025 20:35:31 -0500 Message-ID: <20250827013539.903682-17-terry.bowman@amd.com> X-Mailer: git-send-email 2.51.0.rc2.21.ge5ab6b3e5a In-Reply-To: <20250827013539.903682-1-terry.bowman@amd.com> References: <20250827013539.903682-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|SJ2PR12MB9085:EE_ X-MS-Office365-Filtering-Correlation-Id: a03c4ef5-c4e5-41dd-9b14-08dde50a758c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:38:43.9718 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a03c4ef5-c4e5-41dd-9b14-08dde50a758c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9085 Content-Type: text/plain; charset="utf-8" CXL Endpoint protocol errors are currently handled using PCI error handlers. The CXL Endpoint requires CXL specific handling in the case of uncorrectable error (UCE) handling not provided by the PCI handlers. Add CXL specific handlers for CXL Endpoints. Rename the existing cxl_error_handlers to be pci_error_handlers to more correctly indicate the error type and follow naming consistency. The PCI handlers will be called if the CXL device is not trained for alternate protocol (CXL). Update the CXL Endpoint PCI handlers to call the CXL UCE handlers. The existing EP UCE handler includes checks for various results. These are no longer needed because CXL UCE recovery will not be attempted. Implement cxl_handle_ras() to return PCI_ERS_RESULT_NONE or PCI_ERS_RESULT_PANIC. The CXL UCE handler is called by cxl_do_recovery() that acts on the return value. In the case of the PCI handler path, call panic() if the result is PCI_ERS_RESULT_PANIC. Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonath= an) - cxl_error_detected() - Remove extra line (Shiju) - Changes moved to core/ras.c (Terry) - cxl_error_detected(), remove 'ue' and return with function call. (Jonatha= n) - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition - Move #include "pci.h from cxl.h to core.h (Terry) - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry) --- drivers/cxl/core/core.h | 17 +++++++ drivers/cxl/core/ras.c | 110 +++++++++++++++++++--------------------- drivers/cxl/cxlpci.h | 15 ------ drivers/cxl/pci.c | 9 ++-- include/linux/pci.h | 3 ++ 5 files changed, 78 insertions(+), 76 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 2fa76a913264..6e3e7f2e0e2d 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -6,6 +6,7 @@ =20 #include #include +#include =20 extern const struct device_type cxl_nvdimm_bridge_type; extern const struct device_type cxl_nvdimm_type; @@ -149,6 +150,11 @@ void cxl_ras_exit(void); void cxl_switch_port_init_ras(struct cxl_port *port); void cxl_endpoint_port_init_ras(struct cxl_port *ep); void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); +pci_ers_result_t pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error); +void pci_cor_error_detected(struct pci_dev *pdev); +void cxl_cor_error_detected(struct device *dev); +pci_ers_result_t cxl_error_detected(struct device *dev); #else static inline int cxl_ras_init(void) { @@ -162,6 +168,17 @@ static inline void cxl_switch_port_init_ras(struct cxl= _port *port) { } static inline void cxl_endpoint_port_init_ras(struct cxl_port *ep) { } static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host) { } +static inline pci_ers_result_t pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error) +{ + return PCI_ERS_RESULT_NONE; +} +static inline void pci_cor_error_detected(struct pci_dev *pdev) { } +static inline void cxl_cor_error_detected(struct device *dev) { } +static inline pci_ers_result_t cxl_error_detected(struct device *dev) +{ + return PCI_ERS_RESULT_NONE; +} #endif // CONFIG_CXL_RAS =20 int cxl_gpf_port_setup(struct cxl_dport *dport); diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 42b6e0b092d5..b285448c2d9c 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -129,7 +129,7 @@ void cxl_ras_exit(void) cancel_work_sync(&cxl_cper_prot_err_work); } =20 -static bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *r= as_base); +static pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, voi= d __iomem *ras_base); static void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iome= m *ras_base); =20 #ifdef CONFIG_CXL_RCH_RAS @@ -371,7 +371,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *r= as_base) +static pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, voi= d __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -380,13 +380,13 @@ static bool cxl_handle_ras(struct device *dev, u64 se= rial, void __iomem *ras_bas =20 if (!ras_base) { dev_warn_once(dev, "CXL RAS register block is not mapped"); - return false; + return PCI_ERS_RESULT_NONE; } =20 addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status =3D readl(addr); if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) - return false; + return PCI_ERS_RESULT_NONE; =20 /* If multiple errors, log header points to first error from ctrl reg */ if (hweight32(status) > 1) { @@ -403,76 +403,72 @@ static bool cxl_handle_ras(struct device *dev, u64 se= rial, void __iomem *ras_bas trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 - return true; + return PCI_ERS_RESULT_PANIC; } =20 -void cxl_cor_error_detected(struct pci_dev *pdev) +void cxl_cor_error_detected(struct device *dev) { + struct pci_dev *pdev =3D to_pci_dev(dev); struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct device *dev =3D &cxlds->cxlmd->dev; + struct device *cxlmd_dev =3D &cxlds->cxlmd->dev; =20 - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return; - } + guard(device)(cxlmd_dev); =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras); + if (!cxlmd_dev->driver) { + dev_warn(&pdev->dev, "%s: memdev disabled, abort error handling", dev_na= me(dev)); + return; } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras); } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); =20 -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +void pci_cor_error_detected(struct pci_dev *pdev) { + cxl_cor_error_detected(&pdev->dev); +} +EXPORT_SYMBOL_NS_GPL(pci_cor_error_detected, "CXL"); + +pci_ers_result_t cxl_error_detected(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlmd->dev; - bool ue; + struct device *cxlmd_dev =3D &cxlds->cxlmd->dev; =20 - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; - } + guard(device)(cxlmd_dev); =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. - */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras= ); - } - - - switch (state) { - case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: + if (!dev->driver) { dev_warn(&pdev->dev, - "%s: frozen state error detected, disable CXL.mem\n", + "%s: memdev disabled, abort error handling\n", dev_name(dev)); - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - dev_warn(&pdev->dev, - "failure state error detected, request disconnect\n"); return PCI_ERS_RESULT_DISCONNECT; } - return PCI_ERS_RESULT_NEED_RESET; + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + /* + * A frozen channel indicates an impending reset which is fatal to + * CXL.mem operation, and will likely crash the system. On the off + * chance the situation is recoverable dump the status of the RAS + * capability registers and bounce the active state of the memdev. + */ + return cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras); } EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); + +pci_ers_result_t pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error) +{ + pci_ers_result_t rc; + + rc =3D cxl_error_detected(&pdev->dev); + if (rc =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(pci_error_detected, "CXL"); diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index a6da0abfa506..ccf0ca36bc00 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -79,19 +79,4 @@ struct cxl_dev_state; int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhd= m, struct cxl_endpoint_dvsec_info *info); void read_cdat_data(struct cxl_port *port); - -#ifdef CONFIG_CXL_RAS -void cxl_cor_error_detected(struct pci_dev *pdev); -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state); -#else -static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } - -static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) -{ - return PCI_ERS_RESULT_NONE; -} -#endif - #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bd95be1f3d5c..6803c2fb906b 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -16,6 +16,7 @@ #include "cxlpci.h" #include "cxl.h" #include "pmu.h" +#include "core/core.h" =20 /** * DOC: cxl pci @@ -1112,11 +1113,11 @@ static void cxl_reset_done(struct pci_dev *pdev) } } =20 -static const struct pci_error_handlers cxl_error_handlers =3D { - .error_detected =3D cxl_error_detected, +static const struct pci_error_handlers pci_error_handlers =3D { + .error_detected =3D pci_error_detected, .slot_reset =3D cxl_slot_reset, .resume =3D cxl_error_resume, - .cor_error_detected =3D cxl_cor_error_detected, + .cor_error_detected =3D pci_cor_error_detected, .reset_done =3D cxl_reset_done, }; =20 @@ -1124,7 +1125,7 @@ static struct pci_driver cxl_pci_driver =3D { .name =3D KBUILD_MODNAME, .id_table =3D cxl_mem_pci_tbl, .probe =3D cxl_pci_probe, - .err_handler =3D &cxl_error_handlers, + .err_handler =3D &pci_error_handlers, .dev_groups =3D cxl_rcd_groups, .driver =3D { .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, diff --git a/include/linux/pci.h b/include/linux/pci.h index 79878243b681..3dcab36c437f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -868,6 +868,9 @@ enum pci_ers_result { =20 /* No AER capabilities registered for the driver */ PCI_ERS_RESULT_NO_AER_DRIVER =3D (__force pci_ers_result_t) 6, + + /* System is unstable, panic. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:38:55.0482 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d761670d-8be8-4949-c626-08dde50a7c26 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6217 Content-Type: text/plain; charset="utf-8" CXL virtual hierarchy (VH) RAS handling for CXL Port devices will be added soon. This requires a notification mechanism for the AER driver to share the AER interrupt with the CXL driver. The notification will be used as an indication for the CXL drivers to handle and log the CXL RAS errors. Note, 'CXL protocol error' terminology will refer to CXL VH and not CXL RCH errors unless specifically noted going forward. Introduce a new file in the AER driver to handle the CXL protocol errors named pci/pcie/cxl_aer.c. Add a kfifo work queue to be used by the AER and CXL drivers. The AER driver will be the sole kfifo producer adding work and the cxl_core will be the sole kfifo consumer removing work. Add the boilerplate kfifo support. Encapsulate the kfifo, RW semaphore, and work pointer in a single structure. Add CXL work queue handler registration functions in the AER driver. Export the functions allowing CXL driver to access. Implement registration functions for the CXL driver to assign or clear the work handler function. Synchronize accesses using the RW semaphore. Introduce 'struct cxl_proto_err_work_data' to serve as the kfifo work data. This will contain a reference to the erring PCI device and the error severity. This will be used when the work is dequeued by the cxl_core drive= r. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - Move RCH implementation to cxl_march.c and RCH declarations to pci/pci.h.= (Terry) - Introduce 'struct cxl_proto_err_kfifo' containing semaphore, fifo, and work struct. (Dan) - Remove embedded struct from cxl_proto_err_work (Dan) - Make 'struct work_struct *cxl_proto_err_work' definition static (Jonathan) - Add check for NULL cxl_proto_err_kfifo to determine if CXL driver is not registered for workqueue. (Dan) --- drivers/pci/pci.h | 4 ++ drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/aer.c | 50 ++-------------- drivers/pci/pcie/cxl_aer.c | 120 +++++++++++++++++++++++++++++++++++++ include/linux/aer.h | 21 +++++++ 5 files changed, 150 insertions(+), 46 deletions(-) create mode 100644 drivers/pci/pcie/cxl_aer.c diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 417a088d815f..cfa75903dd3f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1179,10 +1179,14 @@ static inline void cxl_rch_enable_rcec(struct pci_d= ev *rcec) { } void pci_aer_unmask_internal_errors(struct pci_dev *dev); bool cxl_error_is_native(struct pci_dev *dev); bool is_internal_error(struct aer_err_info *info); +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info); +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info); #else static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } static inline bool cxl_error_is_native(struct pci_dev *dev) { return false= ; } static inline bool is_internal_error(struct aer_err_info *info) { return f= alse; } +static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info = *info) { return false; } +static inline void cxl_forward_error(struct pci_dev *pdev, struct aer_err_= info *info) { } #endif =20 #endif /* DRIVERS_PCI_H */ diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 07c299dbcdd7..bfe5bb5a3c89 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_PCIEPORTBUS) +=3D pcieportdrv.o bwctrl.o obj-y +=3D aspm.o obj-$(CONFIG_PCIEAER) +=3D aer.o err.o tlp.o obj-$(CONFIG_CXL_RCH_RAS) +=3D rch_aer.o +obj-$(CONFIG_CXL_RAS) +=3D cxl_aer.o obj-$(CONFIG_PCIEAER_INJECT) +=3D aer_inject.o obj-$(CONFIG_PCIE_PME) +=3D pme.o obj-$(CONFIG_PCIE_DPC) +=3D dpc.o diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index ed1de9256898..627d89ccea9c 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1092,51 +1092,6 @@ static bool find_source_device(struct pci_dev *paren= t, return true; } =20 -#ifdef CONFIG_CXL_RAS - -/** - * pci_aer_unmask_internal_errors - unmask internal errors - * @dev: pointer to the pci_dev data structure - * - * Unmask internal errors in the Uncorrectable and Correctable Error - * Mask registers. - * - * Note: AER must be enabled and supported by the device which must be - * checked in advance, e.g. with pcie_aer_is_native(). - */ -void pci_aer_unmask_internal_errors(struct pci_dev *dev) -{ - int aer =3D dev->aer_cap; - u32 mask; - - pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); - mask &=3D ~PCI_ERR_UNC_INTN; - pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask); - - pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); - mask &=3D ~PCI_ERR_COR_INTERNAL; - pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); -} -EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL"); - -bool cxl_error_is_native(struct pci_dev *dev) -{ - struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); - - return (pcie_ports_native || host->native_aer); -} -EXPORT_SYMBOL_NS_GPL(cxl_error_is_native, "CXL"); - -bool is_internal_error(struct aer_err_info *info) -{ - if (info->severity =3D=3D AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; - - return info->status & PCI_ERR_UNC_INTN; -} -EXPORT_SYMBOL_NS_GPL(is_internal_error, "CXL"); -#endif /* CONFIG_CXL_RAS */ - /** * pci_aer_handle_error - handle logging error into an event log * @dev: pointer to pci_dev data structure of error source device @@ -1173,7 +1128,10 @@ static void pci_aer_handle_error(struct pci_dev *dev= , struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { cxl_rch_handle_error(dev, info); - pci_aer_handle_error(dev, info); + if (is_cxl_error(dev, info)) + cxl_forward_error(dev, info); + else + pci_aer_handle_error(dev, info); pci_dev_put(dev); } =20 diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c new file mode 100644 index 000000000000..74e6d2d04ab6 --- /dev/null +++ b/drivers/pci/pcie/cxl_aer.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2025 AMD Corporation. All rights reserved. */ + +#include +#include +#include +#include +#include +#include "../pci.h" + +#define CXL_ERROR_SOURCES_MAX 128 + +struct cxl_proto_err_kfifo { + struct work_struct *work; + struct rw_semaphore rw_sema; + DECLARE_KFIFO(fifo, struct cxl_proto_err_work_data, + CXL_ERROR_SOURCES_MAX); +}; + +static struct cxl_proto_err_kfifo cxl_proto_err_kfifo =3D { + .rw_sema =3D __RWSEM_INITIALIZER(cxl_proto_err_kfifo.rw_sema) +}; + +/** + * pci_aer_unmask_internal_errors - unmask internal errors + * @dev: pointer to the pci_dev data structure + * + * Unmask internal errors in the Uncorrectable and Correctable Error + * Mask registers. + * + * Note: AER must be enabled and supported by the device which must be + * checked in advance, e.g. with pcie_aer_is_native(). + */ +void pci_aer_unmask_internal_errors(struct pci_dev *dev) +{ + int aer =3D dev->aer_cap; + u32 mask; + + pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); + mask &=3D ~PCI_ERR_UNC_INTN; + pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask); + + pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); + mask &=3D ~PCI_ERR_COR_INTERNAL; + pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); +} +EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL"); + +bool cxl_error_is_native(struct pci_dev *dev) +{ + struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); + + return (pcie_ports_native || host->native_aer); +} +EXPORT_SYMBOL_NS_GPL(cxl_error_is_native, "CXL"); + +bool is_internal_error(struct aer_err_info *info) +{ + if (info->severity =3D=3D AER_CORRECTABLE) + return info->status & PCI_ERR_COR_INTERNAL; + + return info->status & PCI_ERR_UNC_INTN; +} +EXPORT_SYMBOL_NS_GPL(is_internal_error, "CXL"); + +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + if (!info || !info->is_cxl) + return false; + + if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + return false; + + return is_internal_error(info); +} +EXPORT_SYMBOL_NS_GPL(is_cxl_error, "CXL"); + +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + struct cxl_proto_err_work_data wd =3D (struct cxl_proto_err_work_data) { + .severity =3D info->severity, + .pdev =3D pdev + }; + + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema); + + if (!cxl_proto_err_kfifo.work) { + dev_warn_once(&pdev->dev, "CXL driver is not registered for kfifo"); + return; + } + + if (!kfifo_put(&cxl_proto_err_kfifo.fifo, wd)) { + dev_err_ratelimited(&pdev->dev, "CXL kfifo overflow\n"); + return; + } + + schedule_work(cxl_proto_err_kfifo.work); +} +EXPORT_SYMBOL_NS_GPL(cxl_forward_error, "CXL"); + +void cxl_register_proto_err_work(struct work_struct *work) +{ + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema); + cxl_proto_err_kfifo.work =3D work; +} +EXPORT_SYMBOL_NS_GPL(cxl_register_proto_err_work, "CXL"); + +void cxl_unregister_proto_err_work(void) +{ + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema); + cxl_proto_err_kfifo.work =3D NULL; +} +EXPORT_SYMBOL_NS_GPL(cxl_unregister_proto_err_work, "CXL"); + +int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd) +{ + guard(rwsem_read)(&cxl_proto_err_kfifo.rw_sema); + return kfifo_get(&cxl_proto_err_kfifo.fifo, wd); +} +EXPORT_SYMBOL_NS_GPL(cxl_proto_err_kfifo_get, "CXL"); diff --git a/include/linux/aer.h b/include/linux/aer.h index 02940be66324..f8eb32805957 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -10,6 +10,7 @@ =20 #include #include +#include =20 #define AER_NONFATAL 0 #define AER_FATAL 1 @@ -53,6 +54,16 @@ struct aer_capability_regs { u16 uncor_err_source; }; =20 +/** + * struct cxl_proto_err_work_data - Error information used in CXL error ha= ndling + * @severity: AER severity + * @pdev: PCI device detecting the error + */ +struct cxl_proto_err_work_data { + int severity; + struct pci_dev *pdev; +}; + #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); @@ -64,6 +75,16 @@ static inline int pci_aer_clear_nonfatal_status(struct p= ci_dev *dev) static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } #endif =20 +#ifdef CONFIG_CXL_RAS +int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd); +void cxl_register_proto_err_work(struct work_struct *work); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:39:05.9480 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68c7e29f-2175-404f-f31e-08dde50a82a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9329 Content-Type: text/plain; charset="utf-8" The AER driver is now designed to forward CXL protocol errors to the CXL driver. Update the CXL driver with functionality to dequeue the forwarded CXL error from the kfifo. Also, update the CXL driver to begin the protocol error handling processing using the work received from the FIFO. Update function cxl_proto_err_work_fn() to dequeue work forwarded by the AER service driver. This will begin the CXL protocol error processing with a call to cxl_handle_proto_error(). Introduce logic to take the SBDF values from 'struct cxl_proto_error_info' and use in discovering the erring PCI device. The call to pci_get_domain_bu= s_and_slot() will return a reference counted 'struct pci_dev *'. This will serve as reference count to prevent releasing the CXL Endpoint's mapped RAS while handling the error. Use scope base __free() to put the reference count. This will change when adding support for CXL port devices in the future. Implement cxl_handle_proto_error() to differentiate between Restricted CXL Host (RCH) protocol errors and CXL virtual host (VH) protocol errors. Maintain the existing RCH handling. Export the AER driver's pcie_walk_rcec() allowing the CXL driver to walk the RCEC's secondary bus. VH correctable error (CE) processing will call the CXL CE handler. VH uncorrectable errors (UCE) will call cxl_do_recovery(), implemented as a stub for now and to be updated in future patch. Export pci_aer_clean_fatal_= status() and pci_clean_device_status() used to clean up AER status after handling. Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - Reword patch commit message to remove RCiEP details (Jonathan) - Add #include (Terry) - is_cxl_rcd() - Fix short comment message wrap (Jonathan) - is_cxl_rcd() - Combine return calls into 1 (Jonathan) - cxl_handle_proto_error() - Move comment earlier (Jonathan) - Usse FIELD_GET() in discovering class code (Jonathan) - Remove BDF from cxl_proto_err_work_data. Use 'struct pci_dev *' (Dan) --- drivers/cxl/core/ras.c | 68 ++++++++++++++++++++++++++++++++++------- drivers/pci/pci.c | 1 + drivers/pci/pci.h | 7 ----- drivers/pci/pcie/aer.c | 1 + drivers/pci/pcie/rcec.c | 1 + include/linux/aer.h | 2 ++ include/linux/pci.h | 10 ++++++ 7 files changed, 72 insertions(+), 18 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index b285448c2d9c..a2e95c49f965 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -118,17 +118,6 @@ static void cxl_cper_prot_err_work_fn(struct work_stru= ct *work) } static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn); =20 -int cxl_ras_init(void) -{ - return cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work); -} - -void cxl_ras_exit(void) -{ - cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); - cancel_work_sync(&cxl_cper_prot_err_work); -} - static pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, voi= d __iomem *ras_base); static void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iome= m *ras_base); =20 @@ -331,6 +320,10 @@ void cxl_endpoint_port_init_ras(struct cxl_port *ep) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_port_init_ras, "CXL"); =20 +static void cxl_do_recovery(struct device *dev) +{ +} + static void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iome= m *ras_base) { void __iomem *addr; @@ -472,3 +465,56 @@ pci_ers_result_t pci_error_detected(struct pci_dev *pd= ev, return rc; } EXPORT_SYMBOL_NS_GPL(pci_error_detected, "CXL"); + +static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_inf= o) +{ + struct pci_dev *pdev =3D err_info->pdev; + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct cxl_memdev *cxlmd =3D cxlds->cxlmd; + struct device *host_dev __free(put_device) =3D get_device(&cxlmd->dev); + + if (err_info->severity =3D=3D AER_CORRECTABLE) { + int aer =3D pdev->aer_cap; + + if (aer) + pci_clear_and_set_config_dword(pdev, + aer + PCI_ERR_COR_STATUS, + 0, PCI_ERR_COR_INTERNAL); + + cxl_cor_error_detected(&cxlmd->dev); + + pcie_clear_device_status(pdev); + } else { + cxl_do_recovery(&cxlmd->dev); + } +} + +static void cxl_proto_err_work_fn(struct work_struct *work) +{ + struct cxl_proto_err_work_data wd; + + while (cxl_proto_err_kfifo_get(&wd)) + cxl_handle_proto_error(&wd); +} + +static struct work_struct cxl_proto_err_work; +static DECLARE_WORK(cxl_proto_err_work, cxl_proto_err_work_fn); + +int cxl_ras_init(void) +{ + if (cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work)) + pr_err("Failed to initialize CXL RAS CPER\n"); + + cxl_register_proto_err_work(&cxl_proto_err_work); + + return 0; +} + +void cxl_ras_exit(void) +{ + cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); + cancel_work_sync(&cxl_cper_prot_err_work); + + cxl_unregister_proto_err_work(); + cancel_work_sync(&cxl_proto_err_work); +} diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d775ed37a79b..2c9827690cb3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2328,6 +2328,7 @@ void pcie_clear_device_status(struct pci_dev *dev) pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta); pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta); } +EXPORT_SYMBOL_NS_GPL(pcie_clear_device_status, "CXL"); #endif =20 /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index cfa75903dd3f..69ff7c2d214f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -671,16 +671,10 @@ static inline bool pci_dpc_recovered(struct pci_dev *= pdev) { return false; } void pci_rcec_init(struct pci_dev *dev); void pci_rcec_exit(struct pci_dev *dev); void pcie_link_rcec(struct pci_dev *rcec); -void pcie_walk_rcec(struct pci_dev *rcec, - int (*cb)(struct pci_dev *, void *), - void *userdata); #else static inline void pci_rcec_init(struct pci_dev *dev) { } static inline void pci_rcec_exit(struct pci_dev *dev) { } static inline void pcie_link_rcec(struct pci_dev *rcec) { } -static inline void pcie_walk_rcec(struct pci_dev *rcec, - int (*cb)(struct pci_dev *, void *), - void *userdata) { } #endif =20 #ifdef CONFIG_PCI_ATS @@ -1022,7 +1016,6 @@ void pci_restore_aer_state(struct pci_dev *dev); static inline void pci_no_aer(void) { } static inline void pci_aer_init(struct pci_dev *d) { } static inline void pci_aer_exit(struct pci_dev *d) { } -static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINV= AL; } static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -= EINVAL; } static inline void pci_save_aer_state(struct pci_dev *dev) { } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 627d89ccea9c..45abe1622316 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -288,6 +288,7 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev) if (status) pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); } +EXPORT_SYMBOL_GPL(pci_aer_clear_fatal_status); =20 /** * pci_aer_raw_clear_status - Clear AER error registers. diff --git a/drivers/pci/pcie/rcec.c b/drivers/pci/pcie/rcec.c index d0bcd141ac9c..fb6cf6449a1d 100644 --- a/drivers/pci/pcie/rcec.c +++ b/drivers/pci/pcie/rcec.c @@ -145,6 +145,7 @@ void pcie_walk_rcec(struct pci_dev *rcec, int (*cb)(str= uct pci_dev *, void *), =20 walk_rcec(walk_rcec_helper, &rcec_data); } +EXPORT_SYMBOL_NS_GPL(pcie_walk_rcec, "CXL"); =20 void pci_rcec_init(struct pci_dev *dev) { diff --git a/include/linux/aer.h b/include/linux/aer.h index f8eb32805957..1f79f0be4bf7 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -66,12 +66,14 @@ struct cxl_proto_err_work_data { =20 #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); +void pci_aer_clear_fatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); #else static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) { return -EINVAL; } +static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } #endif =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 3dcab36c437f..3407d687459d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1804,6 +1804,9 @@ extern bool pcie_ports_native; =20 int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_r= eq, bool use_lt); +void pcie_walk_rcec(struct pci_dev *rcec, + int (*cb)(struct pci_dev *, void *), + void *userdata); #else #define pcie_ports_disabled true #define pcie_ports_native false @@ -1814,8 +1817,15 @@ static inline int pcie_set_target_speed(struct pci_d= ev *port, { return -EOPNOTSUPP; } + +static inline void pcie_walk_rcec(struct pci_dev *rcec, + int (*cb)(struct pci_dev *, void *), + void *userdata) { } + #endif =20 +void pcie_clear_device_status(struct pci_dev *dev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:39:17.3585 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b8801d9-8da9-4071-2642-08dde50a8973 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4160 Content-Type: text/plain; charset="utf-8" Introduce CXL error handlers for CXL Port devices. Add functions cxl_port_cor_error_detected() and cxl_port_error_detected(). These will serve as the handlers for all CXL Port devices. Introduce cxl_get_ras_base() to provide the RAS base address needed by the handlers. Update cxl_handle_proto_error() to call the CXL Port or CXL Endpoint handler depending on which CXL device reports the error. Implement cxl_get_ras_base() to return the cached RAS register address of a CXL Root Port, CXL Downstream Port, or CXL Upstream Port. Introduce get_pci_cxl_host_dev() to return the host responsible for releasing the RAS mapped resources. CXL endpoints do not use a host to manage its resources, allow for NULL in the case of an EP. Use reference count increment on the host to prevent resource release. Make the caller responsible for the reference decrement. Update the AER driver's is_cxl_error() PCI type check because CXL Port devices are now supported. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - None --- drivers/cxl/core/core.h | 9 ++ drivers/cxl/core/port.c | 4 +- drivers/cxl/core/ras.c | 176 +++++++++++++++++++++++++++++++++++-- drivers/pci/pcie/cxl_aer.c | 5 +- 4 files changed, 186 insertions(+), 8 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 6e3e7f2e0e2d..7e66fbb07b8a 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -155,6 +155,8 @@ pci_ers_result_t pci_error_detected(struct pci_dev *pde= v, void pci_cor_error_detected(struct pci_dev *pdev); void cxl_cor_error_detected(struct device *dev); pci_ers_result_t cxl_error_detected(struct device *dev); +void cxl_port_cor_error_detected(struct device *dev); +pci_ers_result_t cxl_port_error_detected(struct device *dev); #else static inline int cxl_ras_init(void) { @@ -179,9 +181,16 @@ static inline pci_ers_result_t cxl_error_detected(stru= ct device *dev) { return PCI_ERS_RESULT_NONE; } +static inline void cxl_port_cor_error_detected(struct device *dev) { } +static inline pci_ers_result_t cxl_port_error_detected(struct device *dev) +{ + return PCI_ERS_RESULT_NONE; +} #endif // CONFIG_CXL_RAS =20 int cxl_gpf_port_setup(struct cxl_dport *dport); +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport); =20 #ifdef CONFIG_CXL_FEATURES struct cxl_feat_entry * diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 29197376b18e..758fb73374c1 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1335,8 +1335,8 @@ static struct cxl_port *__find_cxl_port(struct cxl_fi= nd_port_ctx *ctx) return NULL; } =20 -static struct cxl_port *find_cxl_port(struct device *dport_dev, - struct cxl_dport **dport) +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport) { struct cxl_find_port_ctx ctx =3D { .dport_dev =3D dport_dev, diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index a2e95c49f965..536ca9c815ce 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -251,6 +251,154 @@ static void cxl_dport_map_ras(struct cxl_dport *dport) dev_dbg(dev, "Failed to map RAS capability.\n"); } =20 +static int match_uport(struct device *dev, const void *data) +{ + const struct device *uport_dev =3D data; + struct cxl_port *port; + + if (!is_cxl_port(dev)) + return 0; + + port =3D to_cxl_port(dev); + + return port->uport_dev =3D=3D uport_dev; +} + +static void __iomem *cxl_get_ras_base(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport =3D NULL; + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port(&pdev->dev,= &dport); + + if (!dport || !dport->dport_dev) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + + if (!dport) + return NULL; + + return dport->regs.ras; + } + case PCI_EXP_TYPE_UPSTREAM: + { + struct cxl_port *port; + struct device *port_dev __free(put_device) =3D + bus_find_device(&cxl_bus_type, NULL, + &pdev->dev, match_uport); + + if (!port_dev || !is_cxl_port(port_dev)) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + + port =3D to_cxl_port(port_dev); + if (!port) + return NULL; + + return port->uport_regs.ras; + } + } + + dev_warn_once(dev, "Error: Unsupported device type (%X)", pci_pcie_type(p= dev)); + return NULL; +} + +static struct device *pci_to_cxl_dev(struct pci_dev *pdev) +{ + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport =3D NULL; + struct cxl_port *port __free(put_cxl_port) =3D + find_cxl_port(&pdev->dev, &dport); + + if (!dport) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + + return dport->dport_dev; + } + case PCI_EXP_TYPE_UPSTREAM: + { + struct cxl_port *port; + struct device *port_dev __free(put_device) =3D + bus_find_device(&cxl_bus_type, NULL, + &pdev->dev, match_uport); + + if (!port_dev || !is_cxl_port(port_dev)) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + + port =3D to_cxl_port(port_dev); + if (!port) + return NULL; + + return port->uport_dev; + } + case PCI_EXP_TYPE_ENDPOINT: + { + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + + return cxlds->dev; + } + } + + pci_warn_once(pdev, "Error: Unsupported device type (%X)", pci_pcie_type(= pdev)); + return NULL; +} + + +/* + * Return 'struct device *' responsible for freeing pdev's CXL resources. + * Caller is responsible for reference count decrementing the return + * 'struct device *'. + * + * dev: Find the host of this dev + */ +static struct device *get_cxl_host_dev(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport =3D NULL; + struct cxl_port *port =3D find_cxl_port(&pdev->dev, &dport); + + if (!port) + return NULL; + + return &port->dev; + } + case PCI_EXP_TYPE_UPSTREAM: + { + struct device *port_dev =3D bus_find_device(&cxl_bus_type, NULL, + &pdev->dev, match_uport); + + if (!port_dev || !is_cxl_port(port_dev)) + return NULL; + + return port_dev; + } + /* Endpoint resources are managed by endpoint itself */ + case PCI_EXP_TYPE_ENDPOINT: + return NULL; + } + + dev_warn_once(dev, "Error: Unsupported device type (%X)", pci_pcie_type(p= dev)); + return NULL; +} + /** * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport * @dport: the cxl_dport that needs to be initialized @@ -399,6 +547,22 @@ static pci_ers_result_t cxl_handle_ras(struct device *= dev, u64 serial, void __io return PCI_ERS_RESULT_PANIC; } =20 +void cxl_port_cor_error_detected(struct device *dev) +{ + void __iomem *ras_base =3D cxl_get_ras_base(dev); + + cxl_handle_cor_ras(dev, 0, ras_base); +} +EXPORT_SYMBOL_NS_GPL(cxl_port_cor_error_detected, "CXL"); + +pci_ers_result_t cxl_port_error_detected(struct device *dev) +{ + void __iomem *ras_base =3D cxl_get_ras_base(dev); + + return cxl_handle_ras(dev, 0, ras_base); +} +EXPORT_SYMBOL_NS_GPL(cxl_port_error_detected, "CXL"); + void cxl_cor_error_detected(struct device *dev) { struct pci_dev *pdev =3D to_pci_dev(dev); @@ -469,9 +633,8 @@ EXPORT_SYMBOL_NS_GPL(pci_error_detected, "CXL"); static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_inf= o) { struct pci_dev *pdev =3D err_info->pdev; - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *host_dev __free(put_device) =3D get_device(&cxlmd->dev); + struct device *dev =3D pci_to_cxl_dev(pdev); + struct device *host_dev __free(put_device) =3D get_cxl_host_dev(&pdev->de= v); =20 if (err_info->severity =3D=3D AER_CORRECTABLE) { int aer =3D pdev->aer_cap; @@ -481,11 +644,14 @@ static void cxl_handle_proto_error(struct cxl_proto_e= rr_work_data *err_info) aer + PCI_ERR_COR_STATUS, 0, PCI_ERR_COR_INTERNAL); =20 - cxl_cor_error_detected(&cxlmd->dev); + if (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ENDPOINT) + cxl_error_detected(&pdev->dev); + else + cxl_port_cor_error_detected(dev); =20 pcie_clear_device_status(pdev); } else { - cxl_do_recovery(&cxlmd->dev); + cxl_do_recovery(dev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:39:28.4210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a20f5348-7bb7-4a4e-3e00-08dde50a900b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8935 Content-Type: text/plain; charset="utf-8" CXL uncorrectable errors (UCE) will soon be handled separately from the PCI AER handling. The merge_result() function can be made common to use in both handling paths. Rename the PCI subsystem's merge_result() to be pci_ers_merge_result(). Export pci_ers_merge_result() to make available for the CXL and other drivers to use. Update pci_ers_merge_result() to support recently introduced PCI_ERS_RESULT= _PANIC result. Signed-off-by: Terry Bowman Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - New patch - pci_ers_merge_result() - Change export to non-namespace and rename to be pci_ers_merge_result() - Move pci_ers_merge_result() definition to pci.h. Needs pci_ers_result --- drivers/pci/pcie/err.c | 14 +++++++++----- include/linux/pci.h | 11 +++++++++++ 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index de6381c690f5..368bad0cb90e 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -21,9 +21,12 @@ #include "portdrv.h" #include "../pci.h" =20 -static pci_ers_result_t merge_result(enum pci_ers_result orig, - enum pci_ers_result new) +pci_ers_result_t pci_ers_merge_result(enum pci_ers_result orig, + enum pci_ers_result new) { + if (new =3D=3D PCI_ERS_RESULT_PANIC) + return PCI_ERS_RESULT_PANIC; + if (new =3D=3D PCI_ERS_RESULT_NO_AER_DRIVER) return PCI_ERS_RESULT_NO_AER_DRIVER; =20 @@ -45,6 +48,7 @@ static pci_ers_result_t merge_result(enum pci_ers_result = orig, =20 return orig; } +EXPORT_SYMBOL(pci_ers_merge_result); =20 static int report_error_detected(struct pci_dev *dev, pci_channel_state_t state, @@ -81,7 +85,7 @@ static int report_error_detected(struct pci_dev *dev, vote =3D err_handler->error_detected(dev, state); } pci_uevent_ers(dev, vote); - *result =3D merge_result(*result, vote); + *result =3D pci_ers_merge_result(*result, vote); device_unlock(&dev->dev); return 0; } @@ -121,7 +125,7 @@ static int report_mmio_enabled(struct pci_dev *dev, voi= d *data) =20 err_handler =3D pdrv->err_handler; vote =3D err_handler->mmio_enabled(dev); - *result =3D merge_result(*result, vote); + *result =3D pci_ers_merge_result(*result, vote); out: device_unlock(&dev->dev); return 0; @@ -140,7 +144,7 @@ static int report_slot_reset(struct pci_dev *dev, void = *data) =20 err_handler =3D pdrv->err_handler; vote =3D err_handler->slot_reset(dev); - *result =3D merge_result(*result, vote); + *result =3D pci_ers_merge_result(*result, vote); out: device_unlock(&dev->dev); return 0; diff --git a/include/linux/pci.h b/include/linux/pci.h index 3407d687459d..ff6812b2b9b6 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2760,6 +2760,17 @@ static inline bool pci_is_thunderbolt_attached(struc= t pci_dev *pdev) void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:39:39.5647 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 402f9bd8-80eb-4946-8345-08dde50a96af X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB9072 Content-Type: text/plain; charset="utf-8" Populate the cxl_do_recovery() function with uncorrectable protocol error (= UCE) handling. Follow similar design as found in PCIe error driver, pcie_do_recovery(). One difference is cxl_do_recovery() will treat all UCEs as fatal with a kernel panic. This is to prevent corruption on CXL memory. Introduce cxl_walk_port(). Make this analogous to pci_walk_bridge() but wal= king CXL ports instead. This will iterate through the CXL topology from the erroring device through the downstream CXL Ports and Endpoints. Export pci_aer_clear_fatal_status() for CXL to use if a UCE is not found. Signed-off-by: Terry Bowman Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - pci_ers_merge_results() - Move to earlier patch --- drivers/cxl/core/port.c | 1 + drivers/cxl/core/ras.c | 94 +++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 2 - include/linux/aer.h | 2 + 4 files changed, 97 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 758fb73374c1..085c8620a797 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1347,6 +1347,7 @@ struct cxl_port *find_cxl_port(struct device *dport_d= ev, port =3D __find_cxl_port(&ctx); return port; } +EXPORT_SYMBOL_NS_GPL(find_cxl_port, "CXL"); =20 static struct cxl_port *find_cxl_port_at(struct cxl_port *parent_port, struct device *dport_dev, diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 536ca9c815ce..3da675f72616 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "trace.h" =20 static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev, @@ -468,8 +469,101 @@ void cxl_endpoint_port_init_ras(struct cxl_port *ep) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_port_init_ras, "CXL"); =20 +static int cxl_report_error_detected(struct device *dev, void *data) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + pci_ers_result_t vote, *result =3D data; + + guard(device)(dev); + + if (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ENDPOINT) + vote =3D cxl_error_detected(dev); + else + vote =3D cxl_port_error_detected(dev); + + vote =3D cxl_error_detected(dev); + *result =3D pci_ers_merge_result(*result, vote); + + return 0; +} + +static int match_port_by_parent_dport(struct device *dev, const void *dpor= t_dev) +{ + struct cxl_port *port; + + if (!is_cxl_port(dev)) + return 0; + + port =3D to_cxl_port(dev); + + return port->parent_dport->dport_dev =3D=3D dport_dev; +} + +static void cxl_walk_port(struct device *port_dev, + int (*cb)(struct device *, void *), + void *userdata) +{ + struct cxl_dport *dport =3D NULL; + struct cxl_port *port; + unsigned long index; + + if (!port_dev) + return; + + port =3D to_cxl_port(port_dev); + if (port->uport_dev && dev_is_pci(port->uport_dev)) + cb(port->uport_dev, userdata); + + xa_for_each(&port->dports, index, dport) + { + struct device *child_port_dev __free(put_device) =3D + bus_find_device(&cxl_bus_type, &port->dev, dport, + match_port_by_parent_dport); + + cb(dport->dport_dev, userdata); + + cxl_walk_port(child_port_dev, cxl_report_error_detected, userdata); + } + + if (is_cxl_endpoint(port)) + cb(port->uport_dev->parent, userdata); +} + static void cxl_do_recovery(struct device *dev) { + pci_ers_result_t status =3D PCI_ERS_RESULT_CAN_RECOVER; + struct pci_dev *pdev =3D to_pci_dev(dev); + struct cxl_dport *dport; + struct cxl_port *port; + + if ((pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) || + (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM)) { + port =3D find_cxl_port(&pdev->dev, &dport); + } else if (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_UPSTREAM) { + struct device *port_dev =3D bus_find_device(&cxl_bus_type, NULL, + &pdev->dev, match_uport); + port =3D to_cxl_port(port_dev); + } + + if (!port) + return; + + cxl_walk_port(&port->dev, cxl_report_error_detected, &status); + if (status =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + /* + * If we have native control of AER, clear error status in the device + * that detected the error. If the platform retained control of AER, + * it is responsible for clearing this status. In that case, the + * signaling device may not even be visible to the OS. + */ + if (cxl_error_is_native(pdev)) { + pcie_clear_device_status(pdev); + pci_aer_clear_nonfatal_status(pdev); + pci_aer_clear_fatal_status(pdev); + } + put_device(&port->dev); } =20 static void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iome= m *ras_base) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 69ff7c2d214f..0c4f73dd645f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1170,13 +1170,11 @@ static inline void cxl_rch_enable_rcec(struct pci_d= ev *rcec) { } =20 #ifdef CONFIG_CXL_RAS void pci_aer_unmask_internal_errors(struct pci_dev *dev); -bool cxl_error_is_native(struct pci_dev *dev); bool is_internal_error(struct aer_err_info *info); bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info); void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info); #else static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } -static inline bool cxl_error_is_native(struct pci_dev *dev) { return false= ; } static inline bool is_internal_error(struct aer_err_info *info) { return f= alse; } static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info = *info) { return false; } static inline void cxl_forward_error(struct pci_dev *pdev, struct aer_err_= info *info) { } diff --git a/include/linux/aer.h b/include/linux/aer.h index 1f79f0be4bf7..751a026fea73 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -81,10 +81,12 @@ static inline int pcie_aer_is_native(struct pci_dev *de= v) { return 0; } int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd); void cxl_register_proto_err_work(struct work_struct *work); void cxl_unregister_proto_err_work(void); +bool cxl_error_is_native(struct pci_dev *dev); #else static inline int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *= wd) { return 0; } static inline void cxl_register_proto_err_work(struct work_struct *work) {= } static inline void cxl_unregister_proto_err_work(void) { } +static inline bool cxl_error_is_native(struct pci_dev *dev) { return false= ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:39:50.6082 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e0885c2-24cd-4b26-877f-08dde50a9d44 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7694 Content-Type: text/plain; charset="utf-8" CXL protocol errors are not enabled for all CXL devices after boot. These must be enabled inorder to process CXL protocol errors. Introduce cxl_unmask_proto_interrupts() to call pci_aer_unmask_internal_err= ors(). pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized. But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable A= ER correctable internal errors and uncorrectable internal errors for all CXL devices. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - Added check for valid PCI devices in is_cxl_error() (Terry) - Removed check for RCiEP in cxl_handle_proto_err() and cxl_report_error_detected() (Terry) --- drivers/cxl/core/ras.c | 26 +++++++++++++++++++++++++- drivers/pci/pci.h | 2 -- include/linux/aer.h | 2 ++ 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 3da675f72616..90ea0dfb942f 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -122,6 +122,21 @@ static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_p= rot_err_work_fn); static pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, voi= d __iomem *ras_base); static void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iome= m *ras_base); =20 +static void cxl_unmask_proto_interrupts(struct device *dev) +{ + struct pci_dev *pdev __free(pci_dev_put) =3D + pci_dev_get(to_pci_dev(dev)); + + if (!pdev->aer_cap) { + pdev->aer_cap =3D pci_find_ext_capability(pdev, + PCI_EXT_CAP_ID_ERR); + if (!pdev->aer_cap) + return; + } + + pci_aer_unmask_internal_errors(pdev); +} + #ifdef CONFIG_CXL_RCH_RAS static void cxl_dport_map_rch_aer(struct cxl_dport *dport) { @@ -418,7 +433,10 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dp= ort, struct device *host) =20 cxl_dport_map_rch_aer(dport); cxl_disable_rch_root_ints(dport); + return; } + + cxl_unmask_proto_interrupts(dport->dport_dev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 @@ -429,8 +447,12 @@ static void cxl_uport_init_ras_reporting(struct cxl_po= rt *port, =20 map->host =3D host; if (cxl_map_component_regs(map, &port->uport_regs, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_dbg(&port->dev, "Failed to map RAS capability\n"); + return; + } + + cxl_unmask_proto_interrupts(port->uport_dev); } =20 void cxl_switch_port_init_ras(struct cxl_port *port) @@ -466,6 +488,8 @@ void cxl_endpoint_port_init_ras(struct cxl_port *ep) } =20 cxl_dport_init_ras_reporting(parent_dport, cxlmd->cxlds->dev); + + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev); } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_port_init_ras, "CXL"); =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0c4f73dd645f..090b52a26862 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1169,12 +1169,10 @@ static inline void cxl_rch_enable_rcec(struct pci_d= ev *rcec) { } #endif =20 #ifdef CONFIG_CXL_RAS -void pci_aer_unmask_internal_errors(struct pci_dev *dev); bool is_internal_error(struct aer_err_info *info); bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info); void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info); #else -static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } static inline bool is_internal_error(struct aer_err_info *info) { return f= alse; } static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info = *info) { return false; } static inline void cxl_forward_error(struct pci_dev *pdev, struct aer_err_= info *info) { } diff --git a/include/linux/aer.h b/include/linux/aer.h index 751a026fea73..4e2fc55f2497 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -82,11 +82,13 @@ int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_d= ata *wd); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 01:40:01.7060 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73034174-0a8d-486f-eb5a-08dde50aa3e1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9313 Content-Type: text/plain; charset="utf-8" During CXL device cleanup the CXL PCIe Port device interrupts remain enabled. This potentially allows unnecessary interrupt processing on behalf of the CXL errors while the device is destroyed. Disable CXL protocol errors by setting the CXL devices' AER mask register. Introduce pci_aer_mask_internal_errors() similar to pci_aer_unmask_internal= _errors(). Introduce cxl_mask_proto_interrupts() to call pci_aer_mask_internal_errors(= ). Add calls to cxl_mask_proto_interrupts() within CXL Port teardown for CXL Root Ports, CXL Downstream Switch Ports, CXL Upstream Switch Ports, and CXL Endpoints. Follow the same "bottom-up" approach used during CXL Port teardown. Implement cxl_mask_proto_interrupts() in a header file to avoid introducing Kconfig ifdefs in cxl/core/port.c. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Gregory Price Tested-by: Srinivasulu Thanneeru --- Changes in v10->v11: - Removed guard() cxl_mask_proto_interrupts(). RP was blocking during testing. (Terry) --- drivers/cxl/core/core.h | 2 ++ drivers/cxl/core/port.c | 6 ++++++ drivers/cxl/core/ras.c | 8 ++++++++ drivers/pci/pcie/cxl_aer.c | 21 +++++++++++++++++++++ include/linux/aer.h | 2 ++ 5 files changed, 39 insertions(+) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 7e66fbb07b8a..385bfd38b778 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -157,6 +157,7 @@ void cxl_cor_error_detected(struct device *dev); pci_ers_result_t cxl_error_detected(struct device *dev); void cxl_port_cor_error_detected(struct device *dev); pci_ers_result_t cxl_port_error_detected(struct device *dev); +void cxl_mask_proto_interrupts(struct device *dev); #else static inline int cxl_ras_init(void) { @@ -186,6 +187,7 @@ static inline pci_ers_result_t cxl_port_error_detected(= struct device *dev) { return PCI_ERS_RESULT_NONE; } +static inline void cxl_mask_proto_interrupts(struct device *dev) { } #endif // CONFIG_CXL_RAS =20 int cxl_gpf_port_setup(struct cxl_dport *dport); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 085c8620a797..bb326dc95d5f 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1428,6 +1428,9 @@ EXPORT_SYMBOL_NS_GPL(cxl_endpoint_autoremove, "CXL"); */ static void delete_switch_port(struct cxl_port *port) { + cxl_mask_proto_interrupts(port->uport_dev); + cxl_mask_proto_interrupts(port->parent_dport->dport_dev); + devm_release_action(port->dev.parent, cxl_unlink_parent_dport, port); devm_release_action(port->dev.parent, cxl_unlink_uport, port); devm_release_action(port->dev.parent, unregister_port, port); @@ -1441,6 +1444,7 @@ static void reap_dports(struct cxl_port *port) device_lock_assert(&port->dev); =20 xa_for_each(&port->dports, index, dport) { + cxl_mask_proto_interrupts(dport->dport_dev); devm_release_action(&port->dev, cxl_dport_unlink, dport); devm_release_action(&port->dev, cxl_dport_remove, dport); devm_kfree(&port->dev, dport); @@ -1471,6 +1475,8 @@ static void cxl_detach_ep(void *data) { struct cxl_memdev *cxlmd =3D data; =20 + cxl_mask_proto_interrupts(cxlmd->cxlds->dev); + for (int i =3D cxlmd->depth - 1; i >=3D 1; i--) { struct cxl_port *port, *parent_port; struct detach_ctx ctx =3D { diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 90ea0dfb942f..564144c2d23f 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -137,6 +137,14 @@ static void cxl_unmask_proto_interrupts(struct device = *dev) pci_aer_unmask_internal_errors(pdev); } =20 +void cxl_mask_proto_interrupts(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + + pci_aer_mask_internal_errors(pdev); +} +EXPORT_SYMBOL_NS_GPL(cxl_mask_proto_interrupts, "CXL"); + #ifdef CONFIG_CXL_RCH_RAS static void cxl_dport_map_rch_aer(struct cxl_dport *dport) { diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c index 6eeff0b78b47..2de2d9e7934b 100644 --- a/drivers/pci/pcie/cxl_aer.c +++ b/drivers/pci/pcie/cxl_aer.c @@ -46,6 +46,27 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev) } EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL"); =20 +/** + * pci_aer_mask_internal_errors - mask internal errors + * @dev: pointer to the pcie_dev data structure + * + * Masks internal errors in the Uncorrectable and Correctable Error + * Mask registers. + * + * Note: AER must be enabled and supported by the device which must be + * checked in advance, e.g. with pcie_aer_is_native(). + */ +void pci_aer_mask_internal_errors(struct pci_dev *dev) +{ + int aer =3D dev->aer_cap; + + pci_clear_and_set_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, + 0, PCI_ERR_UNC_INTN); + pci_clear_and_set_config_dword(dev, aer + PCI_ERR_COR_MASK, + 0, PCI_ERR_COR_INTERNAL); +} +EXPORT_SYMBOL_NS_GPL(pci_aer_mask_internal_errors, "CXL"); + bool cxl_error_is_native(struct pci_dev *dev) { struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); diff --git a/include/linux/aer.h b/include/linux/aer.h index 4e2fc55f2497..82264221ad09 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -83,12 +83,14 @@ void cxl_register_proto_err_work(struct work_struct *wo= rk); void cxl_unregister_proto_err_work(void); bool cxl_error_is_native(struct pci_dev *dev); void pci_aer_unmask_internal_errors(struct pci_dev *dev); +void pci_aer_mask_internal_errors(struct pci_dev *dev); #else static inline int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *= wd) { return 0; } static inline void cxl_register_proto_err_work(struct work_struct *work) {= } static inline void cxl_unregister_proto_err_work(void) { } static inline bool cxl_error_is_native(struct pci_dev *dev) { return false= ; } static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } +static inline void pci_aer_mask_internal_errors(struct pci_dev *dev) { } #endif =20 void pci_print_aer(struct pci_dev *dev, int aer_severity, --=20 2.51.0.rc2.21.ge5ab6b3e5a