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Wed, 27 Aug 2025 15:39:32 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 7939611079706169338 EX-QQ-RecipientCnt: 9 From: Troy Mitchell Date: Wed, 27 Aug 2025 15:39:12 +0800 Subject: [PATCH 5/6] i2c: spacemit: ensure SDA is released after bus reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-k1-i2c-atomic-v1-5-e59bea02d680@linux.spacemit.com> References: <20250827-k1-i2c-atomic-v1-0-e59bea02d680@linux.spacemit.com> In-Reply-To: <20250827-k1-i2c-atomic-v1-0-e59bea02d680@linux.spacemit.com> To: Andi Shyti , Yixun Lan , Alex Elder , Troy Mitchell Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Troy Mitchell X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756280357; l=3354; i=troy.mitchell@linux.spacemit.com; s=20250710; h=from:subject:message-id; bh=N/MIBGWdKMusWYQh+IE7iWqeuc/rxrsn46nwIp2rkh8=; b=Ls/K6GXozvyjgJrMx+La90IrRGLCE0mHghea4y/6w4HrQLk/PPk3a8tKHS40YJbMBVu5yhmGb buX3D46J7S1DMicQ/+EnfV6Z26hm7ozie6c0OIGhr1AaX6YqGbHjpsU X-Developer-Key: i=troy.mitchell@linux.spacemit.com; a=ed25519; pk=lQa7BzLrq8DfZnChqmwJ5qQk8fP2USmY/4xZ2/MSsXc= X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpgz:linux.spacemit.com:qybglogicsvrsz:qybglogicsvrsz3a-0 X-QQ-XMAILINFO: N8arHCzhf4/cmIVcGeLtNQIiaiYPkkgUUhAfUvCuOyuIAnf1iG8c3m+t z4RJwfVL/Z/LzLIguRwb24+e/FwLjgQHUGo6jR6dFBUU0UYWFMKW68NoY64Xm1ZLz5Q9Bri Zp15oc8Ro0qaIo4C2gQuZvIcLfUnE0z0Gb3p3VtLrw551BSxUt3Qzn5AMrzlkq+6oh3355X XeT6KNvdjAIsrTUeSH0ae9DN5TqZ9tLFfvofaNYZDmbAjCtfwV9iesIWf1V/uDEC5VELt0l 09bNb+qSORiivkobuhGCDrYkh2U4oYbF/K3dyfQXLzh4lutyBlWpf2+oCrLgfRcW8pTvBUZ trZPl9whI9qEYEqvUOMff4b3K2+m8vefgVbCt20bcVrZ3skikFuMyPMjw9+9JACZ0ZW03xZ BnlCmCpAtzp4Au4Kc8qLZFcEG0hyqZN4GNNdej7PqVrjfleJ1pVaBkO6jpPqfFsPI2rOIbU ZAdaX5gqBdS5/MD8JI/7Vvm3Nzc4JN20b05ODesF5penlEL6VIUfS/goZ+ir8BqvCw6B0H2 U/5k6n1VrynaeOLVDIS0TkQjmsHf9P9vOHhs+2mheuAThHrkZooONWwqicCH3wieWPTsrtM vFEhorqXwBwkIJrDp02eo0EyITtmwv7L9hu6xMSTLh0UV0rVlfY+EZ8gkH5h5JyyOzQtLyS 1ccfepyfY7wdGTXSKii3qW1IjSzb9KjKfEFqco6ouXPDhN9idBYMIR0QtzQQmnCi58j+HIO 9I/mh/W90c1mFcJUsRMs4p5pcbDcSzF4sz4P8aNr/pSOClvYEDVDhlr0KPrYKwWMTshv3VE uZRv+S9A7DYkSGE+Nbd6WlupH8OBgv93DqDZEwTNr1Mlz3zhgVrc6qinLeGrKCh1uhYRJA0 BwHekUUcTLcBQLQGsmC6KOfEaial2AOns62Wh41yjdhbfVjGbYPtpJ35MUKhKhCJYfOX8qv fbAK+jJdHqNepkpG7B3K+yKxrW/GJb6GmQCo8BBz8Flv3nRV32CDn0AgHusrCAONPIoLvIa p2nGFBgopjT9ypvV9H+Nl9RTDQVcXfWF097TrxETiuZJfF65WtCzEl3MfDA51X0dEWXrq6o MTHJjlk/JZwSfpuBHENE95XQ9UTa6oYRQ== X-QQ-XMRINFO: NyFYKkN4Ny6FSmKK/uo/jdU= X-QQ-RECHKSPAM: 0 After performing a conditional bus reset, the controller must ensure that the SDA line is actually released. Previously, the reset routine only performed a single check, which could leave the bus in a locked state in some situations. This patch introduces a loop that toggles the reset cycle and issues a reset request up to SPACEMIT_BUS_RESET_CLK_CNT_MAX times, checking SDA after each attempt. If SDA is released before the maximum count, the function returns early. Otherwise, a warning is emitted. This change improves bus recovery reliability. Fixes: 5ea558473fa31 ("i2c: spacemit: add support for SpacemiT K1 SoC") Signed-off-by: Troy Mitchell --- drivers/i2c/busses/i2c-k1.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c index 4d78ee7b6929ee43771e500d4f85d9e55e68b221..d2c0d20d19ba73baa8b2e9a6acb= 02b2cc3b7243f 100644 --- a/drivers/i2c/busses/i2c-k1.c +++ b/drivers/i2c/busses/i2c-k1.c @@ -3,6 +3,7 @@ * Copyright (C) 2024-2025 Troy Mitchell */ =20 +#include #include #include #include @@ -26,7 +27,8 @@ #define SPACEMIT_CR_MODE_FAST BIT(8) /* bus mode (master operation) */ /* Bit 9 is reserved */ #define SPACEMIT_CR_UR BIT(10) /* unit reset */ -/* Bits 11-12 are reserved */ +#define SPACEMIT_CR_RSTREQ BIT(11) /* i2c bus reset request */ +/* Bit 12 is reserved */ #define SPACEMIT_CR_SCLE BIT(13) /* master clock enable */ #define SPACEMIT_CR_IUE BIT(14) /* unit enable */ /* Bits 15-17 are reserved */ @@ -78,6 +80,7 @@ SPACEMIT_SR_ALD) =20 #define SPACEMIT_RCR_SDA_GLITCH_NOFIX BIT(7) /* bypass the SDA glitch fi= x */ +#define SPACEMIT_RCR_FIELD_RST_CYC GENMASK(3, 0) /* bypass the SDA glitch= fix */ =20 /* SPACEMIT_IBMR register fields */ #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ @@ -91,6 +94,8 @@ =20 #define SPACEMIT_SR_ERR (SPACEMIT_SR_BED | SPACEMIT_SR_RXOV | SPACEMIT_SR_= ALD) =20 +#define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9 + enum spacemit_i2c_state { SPACEMIT_STATE_IDLE, SPACEMIT_STATE_START, @@ -163,6 +168,7 @@ static int spacemit_i2c_handle_err(struct spacemit_i2c_= dev *i2c) static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *= i2c) { u32 status; + u8 clk_cnt; =20 /* if bus is locked, reset unit. 0: locked */ status =3D readl(i2c->base + SPACEMIT_IBMR); @@ -172,6 +178,21 @@ static void spacemit_i2c_conditionally_reset_bus(struc= t spacemit_i2c_dev *i2c) spacemit_i2c_reset(i2c); usleep_range(10, 20); =20 + for (clk_cnt =3D 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) { + status =3D readl(i2c->base + SPACEMIT_IBMR); + if (status & SPACEMIT_BMR_SDA) + break; + + /* There's nothing left to save here, we are about to exit */ + writel(FIELD_PREP(SPACEMIT_RCR_FIELD_RST_CYC, 1), + i2c->base + SPACEMIT_IRCR); + writel(SPACEMIT_CR_RSTREQ, i2c->base + SPACEMIT_ICR); + usleep_range(20, 30); + } + + if (clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX) + return; + /* check sda again here */ status =3D readl(i2c->base + SPACEMIT_IBMR); if (!(status & SPACEMIT_BMR_SDA)) --=20 2.50.1