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Wed, 27 Aug 2025 15:39:25 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 2985033504381610877 EX-QQ-RecipientCnt: 9 From: Troy Mitchell Date: Wed, 27 Aug 2025 15:39:10 +0800 Subject: [PATCH 3/6] i2c: spacemit: disable SDA glitch fix to avoid restart delay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-k1-i2c-atomic-v1-3-e59bea02d680@linux.spacemit.com> References: <20250827-k1-i2c-atomic-v1-0-e59bea02d680@linux.spacemit.com> In-Reply-To: <20250827-k1-i2c-atomic-v1-0-e59bea02d680@linux.spacemit.com> To: Andi Shyti , Yixun Lan , Alex Elder , Troy Mitchell Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Troy Mitchell X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756280357; l=2255; i=troy.mitchell@linux.spacemit.com; s=20250710; h=from:subject:message-id; bh=XOadE6q3hu9FC4+hTj5B4E1CAH50HQ7DCsTZxRN6P5w=; b=Y9zQihml6SFgzLnNFvIYUCpA939k2Lzx7ML2GodAd0uKVXap/b6Ez47Q1y4B/U9tU8+wDNoK2 aTOGsgN494GCFus4VUCGlCjGEwRSQHzOsUm10u3OjlutLh+l17Xn7T4 X-Developer-Key: i=troy.mitchell@linux.spacemit.com; a=ed25519; pk=lQa7BzLrq8DfZnChqmwJ5qQk8fP2USmY/4xZ2/MSsXc= X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:linux.spacemit.com:qybglogicsvrsz:qybglogicsvrsz3a-0 X-QQ-XMAILINFO: OW4JKxETGMY2QhaCakBTCB0FjQaqcoMM1c7I9ZPm44zlRnzzVP87jDti VUKuVVXZVX0C6OGD2Ghkl+2xAZY+XuE/QUYxJRgXCEuqtM+RRv1/dzSND8Bk5O0LsyDIUdG iWpuzWj+/bhVKu5biftADdtHD8RMRflttEV+rfwuHf1cwrb9MHSWbD6/0bUyYkwXL/kpu9w RlnIb00jfsChiJt5+j3Q3rULDkFTIrNFqvDoO6msmDJ8ydUiP1kPKAqcpSxHW4Ng3hQMV7N /DauvBnxT2isMHGzXHddt4zGU7UaLgACaxUa2fmJSXlzKcy3LCw1KsdeDJxIm0oy1uicXLM E5/JRfZRGRvm8Ia1yrCkCm8nNfaMbS2DAHAQN2L+yMyeDEQ6BklgF/HkJh3SJVSPxJKPVqX sLItFZG78YHYSdy6jAt/675dBNyTP4UszOVpxPhXyODek5ALmDWXDRtRmQjpsP3f4WbMvcx uBBTk3agLCFae8DRvAGJ5BScmoUfJMaDw0BggxWs20VNc1/0ULsXzpLSxj8fxL+F3gN6O9L mjklHjZ1djI/jJfVW8rMzX3HmgBC3rZNofUapSbe6278zfBKg0iOK5tOl9iDt1cMcglZlO2 rKJnMXMhdD2f+wp/6gP2fgnGoGr8QbnUx36W/+lXOwCZgGBh+YRuz0Hkbs3dNx0+Dl/vp2i +/W3F5rc8Nh3MiIKZyjMJDMdyWG5J/9+bcH0ujqMovyL8kr08TArOHbLTNyTEgPSHRflMFR 0vqywq2pKX4ButIbKvDTV4xK8j4R04KWQK+XqgvvNSgkoGs7MHQRwJdL7nqQMozsLTQRGu5 Geh3c0XJZoutQ+V1XDpG8x/aSdPvms99AHlQ6wU89hig0o1mIxOwQaY3gQq0+F4HlJ9bsHK 0V+OAjNZh2Xw1zpodKlpr+L5+a31MWRxHnhV6XbRMv37REFoJfcnrJN4l1EbWd0y5bYrvgz TuFYwb1xpIAFKY8zWTGrHqY1RVTE4y3uCqV3n3V4eTqJYGLL1QpUbEo84FVQLt+1J2C1MV5 W1pxAM0EAQxvhWlPxjRVR/PU5BlvCuP15kMDou3w2f7rYW2xQwPAGh//AKyUZVxyumzJkLI uWbRcg4LrPZwNt5i13AjkaHLy166NB7Dg== X-QQ-XMRINFO: MSVp+SPm3vtS1Vd6Y4Mggwc= X-QQ-RECHKSPAM: 0 The K1 I2C controller has an SDA glitch fix that introduces a small delay on restart signals. While this feature can suppress glitches on SDA when SCL =3D 0, it also delays the restart signal, which may cause unexpected behavior in some transfers. The glitch itself does not affect normal I2C operation, because the I2C specification allows SDA to change while SCL is low. To ensure correct transmission for every message, we disable the SDA glitch fix by setting the RCR.SDA_GLITCH_NOFIX bit during initialization. This guarantees that restarts are issued promptly without unintended delays. Fixes: 5ea558473fa31 ("i2c: spacemit: add support for SpacemiT K1 SoC") Signed-off-by: Troy Mitchell Reviewed-by: Aurelien Jarno --- drivers/i2c/busses/i2c-k1.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c index d342752030d077953adf84a2886211de96e843c4..c1656b78f1681729ccc2ebca6e2= 90259d14889d9 100644 --- a/drivers/i2c/busses/i2c-k1.c +++ b/drivers/i2c/busses/i2c-k1.c @@ -14,6 +14,7 @@ #define SPACEMIT_ICR 0x0 /* Control register */ #define SPACEMIT_ISR 0x4 /* Status register */ #define SPACEMIT_IDBR 0xc /* Data buffer register */ +#define SPACEMIT_IRCR 0x18 /* Reset cycle counter */ #define SPACEMIT_IBMR 0x1c /* Bus monitor register */ =20 /* SPACEMIT_ICR register fields */ @@ -76,6 +77,8 @@ SPACEMIT_SR_GCAD | SPACEMIT_SR_IRF | SPACEMIT_SR_ITE | \ SPACEMIT_SR_ALD) =20 +#define SPACEMIT_RCR_SDA_GLITCH_NOFIX BIT(7) /* bypass the SDA glitch fi= x */ + /* SPACEMIT_IBMR register fields */ #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */ @@ -237,6 +240,14 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev = *i2c) val |=3D SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE; =20 writel(val, i2c->base + SPACEMIT_ICR); + + /* + * The glitch fix in the K1 I2C controller introduces a delay + * on restart signals, so we disable the fix here. + */ + val =3D readl(i2c->base + SPACEMIT_IRCR); + val |=3D SPACEMIT_RCR_SDA_GLITCH_NOFIX; + writel(val, i2c->base + SPACEMIT_IRCR); } =20 static inline void --=20 2.50.1