From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51970275105 for ; Wed, 27 Aug 2025 15:12:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756307568; cv=none; b=ru4irycREHmYmQ1J9kW7drbSWtxx8ZdQUPX2ND2IKsdrJeTF9Fhod25lxoQ2Azsp/xjcccNdc6HVS3iOPZ2ic6mQ96Vm3dLMFZMU+mYYb7ySKa9DtPksapJQDRQSaTIwzj6w5MLR6y92ldgdJBuMxPjlBNE0x5fEZJhAOjKc798= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756307568; c=relaxed/simple; bh=TOyEj6XtI89c72jvHNqBo0jjmqIBf/MzWhGVwim4FCA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YKaEHTTEaCqs4t3XyoWoJwfKZaam4w9iX28WLMm5hjE+i4X1Vh5S1NdtZ6J8cXzFJbkGCQt1mmiK9EsSILjro7K9nNeskJ6x7ZddOJAFe7DLLjaEvHTka4FgCKNE+ctjnSd1pkyTgW5V284AJ5mZYL+LZhaZSzorSOYieqWa6C4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SMbVdFR/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SMbVdFR/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 84361C4CEF0; Wed, 27 Aug 2025 15:12:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307566; bh=TOyEj6XtI89c72jvHNqBo0jjmqIBf/MzWhGVwim4FCA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SMbVdFR/6HYBUUiHSEEqS/ABonhocWVWP3tF4zIhH8zlV4KKPRkhcMgU793wICR0n gRA6s2/7p3bPgszUEchZWoyxS69jbSwBiTBCmaijbbKcMKF2PHtqYeNBEGYhlvkYfC tT43iHO2JCnTZJy+82eUxeIQFPxuK+oV9j4EvDH66GBcnePXYr0354oLdcNmODYHym Wlos7ZGrukh1K9qW39iXWnz9bmBjLx+ECZV1WcJ1dF8dPsR0116beDk6KTxWGl7gK6 gwi00NbMh/qb8NdNPU5g9Z/ZY+7GueiJYIbrnNwpthEPf6fSoGg2zDZsHaD/E2cHyc s8Z2O8IPSQ7Cg== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:32 +0200 Subject: [PATCH v3 01/14] drm/tidss: dispc: Remove unused OVR_REG_GET Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-1-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1128; i=mripard@kernel.org; h=from:subject:message-id; bh=TOyEj6XtI89c72jvHNqBo0jjmqIBf/MzWhGVwim4FCA=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFZLn7fRdlB5lHbnM2f8IQ617x7xkV+O7TMufXNk9I 3Guze+pHVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAifMGMDfu0bsmVec8VV0p7 ISvNYxNrdCmw8drCzXycRvdUxBZceFEhPHXLcrWcKYzPZ7TZareeYWx4m6699vSJC4o5G+Se2KR KuOrZTta9yrDDdqdV6vyGD2L5uU+3NmwPj4mySSyruRDeawAA X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The OVR_REG_GET function in the dispc driver is not used anywhere. Let's drop it. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 3f6cff2ab1b29b43638eb62d4ead36f7fe07486f..71031c3ad60e5a2c99a9a0981c8= 5d246a1a42dc6 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -651,17 +651,10 @@ static void VP_REG_FLD_MOD(struct dispc_device *dispc= , u32 vp, u32 idx, u32 val, { dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), val, start, end)); } =20 -__maybe_unused -static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx, - u32 start, u32 end) -{ - return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end); -} - static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, u32 val, u32 start, u32 end) { dispc_ovr_write(dispc, ovr, idx, FLD_MOD(dispc_ovr_read(dispc, ovr, idx), --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0861C276027 for ; Wed, 27 Aug 2025 15:12:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756307570; cv=none; b=iyBcqiMk5TdxBiTzKqCKh398g0q4KMZ8wU9BRT5NGfQtMu/2jqX7kBncLLjOm+Ne7rLF4woTq591w7yBTPvkO/7HhqZLWtLGWB6lxlsVwLDLGtjK9ZD2Z7rN9wcEdY+cawWZpeQYpFP1awgZxcMgSDUjcJsqSW+vciSjnxYcf5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756307570; c=relaxed/simple; bh=CScdAF88DJpHJzjNw1q6hQx+PlMuLPDsFTEZ17iufnQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LgVa1X9F1zQmuiAoWBkSBvuqa+lul0hvHfEMwiHy8uRmHl7R5ofBtMjfKaaaq1ws9UtmV5bCQWeSdWhmdGlCwhvjCA/x2U/fTTy8a1+drkkFMKEeFLOrz/tY4noLWEbejvNJJRhbEJTgjARS1ijEXwI5BMKFpQauYfIi7PXJasQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TEOrzaeR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TEOrzaeR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32F85C4CEEB; Wed, 27 Aug 2025 15:12:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307569; bh=CScdAF88DJpHJzjNw1q6hQx+PlMuLPDsFTEZ17iufnQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TEOrzaeRl5nxx4lQVWJmj2cB+JTvQ16ig6E0LRLeevFI1NjBu/PuHAIRE/Nv7qQ6E Z/j6HEbpBxCAL59fm1Z6Xf1RfsAvkyEZnvRfneIDGmJAHtZbYIJnuJeykBretXDGBL zEVYGx2G6ieITfdlITM4nf9nen9jaI7GPs1nRW3d0X+g5t+APn7FUKVaHyZobXoouA nEeqCXPM9++IaaXViR77xtn45RKU2b+Je1mxxlLzYWs2kjOtVVw51xa53A8GGIAxU/ HnorzV4pI43LxuJMH3W9F7mDrbbQEpb9R9RnY9uZYcXCvcT4RYdKmoM+NQPcZS6xNY vQR97GiGpUPRw== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:33 +0200 Subject: [PATCH v3 02/14] drm/tidss: dispc: Convert accessors to macros Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-2-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5528; i=mripard@kernel.org; h=from:subject:message-id; bh=CScdAF88DJpHJzjNw1q6hQx+PlMuLPDsFTEZ17iufnQ=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFZLT7q1gvy1SbNi0d6KIdfmD6C8X+eoMCl+cbtzqN UnERGxRx1QWBmFOBlkxRZYnMmGnl7cvrnKwX/kDZg4rE8gQBi5OAZhIyXXGhmUu/H57tm6eLX46 8KfqxI/fvD6/V6g+X7Blk2qycs+kFBeedcvO3+st2eDx0qt+7gcjdcaGN9xHFs/w0zrzyancSF+ g5mufWUfhk669k/SfxmVHJvuFWL06ldXxZv/3Rx9TvIQ7PrIDAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The dispc driver uses upper-cased, inlined, functions to provide macro-like accessors to the dispc registers. This is confusing, since upper-case is usually used by macros, and that pattern will create gcc errors later on in this series. Let's switch to macros to make it more consistent, and prevent those errors down the line. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 122 +++++++++++++++++++-------------= ---- 1 file changed, 66 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 71031c3ad60e5a2c99a9a0981c85d246a1a42dc6..6231e1aa07fdfa4ea1265b8239e= 561972dbba8f3 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -592,76 +592,86 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -static u32 FLD_MASK(u32 start, u32 end) -{ - return ((1 << (start - end + 1)) - 1) << end; -} +#define FLD_MASK(start, end) \ + ({ \ + int _end_inner =3D (end); \ + u32 _mask =3D ((1 << ((start) - _end_inner + 1)) - 1) << _end_inner; \ + _mask; \ + }) =20 -static u32 FLD_VAL(u32 val, u32 start, u32 end) -{ - return (val << end) & FLD_MASK(start, end); -} +#define FLD_VAL(val, start, end) \ + ({ \ + int _end_inner =3D (end); \ + u32 _new_val =3D ((val) << _end_inner) & FLD_MASK((start), _end_inner); \ + _new_val; \ + }) =20 -static u32 FLD_GET(u32 val, u32 start, u32 end) -{ - return (val & FLD_MASK(start, end)) >> end; -} +#define FLD_GET(val, start, end) \ + ({ \ + int _end =3D (end); \ + u32 _ret_val =3D ((val) & FLD_MASK((start), _end)) >> _end; \ + _ret_val; \ + }) =20 -static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) -{ - return (orig & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end); -} +#define FLD_MOD(orig, val, start, end) \ + ({ \ + int _start =3D (start), _end =3D (end); \ + u32 _masked_val =3D (orig) & ~FLD_MASK(_start, _end); \ + u32 _new_val =3D _masked_val | FLD_VAL((val), _start, _end); \ + _new_val; \ + }) =20 -static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) -{ - return FLD_GET(dispc_read(dispc, idx), start, end); -} +#define REG_GET(dispc, idx, start, end) \ + ((u32)FLD_GET(dispc_read((dispc), (idx)), (start), (end))) =20 -static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, - u32 start, u32 end) -{ - dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val, - start, end)); -} +#define REG_FLD_MOD(dispc, idx, val, start, end) \ + ({ \ + struct dispc_device *_dispc =3D (dispc); \ + u32 _idx =3D (idx); \ + u32 _curr =3D dispc_read(_dispc, _idx); \ + u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ + dispc_write(_dispc, _idx, _new); \ + }) =20 -static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, - u32 start, u32 end) -{ - return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); -} +#define VID_REG_GET(dispc, hw_plane, idx, start, end) \ + ((u32)FLD_GET(dispc_vid_read((dispc), (hw_plane), (idx)), (start), (end))) =20 -static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 = idx, - u32 val, u32 start, u32 end) -{ - dispc_vid_write(dispc, hw_plane, idx, - FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), - val, start, end)); -} +#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ + ({ \ + struct dispc_device *_dispc =3D (dispc); \ + u32 _hw_plane =3D (hw_plane); \ + u32 _idx =3D (idx); \ + u32 _curr =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ + u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ + dispc_vid_write(_dispc, _hw_plane, _idx, _new); \ + }) =20 -static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, - u32 start, u32 end) -{ - return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end); -} +#define VP_REG_GET(dispc, vp, idx, start, end) \ + ((u32)FLD_GET(dispc_vp_read((dispc), (vp), (idx)), (start), (end))) =20 -static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u3= 2 val, - u32 start, u32 end) -{ - dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), - val, start, end)); -} +#define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ + ({ \ + struct dispc_device *_dispc =3D (dispc); \ + u32 _vp =3D (vp); \ + u32 _idx =3D (idx); \ + u32 _curr =3D dispc_vp_read(_dispc, _vp, _idx); \ + u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ + dispc_vp_write(_dispc, _vp, _idx, _new); \ + }) =20 -static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, - u32 val, u32 start, u32 end) -{ - dispc_ovr_write(dispc, ovr, idx, - FLD_MOD(dispc_ovr_read(dispc, ovr, idx), - val, start, end)); -} +#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end) \ + ({ \ + struct dispc_device *_dispc =3D (dispc); \ + u32 _ovr =3D (ovr); \ + u32 _idx =3D (idx); \ + u32 _curr =3D dispc_ovr_read(_dispc, _ovr, _idx); \ + u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ + dispc_ovr_write(_dispc, _ovr, _idx, _new); \ + }) =20 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) { dispc_irq_t vp_stat =3D 0; =20 --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 878B227702E for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PZSgVF+U" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BF079C4CEF5; Wed, 27 Aug 2025 15:12:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307572; bh=EBPSGENkTcwztznrwhtBrxgFnzCYLtSKl6BkLZjU1c8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PZSgVF+UQTzFbvQD+OJCASw7ojVoJ//PgyIDpDpBxZ/qvsNZBXl+ZcfWLI9gPQorp QSoOP4VblCzR23UaNal0kPKVVTQozfHUNU+6ZqtX8XI9fTicZYzmbCFoQOWxVY/nRo 1ydumtnahPsSW+AZmvRh573YT65Qr1T3qxlxZcWV85ISUbstG3asgNRBXOTBso77x3 fNnNlNmuq+f70TEBMqbPgz+cCP9fCM4L2n9n4SjaYuiWsCereKyizbkkOZVmo5D2RE uDmeywUBe4UqUaNgdq1B37Y3M//o94eJ92y+H4ne14tBhiO6AkasX0js7NslT7t7FL XWIB87Js5sUDw== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:34 +0200 Subject: [PATCH v3 03/14] drm/tidss: dispc: Switch to GENMASK instead of FLD_MASK Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-3-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1844; i=mripard@kernel.org; h=from:subject:message-id; bh=EBPSGENkTcwztznrwhtBrxgFnzCYLtSKl6BkLZjU1c8=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFVK2nZJXucLJzBdZ+crutUyV9bZtiY7FTrx+JRMEr G+9Sd7ZMZWFQZiTQVZMkeWJTNjp5e2LqxzsV/6AmcPKBDKEgYtTACYSl8lYn2uSO2Xm19+b7ZeH b8h/veFaE6PrY5Uo9rsTbL4/38jJVVHPf6w5enrKoed2VTPut3YkMNZpV8WV18Y7m3YXMwi/f31 vidnx3vbZjcxsUkeb+qLU86VEpwQXT7+nm+ldOfv0sglhRQA= X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The dispc FLD_MASK function is an exact equivalent of the GENMASK macro. Let's convert the dispc driver to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 6231e1aa07fdfa4ea1265b8239e561972dbba8f3..b5f09ed2f3700068bc39bef3630= a86a33c16fabb 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -592,35 +592,28 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define FLD_MASK(start, end) \ - ({ \ - int _end_inner =3D (end); \ - u32 _mask =3D ((1 << ((start) - _end_inner + 1)) - 1) << _end_inner; \ - _mask; \ - }) - #define FLD_VAL(val, start, end) \ ({ \ int _end_inner =3D (end); \ - u32 _new_val =3D ((val) << _end_inner) & FLD_MASK((start), _end_inner); \ + u32 _new_val =3D ((val) << _end_inner) & GENMASK((start), _end_inner); \ _new_val; \ }) =20 #define FLD_GET(val, start, end) \ ({ \ int _end =3D (end); \ - u32 _ret_val =3D ((val) & FLD_MASK((start), _end)) >> _end; \ + u32 _ret_val =3D ((val) & GENMASK((start), _end)) >> _end; \ _ret_val; \ }) =20 #define FLD_MOD(orig, val, start, end) \ ({ \ int _start =3D (start), _end =3D (end); \ - u32 _masked_val =3D (orig) & ~FLD_MASK(_start, _end); \ + u32 _masked_val =3D (orig) & ~GENMASK(_start, _end); \ u32 _new_val =3D _masked_val | FLD_VAL((val), _start, _end); \ _new_val; \ }) =20 #define REG_GET(dispc, idx, start, end) \ --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17EE1277C86 for ; Wed, 27 Aug 2025 15:12:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756307575; cv=none; b=Rt1REsPV7LWHItU29n0Jbo9JLdHQEZoyIxxm/nT6zxY4fWOA2MLT62wRUsAQ4xcxp8PfYSqBIGGirY/ZnIW6Aa+uJnXWeykEAKXLsAs5elBE100gEH4olIq8YBb5CeXz5YqjzisFx70OPa2tp7ZnuuGECMW3kh5/tRKPcnpTwV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756307575; c=relaxed/simple; bh=PmbbEdF9MF1vSaRgtsiUedCNxEGcP/e30F1iYuqyXv8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N94+kzWvQfeFx/GkAjRkJrtBbyn/KQDRSXMJfuQBfkVm41jxf9a+0nZJsBdDMgi4K6K5epUL+g+MiYM7r8WkTh/ypItFqBFjUWzsWwROTJ7wGvgw9bVMdFFQWJsA1A8UqlyP8P3kLfBW1nECWi8qAkqpg67bVc3TM7FMvWI4KBc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Hq5J2Gu3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Hq5J2Gu3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6CD34C4CEF0; Wed, 27 Aug 2025 15:12:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307574; bh=PmbbEdF9MF1vSaRgtsiUedCNxEGcP/e30F1iYuqyXv8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Hq5J2Gu3bpHyvLTZZ/Lb3v1JUPN+kKFi+gGpg7/IPRx+f+Rol42KtUquzoJA6YzJp IVYrFTwvX0GE5XILExMSOObRQchWi32w+m71/iQvhhAGCK5T85a/2nAyAQh90D5EiA nERSAkKDHCaX9bKoMupY0HQtgyXgC03KgbUp2Ei9hMN6YE+Z01apmUKt0O2rit0O7Q SAmDp1EOJrIDWlw8ka/e2pGm5Wsw8fkcdIKjHq6CzHGcxCAtrmq5hnPmki+/F+yRBG PlZg6hYMJ48flbwoeL/PtJi8/43JVyaGoJPCLg4VbxhaovQM4dDw7yWY3XtEFZEhT3 q0FiP6dQ/q1Mw== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:35 +0200 Subject: [PATCH v3 04/14] drm/tidss: dispc: Get rid of FLD_VAL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-4-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7298; i=mripard@kernel.org; h=from:subject:message-id; bh=PmbbEdF9MF1vSaRgtsiUedCNxEGcP/e30F1iYuqyXv8=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFVLqtM5/tz2zv9G1+2W9b//+H1LyTHs+e86aL3Pe7 Mw6kU7ljqksDMKcDLJiiixPZMJOL29fXOVgv/IHzBxWJpAhDFycAjCRsNuM9XH/dM+VyW25fatO rE3I99el+Mw3d5dIzzZi1yitV1suY/bN+syK7Y938QR+MOhcd396PWPDBc3vuxn0ircfDd3Zol9 t7Va299U//wmPQiP4U2ZvZFjXabXgb0nK2yzrNo5pu9c2xDEBAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_VAL function is an equivalent to what FIELD_PREP + GENMASK provide, so let's drop it and switch to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 58 +++++++++++++++++----------------= ---- 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index b5f09ed2f3700068bc39bef3630a86a33c16fabb..43f8078a1effa2b5a09532cb069= 131dc0cbf3c10 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -592,17 +592,10 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define FLD_VAL(val, start, end) \ - ({ \ - int _end_inner =3D (end); \ - u32 _new_val =3D ((val) << _end_inner) & GENMASK((start), _end_inner); \ - _new_val; \ - }) - #define FLD_GET(val, start, end) \ ({ \ int _end =3D (end); \ u32 _ret_val =3D ((val) & GENMASK((start), _end)) >> _end; \ _ret_val; \ @@ -610,11 +603,11 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) =20 #define FLD_MOD(orig, val, start, end) \ ({ \ int _start =3D (start), _end =3D (end); \ u32 _masked_val =3D (orig) & ~GENMASK(_start, _end); \ - u32 _new_val =3D _masked_val | FLD_VAL((val), _start, _end); \ + u32 _new_val =3D _masked_val | FIELD_PREP(GENMASK(_start, _end), (val));= \ _new_val; \ }) =20 #define REG_GET(dispc, idx, start, end) \ ((u32)FLD_GET(dispc_read((dispc), (idx)), (start), (end))) @@ -1218,18 +1211,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, vfp =3D mode->crtc_vsync_start - mode->crtc_vdisplay; vsw =3D mode->crtc_vsync_end - mode->crtc_vsync_start; vbp =3D mode->crtc_vtotal - mode->crtc_vsync_end; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, - FLD_VAL(hsw - 1, 7, 0) | - FLD_VAL(hfp - 1, 19, 8) | - FLD_VAL(hbp - 1, 31, 20)); + FIELD_PREP(GENMASK(7, 0), hsw - 1) | + FIELD_PREP(GENMASK(19, 8), hfp - 1) | + FIELD_PREP(GENMASK(31, 20), hbp - 1)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, - FLD_VAL(vsw - 1, 7, 0) | - FLD_VAL(vfp, 19, 8) | - FLD_VAL(vbp, 31, 20)); + FIELD_PREP(GENMASK(7, 0), vsw - 1) | + FIELD_PREP(GENMASK(19, 8), vfp) | + FIELD_PREP(GENMASK(31, 20), vbp)); =20 ivs =3D !!(mode->flags & DRM_MODE_FLAG_NVSYNC); =20 ihs =3D !!(mode->flags & DRM_MODE_FLAG_NHSYNC); =20 @@ -1248,21 +1241,21 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, /* always use DE_HIGH for OLDI */ if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) ieo =3D false; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, - FLD_VAL(align, 18, 18) | - FLD_VAL(onoff, 17, 17) | - FLD_VAL(rf, 16, 16) | - FLD_VAL(ieo, 15, 15) | - FLD_VAL(ipc, 14, 14) | - FLD_VAL(ihs, 13, 13) | - FLD_VAL(ivs, 12, 12)); + FIELD_PREP(GENMASK(18, 18), align) | + FIELD_PREP(GENMASK(17, 17), onoff) | + FIELD_PREP(GENMASK(16, 16), rf) | + FIELD_PREP(GENMASK(15, 15), ieo) | + FIELD_PREP(GENMASK(14, 14), ipc) | + FIELD_PREP(GENMASK(13, 13), ihs) | + FIELD_PREP(GENMASK(12, 12), ivs)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, - FLD_VAL(mode->crtc_hdisplay - 1, 11, 0) | - FLD_VAL(mode->crtc_vdisplay - 1, 27, 16)); + FIELD_PREP(GENMASK(11, 0), mode->crtc_hdisplay - 1) | + FIELD_PREP(GENMASK(27, 16), mode->crtc_vdisplay - 1)); =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) @@ -1574,18 +1567,18 @@ struct dispc_csc_coef { #define DISPC_CSC_REGVAL_LEN 8 =20 static void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval) { -#define OVAL(x, y) (FLD_VAL(x, 15, 3) | FLD_VAL(y, 31, 19)) +#define OVAL(x, y) (FIELD_PREP(GENMASK(15, 3), x) | FIELD_PREP(GENMASK(31,= 19), y)) regval[5] =3D OVAL(csc->preoffset[0], csc->preoffset[1]); regval[6] =3D OVAL(csc->preoffset[2], csc->postoffset[0]); regval[7] =3D OVAL(csc->postoffset[1], csc->postoffset[2]); #undef OVAL } =20 -#define CVAL(x, y) (FLD_VAL(x, 10, 0) | FLD_VAL(y, 26, 16)) +#define CVAL(x, y) (FIELD_PREP(GENMASK(10, 0), x) | FIELD_PREP(GENMASK(26,= 16), y)) static void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regva= l) { regval[0] =3D CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); regval[1] =3D CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); @@ -1820,11 +1813,12 @@ static void dispc_vid_write_fir_coefs(struct dispc_= device *dispc, s16 c1, c2; u32 c12; =20 c1 =3D coefs->c1[phase]; c2 =3D coefs->c2[phase]; - c12 =3D FLD_VAL(c1, 19, 10) | FLD_VAL(c2, 29, 20); + c12 =3D FIELD_PREP(GENMASK(19, 10), c1) | FIELD_PREP(GENMASK(29, 20), + c2); =20 dispc_vid_write(dispc, hw_plane, reg, c12); } } =20 @@ -2318,18 +2312,18 @@ static u32 dispc_vid_get_fifo_size(struct dispc_dev= ice *dispc, u32 hw_plane) =20 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, - FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); + FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); } =20 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, - FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); + FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); } =20 static void dispc_k2g_plane_init(struct dispc_device *dispc) { unsigned int hw_plane; @@ -2466,12 +2460,12 @@ static void dispc_initial_config(struct dispc_devic= e *dispc) dispc_vp_init(dispc); =20 /* Note: Hardcoded DPI routing on J721E for now */ if (dispc->feat->subrev =3D=3D DISPC_J721E) { dispc_write(dispc, DISPC_CONNECTIONS, - FLD_VAL(2, 3, 0) | /* VP1 to DPI0 */ - FLD_VAL(8, 7, 4) /* VP3 to DPI1 */ + FIELD_PREP(GENMASK(3, 0), 2) | /* VP1 to DPI0 */ + FIELD_PREP(GENMASK(7, 4), 8) /* VP3 to DPI1 */ ); } } =20 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, @@ -2645,12 +2639,12 @@ static void dispc_k2g_cpr_from_ctm(const struct drm= _color_ctm *ctm, cpr->m[CSC_BR] =3D dispc_S31_32_to_s2_8(ctm->matrix[6]); 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Wed, 27 Aug 2025 15:12:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307577; bh=uP7VrIhR0S0n6XikKxh4fvAsgSssIZys68koJDMOXK0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AyzWDH9c/dRaqFbFLLopAVhe7M6mQrp2SGvgz/5JzPE0+vvjRkRROMTbrp5ap2uxf YIIj15YknVvmT0eWEc/Y5S/zaoih7xoQLWvnynl4OcUNj/r6NUjwrwVMzIdu6rJcWZ coUXJOkl14tIuPjVct6nw5iiD4w2dZVoKC5S60YaAuM0/R8apIxwgSMFBV6/nVK2uu B5hdKyuYUlL8w1e6vNf/i9j1VprDoAEwLOVFizJYARiOfVKr0m+abOL/djtrDOQBCR bHXcmGimLer6y0ZgdHVg82+n4CM/RvqILyJJxdtSq6OVF+Jk+ePbHpQtfAGXmrjZjY 5R0unXV5aRH2w== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:36 +0200 Subject: [PATCH v3 05/14] drm/tidss: dispc: Get rid of FLD_GET Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-5-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2757; i=mripard@kernel.org; h=from:subject:message-id; bh=uP7VrIhR0S0n6XikKxh4fvAsgSssIZys68koJDMOXK0=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFVIjzv06nt9vkfTTd+HDJgftjlff5k90F41u2LSa7 +Xv688udExlYRDmZJAVU2R5IhN2enn74ioH+5U/YOawMoEMYeDiFICJsF9lrJXqKDB0v3fR7cfW G9ra7e/vfbSad/7IEV3GkC+H/s00WvJ23pOapYb1fAa+BfUBBS1bKhgbul9kbD1oJPO6o8Je/9o httesJxVW6tS0KdsubNec+2TPX4ZVvzkcL/buZG/5mTjpzbWVAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_GET function is an equivalent to what FIELD_GET + GENMASK provide, so let's drop it and switch to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 43f8078a1effa2b5a09532cb069131dc0cbf3c10..b4ba342ac241a603db447d6c5ae= 147c981013be2 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -592,27 +592,21 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define FLD_GET(val, start, end) \ - ({ \ - int _end =3D (end); \ - u32 _ret_val =3D ((val) & GENMASK((start), _end)) >> _end; \ - _ret_val; \ - }) - #define FLD_MOD(orig, val, start, end) \ ({ \ int _start =3D (start), _end =3D (end); \ u32 _masked_val =3D (orig) & ~GENMASK(_start, _end); \ u32 _new_val =3D _masked_val | FIELD_PREP(GENMASK(_start, _end), (val));= \ _new_val; \ }) =20 #define REG_GET(dispc, idx, start, end) \ - ((u32)FLD_GET(dispc_read((dispc), (idx)), (start), (end))) + ((u32)FIELD_GET(GENMASK((start), (end)), \ + dispc_read((dispc), (idx)))) =20 #define REG_FLD_MOD(dispc, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _idx =3D (idx); \ @@ -620,11 +614,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ dispc_write(_dispc, _idx, _new); \ }) =20 #define VID_REG_GET(dispc, hw_plane, idx, start, end) \ - ((u32)FLD_GET(dispc_vid_read((dispc), (hw_plane), (idx)), (start), (end))) + ((u32)FIELD_GET(GENMASK((start), (end)), \ + dispc_vid_read((dispc), (hw_plane), (idx)))) =20 #define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _hw_plane =3D (hw_plane); \ @@ -633,11 +628,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ dispc_vid_write(_dispc, _hw_plane, _idx, _new); \ }) =20 #define VP_REG_GET(dispc, vp, idx, start, end) \ - ((u32)FLD_GET(dispc_vp_read((dispc), (vp), (idx)), (start), (end))) + ((u32)FIELD_GET(GENMASK((start), (end)), \ + dispc_vp_read((dispc), (vp), (idx)))) =20 #define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _vp =3D (vp); \ --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D63B279DDF for ; Wed, 27 Aug 2025 15:13:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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Wed, 27 Aug 2025 15:12:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307580; bh=IUaQn0XWbrijEey97sd6Zt/C2swsiVJ+8FwifczVmyc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=IBrC+iO48o0B97niiVfx3anc481X5q9Emv+H0K3yJbR5sKy9RHTw43bC+ggt+YotB lAHNjMVqqa0gojDQhMpdvEMzLR5mktj7kUyolz7tfsKDEtNUervHlpHG1lxUAaieI6 ZukwmB6o0MiX99AnzdWyQGD6eXR+kNPVIcYMVNTAhrblgHqpnGHpohP25nfK8NMW6s fXpAfJvLmGlTNQLX143tSs4PwhB8fgZB27JcAAU8e9fEgTeftPZB/mFXvEuW9948pj x9DjjAh4DIR0IKdSkZHwFawG3cVIDW00edvkpiAZ4o87uD/cMRfHxNzL5ij/aliJjh VuqhhS3oJVVAw== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:37 +0200 Subject: [PATCH v3 06/14] drm/tidss: dispc: Get rid of FLD_MOD Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-6-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4304; i=mripard@kernel.org; h=from:subject:message-id; bh=IUaQn0XWbrijEey97sd6Zt/C2swsiVJ+8FwifczVmyc=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFVIPuOyUSz+w4dKl+LJCo7c5O3YG3uXb9n7ewg65+ LZJTAk9HVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAiJ2sZG1b3qbZtl/NTP/NU 59DXwG0H+GK5uRXUFlitX5hmW/Rtt5DaU2GpPb8D5znIcvn3WL9dz1ifkPnjcd3JBkcHjvrHV0T i1J9Y33/aeeH5HGmlNf/u1bUWJkW+8TdzlFmze+3+9xblb0oA X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_MOD function is an equivalent to what FIELD_MODIFY + GENMASK provide, so let's drop it and switch to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 36 ++++++++++++++-------------------= --- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index b4ba342ac241a603db447d6c5ae147c981013be2..4eeeae6e0a0ecc8bb5bbc5f455e= 9fab6b913097a 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -592,29 +592,21 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define FLD_MOD(orig, val, start, end) \ - ({ \ - int _start =3D (start), _end =3D (end); \ - u32 _masked_val =3D (orig) & ~GENMASK(_start, _end); \ - u32 _new_val =3D _masked_val | FIELD_PREP(GENMASK(_start, _end), (val));= \ - _new_val; \ - }) - #define REG_GET(dispc, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ dispc_read((dispc), (idx)))) =20 #define REG_FLD_MOD(dispc, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _idx =3D (idx); \ - u32 _curr =3D dispc_read(_dispc, _idx); \ - u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ - dispc_write(_dispc, _idx, _new); \ + u32 _reg =3D dispc_read(_dispc, _idx); \ + FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + dispc_write(_dispc, _idx, _reg); \ }) =20 #define VID_REG_GET(dispc, hw_plane, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ dispc_vid_read((dispc), (hw_plane), (idx)))) @@ -622,13 +614,13 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) #define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _hw_plane =3D (hw_plane); \ u32 _idx =3D (idx); \ - u32 _curr =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ - u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ - dispc_vid_write(_dispc, _hw_plane, _idx, _new); \ + u32 _reg =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ + FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + dispc_vid_write(_dispc, _hw_plane, _idx, _reg); \ }) =20 #define VP_REG_GET(dispc, vp, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ dispc_vp_read((dispc), (vp), (idx)))) @@ -636,23 +628,23 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) #define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _vp =3D (vp); \ u32 _idx =3D (idx); \ - u32 _curr =3D dispc_vp_read(_dispc, _vp, _idx); \ - u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ - dispc_vp_write(_dispc, _vp, _idx, _new); \ + u32 _reg =3D dispc_vp_read(_dispc, _vp, _idx); \ + FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + dispc_vp_write(_dispc, _vp, _idx, _reg); \ }) =20 #define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ - u32 _ovr =3D (ovr); \ + u32 _ovr =3D (ovr); \ u32 _idx =3D (idx); \ - u32 _curr =3D dispc_ovr_read(_dispc, _ovr, _idx); \ - u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ - dispc_ovr_write(_dispc, _ovr, _idx, _new); \ + u32 _reg =3D dispc_ovr_read(_dispc, _ovr, _idx); \ + FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + dispc_ovr_write(_dispc, _ovr, _idx, _reg); \ }) =20 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) { dispc_irq_t vp_stat =3D 0; @@ -1145,11 +1137,11 @@ static void dispc_enable_am65x_oldi(struct dispc_de= vice *dispc, u32 hw_videoport dev_warn(dispc->dev, "%s: %d port width not supported\n", __func__, fmt->data_width); =20 oldi_cfg |=3D BIT(7); /* DEPOL */ =20 - oldi_cfg =3D FLD_MOD(oldi_cfg, fmt->am65x_oldi_mode_reg_val, 3, 1); + FIELD_MODIFY(GENMASK(3, 1), &oldi_cfg, fmt->am65x_oldi_mode_reg_val); =20 oldi_cfg |=3D BIT(12); /* SOFTRST */ =20 oldi_cfg |=3D BIT(0); /* ENABLE */ =20 --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0971527B32F for ; Wed, 27 Aug 2025 15:13:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756307583; cv=none; b=F8LtbLHZDO/r3ceavfUbhIHjQIskDH8fRpUJehyqCxupfUVQ9+E+P5qntjEJkGh/luYDnHiJsnyl7RkQJo6csG6Z5ULneKr0I+vyvzPsh37NLctDrAICKdMhTorMlXf4bWxZkBVhEmSR3P2JRfEjll6BSfJZQ9lRwmOO6aO2JPQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756307583; c=relaxed/simple; bh=ZbI27RylcyMGj+s7T7zJmmbfZNuvnXtkNAubQV1O/80=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IR7GgoC8AjC8V5NEZwgeOdGG8Ir3wDzocMN9hlT+tNRVeHWg9S7pqsi//dz0gpgzimU8i9yH8tnCp3nH+559iaY5srPDRP3+mmeqHnJMhKag8dTULIr5z8QznCz397EI8w2MwpuBvtHOv6g529L7ZXPWvMp9Xi2Oqn3sNmaRdG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=W7iZDn1q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="W7iZDn1q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 50512C4CEF0; Wed, 27 Aug 2025 15:13:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307582; bh=ZbI27RylcyMGj+s7T7zJmmbfZNuvnXtkNAubQV1O/80=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=W7iZDn1qymdPZrY75n9JZjKKu/mpClOMOjfEHpFcAYrjtAOpnFU2bqrXZnLZ7O5kC kakPvexQvAARuuyUF4LUlFgQ3KXvIaAzUXX3RFe4jp7bsrMXzQqOkup2LLGujqZj8W tZzOKqM+510F38N+klZuH3UGQKklZIHD8L16I9WpxjkCfoFzc/brr2bbJCGiPHFmz+ V9F6NUfgZHMyk+/8vYp3Q3EUWNdcdcX6O0J91D4Ok6nqkAKOfOC2mKgasf0BrnfAAx kKm9QRekIN50aUyfsNcVXlvDq9aA4HCIUS6/wKaBIGCJubIxAnb7WcFY3v/ZrAb/JK vAsHN5kjDOzdA== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:38 +0200 Subject: [PATCH v3 07/14] drm/tidss: dispc: Switch REG_GET to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-7-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2796; i=mripard@kernel.org; h=from:subject:message-id; bh=ZbI27RylcyMGj+s7T7zJmmbfZNuvnXtkNAubQV1O/80=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFdJWpiukixxoSfzV8Ob8zzje2IrTG3V1n1l0p0qfP P3hqEZ0x1QWBmFOBlkxRZYnMmGnl7cvrnKwX/kDZg4rE8gQBi5OAZjI22zGhiP98WulyxjOGZat FlherOlSVuT9bn17ZOXyFV80gs+8rQw//Mbi0PSM1/E/rV+2ddmmMtaZWi4vPX3nPmvIfbbgJ0f +NZpu11tpoXlfj8mXcZrw4uMrcufwsFequM49pMpQU1/27CMA X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The REG_GET function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change REG_GET to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 4eeeae6e0a0ecc8bb5bbc5f455e9fab6b913097a..48985f0bbbacacf76293f244144= 70664c74c40ec 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -592,13 +592,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define REG_GET(dispc, idx, start, end) \ - ((u32)FIELD_GET(GENMASK((start), (end)), \ - dispc_read((dispc), (idx)))) +#define REG_GET(dispc, idx, mask) \ + ((u32)FIELD_GET((mask), dispc_read((dispc), (idx)))) =20 #define REG_FLD_MOD(dispc, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _idx =3D (idx); \ @@ -2792,30 +2791,30 @@ int dispc_runtime_resume(struct dispc_device *dispc) { dev_dbg(dispc->dev, "resume\n"); =20 clk_prepare_enable(dispc->fclk); =20 - if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) =3D=3D 0) + if (REG_GET(dispc, DSS_SYSSTATUS, GENMASK(0, 0)) =3D=3D 0) dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); =20 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", dispc_read(dispc, DSS_REVISION)); =20 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", - REG_GET(dispc, DSS_SYSSTATUS, 1, 1), - REG_GET(dispc, DSS_SYSSTATUS, 2, 2), - REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(1, 1)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(2, 2)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(3, 3))); =20 if (dispc->feat->subrev =3D=3D DISPC_AM625 || dispc->feat->subrev =3D=3D DISPC_AM65X) dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", - REG_GET(dispc, DSS_SYSSTATUS, 5, 5), - REG_GET(dispc, DSS_SYSSTATUS, 6, 6), - REG_GET(dispc, DSS_SYSSTATUS, 7, 7)); + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(5, 5)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(6, 6)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(7, 7))); =20 dev_dbg(dispc->dev, "DISPC IDLE %d\n", - REG_GET(dispc, DSS_SYSSTATUS, 9, 9)); + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(9, 9))); =20 dispc_initial_config(dispc); =20 dispc->is_enabled =3D true; =20 --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66E3D27D786 for ; Wed, 27 Aug 2025 15:13:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 27 Aug 2025 15:13:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307585; bh=k6TwiI8He8GNSiGlGO+CMw9G5rhFmltlagnJGvSCcUw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gNTsOlglXMeUUV2UbTVaB1a6wDp6C6CaEHdsOCguHmKF8UUQfNfMrD0aAGuoyfHvR MFBCtujgsPC3K1NIhpP+yrBAVPB5gQ+fzIbEfME//eg2ypaVh9Lqa4J8Q36M7HC6pF i12ub26z7b6bZ3lnDKyctcSDnwQwbWAaNwVVWHeh1Dvw4Z8SYpg4SpARYPS+fgMwm1 CeKYjpbTiudQtKYcR2FNwkRE7o6HL6iBRipg4ZNtkpAX42JoFODmdVi94/RZC9qWIG yWFyw03Z4IC/zQ5i1gIosgBEc6wwRsDaL141gwjDNmjly35EaEIkRkzLOxSllocanG TGGwmO1qwTtJg== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:39 +0200 Subject: [PATCH v3 08/14] drm/tidss: dispc: Switch REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-8-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3642; i=mripard@kernel.org; h=from:subject:message-id; bh=k6TwiI8He8GNSiGlGO+CMw9G5rhFmltlagnJGvSCcUw=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFdL+Hg13kVz5NLBM7kBwc2/WwgnCVXeu6yerSxQ5i uWyJ0V3TGVhEOZkkBVTZHkiE3Z6efviKgf7lT9g5rAygQxh4OIUgIk8C2KslXC6WBDLoFWiGhpc xmdltnR6iXyWs76KklnRw7nLqwru7+dquvWiLdjN/H9IdPPpjRGMDaeZNGMnLnk3RbY8IueGU9Z RG27fgFucpXJXvjwpsdx76c2Xx4V3+p/e+ZvjmjjDdZ7THQA= X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 48985f0bbbacacf76293f24414470664c74c40ec..82b038285acc245f86573a6a854= da37248c92407 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -595,16 +595,16 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) */ =20 #define REG_GET(dispc, idx, mask) \ ((u32)FIELD_GET((mask), dispc_read((dispc), (idx)))) =20 -#define REG_FLD_MOD(dispc, idx, val, start, end) \ +#define REG_FLD_MOD(dispc, idx, val, mask) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _idx =3D (idx); \ u32 _reg =3D dispc_read(_dispc, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_write(_dispc, _idx, _reg); \ }) =20 #define VID_REG_GET(dispc, hw_plane, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ @@ -2316,13 +2316,13 @@ static void dispc_k2g_plane_init(struct dispc_devic= e *dispc) unsigned int hw_plane; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2367,17 +2367,17 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) u32 cba_lo_pri =3D 1; u32 cba_hi_pri =3D 0; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0); - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, GENMASK(2, 0)); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, GENMASK(5, 3)); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2901,11 +2901,11 @@ static int dispc_softreset(struct dispc_device *dis= pc) dispc_softreset_k2g(dispc); return 0; } =20 /* Soft reset */ - REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); + REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, GENMASK(1, 1)); /* Wait for reset to complete */ ret =3D readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, val, val & 1, 100, 5000); if (ret) { dev_err(dispc->dev, "failed to reset dispc\n"); --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75A6427FD6B for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nxo6kY9s" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5BC9C4CEEB; Wed, 27 Aug 2025 15:13:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307588; bh=YR/gYRTUbGVsPcXt+qNXfBhGUDKi5WInCy3Qs5bL5Cw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nxo6kY9scmEYDx7Cu2pXPuIwgx4qmT1gxiMlpW4N7VpoD9nS3cCKl0bRXjd/DhrJv LRGY0t7zDLssSZwYJczQv0M/LtIv0wQ4MHqolc6aajhI5HVyoUs5jehn59otX0lXah 0/PUWD+XOwAsFiOgpC5u7H5p0HDqkVLEC+Jb2iYlTxLDdZ2pZCF4GvSUFlGglxlblW 2dYlEH0ZVdrOMoTNVdbdFs7OP7Ma55iuHX0U6Bi5hMI3Vwokt1pXPytwdFtpaNS7WA +fYMzqAWFPw4wFgGpGfVlk2/EVsjdqvTra1PsxZKtsGRqvBkLfqvTTogHMXe30VReA AiKTULFxtXAeA== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:40 +0200 Subject: [PATCH v3 09/14] drm/tidss: dispc: Switch VID_REG_GET to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-9-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2081; i=mripard@kernel.org; h=from:subject:message-id; bh=YR/gYRTUbGVsPcXt+qNXfBhGUDKi5WInCy3Qs5bL5Cw=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFdLal9a6+K4JSHEpu7znRGjRrAnNi3cx2bVZzpzJv jlCbB1vx1QWBmFOBlkxRZYnMmGnl7cvrnKwX/kDZg4rE8gQBi5OAZhI2HbGhtUrF8+tadSt4kos uLTHdluCxq7ZZzwNbxodnmep+lyz2kt5w/y9LAfvegvdP3Wq8qvnb8aGZY9Mrs4zlmyI4fn7co/ 8IZvg/oJ1HBafZb9MY/m37p+R5LO7invv7QthZP25fcLtd9UlAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VID_REG_GET function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VID_REG_GET to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 82b038285acc245f86573a6a854da37248c92407..8e2c8ecb9f18c71cb532f1f5cea= 2bc00a0262ad3 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -604,13 +604,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) u32 _reg =3D dispc_read(_dispc, _idx); \ FIELD_MODIFY((mask), &_reg, (val)); \ dispc_write(_dispc, _idx, _reg); \ }) =20 -#define VID_REG_GET(dispc, hw_plane, idx, start, end) \ - ((u32)FIELD_GET(GENMASK((start), (end)), \ - dispc_vid_read((dispc), (hw_plane), (idx)))) +#define VID_REG_GET(dispc, hw_plane, idx, mask) \ + ((u32)FIELD_GET((mask), dispc_vid_read((dispc), (hw_plane), (idx)))) =20 #define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _hw_plane =3D (hw_plane); \ @@ -2292,11 +2291,12 @@ void dispc_plane_enable(struct dispc_device *dispc,= u32 hw_plane, bool enable) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); } =20 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plan= e) { - return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0); + return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, + GENMASK(15, 0)); } =20 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6F6528151E for ; Wed, 27 Aug 2025 15:13:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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Wed, 27 Aug 2025 15:13:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307590; bh=6hD6UxbBlKoYZyHeGn3CyW4PVYW/AoySrOUl6AiF3ic=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qUX6FfabGEBcUa5pVk9bIbE+C1DAS80F5Ep4T1uddeVXIfu9Q3hhlKnlLyymWC6S7 SvVaMgVAnVdUsXSl/pb1XvbT5KzqWq5BLgq8xEV8OCZh+sPD/G5vRW9kQIasc1EQXR NhEbNe+dklyvGK2f5dZODbctkxRpQidX5/zhp8Rz9JvzmfNewyS+MyLMGee/9jVtw0 jbr8M3jWGnLQr3Hyk0XMTQysegNtUTUw3bCwS2fQVYM5AbgAduoEIUuo/CWJTVJDdR eWkCFc7Cu2qjdXVS4lh1kDAzJt84yivd4llvd4TfYG5yF3mpJZxXZ638jQaemA8Z4X 5cvF/skwADHjA== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:41 +0200 Subject: [PATCH v3 10/14] drm/tidss: dispc: Switch VID_REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-10-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5234; i=mripard@kernel.org; h=from:subject:message-id; bh=6hD6UxbBlKoYZyHeGn3CyW4PVYW/AoySrOUl6AiF3ic=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFdLn3xS4WjR9mpaZ2gq5rJ5qkxdbQvycsz18/LR+T p6x8cGvjqksDMKcDLJiiixPZMJOL29fXOVgv/IHzBxWJpAhDFycAjCRFk7Ghnlc81xPbn3CqbRo 29V5jTsDg9u4feZN3S03rWzNwcIdffV9XwsrYvq5k76x5r9K2fM5hbHhMW9Og6qR6jTH43tfCwW yzHn+X/jHhfkW2T07Eq9PfbpZYqrWfGGltg21Z1bnNvE9nWcCAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VID_REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VID_REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 8e2c8ecb9f18c71cb532f1f5cea2bc00a0262ad3..27ac57d770327707c3b6d8bc97a= 683e4d770cffa 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,17 +607,17 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) }) =20 #define VID_REG_GET(dispc, hw_plane, idx, mask) \ ((u32)FIELD_GET((mask), dispc_vid_read((dispc), (hw_plane), (idx)))) =20 -#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ +#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, mask) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _hw_plane =3D (hw_plane); \ u32 _idx =3D (idx); \ u32 _reg =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vid_write(_dispc, _hw_plane, _idx, _reg); \ }) =20 #define VP_REG_GET(dispc, vp, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ @@ -1740,11 +1740,12 @@ static void dispc_vid_csc_setup(struct dispc_device= *dispc, u32 hw_plane, } =20 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, + GENMASK(9, 9)); } =20 /* SCALER */ =20 static u32 dispc_calc_fir_inc(u32 in, u32 out) @@ -1997,24 +1998,24 @@ static void dispc_vid_set_scaling(struct dispc_devi= ce *dispc, u32 hw_plane, struct dispc_scaling_params *sp, u32 fourcc) { /* HORIZONTAL RESIZE ENABLE */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->scale_x, 7, 7); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_x, + GENMASK(7, 7)); =20 /* VERTICAL RESIZE ENABLE */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->scale_y, 8, 8); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_y, + GENMASK(8, 8)); =20 /* Skip the rest if no scaling is used */ if (!sp->scale_x && !sp->scale_y) return; =20 /* VERTICAL 5-TAPS */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->five_taps, 21, 21); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->five_taps, + GENMASK(21, 21)); =20 if (dispc_fourcc_is_yuv(fourcc)) { if (sp->scale_x) { dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, sp->fir_xinc_uv); @@ -2100,11 +2101,11 @@ static void dispc_plane_set_pixel_format(struct dis= pc_device *dispc, =20 for (i =3D 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { if (dispc_color_formats[i].fourcc =3D=3D fourcc) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, dispc_color_formats[i].dss_code, - 6, 1); + GENMASK(6, 1)); return; } } =20 WARN_ON(1); @@ -2278,19 +2279,20 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, 0xFF & (state->alpha >> 8)); =20 if (state->pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - 28, 28); + GENMASK(28, 28)); else VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - 28, 28); + GENMASK(28, 28)); } =20 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool ena= ble) { - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, + GENMASK(0, 0)); } =20 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plan= e) { return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, @@ -2355,11 +2357,11 @@ static void dispc_k2g_plane_init(struct dispc_devic= e *dispc) * Prefetch up to fifo high-threshold value to minimize the * possibility of underflows. Note that this means the PRELOAD * register is ignored. */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - 19, 19); + GENMASK(19, 19)); } } =20 static void dispc_k3_plane_init(struct dispc_device *dispc) { @@ -2406,11 +2408,11 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); =20 /* Prefech up to PRELOAD value */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - 19, 19); + GENMASK(19, 19)); } } =20 static void dispc_plane_init(struct dispc_device *dispc) { --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19C5D286D57 for ; Wed, 27 Aug 2025 15:13:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756307594; cv=none; b=J6Jtw5ObCz5W08XyMThQ4l6lBA9FhCiSPsX768hco72ui+gDJeslvVJVATR/K9KT6VrO6RclrixIxpkk83tDVt0mrk2o9w1wdaFnMeaiERQwvRNChMXyvYYMRVhhuJ95qx30gSB8ZbB8LacJIIWY7UA+STKCXvUCYGeqbt2jFjs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756307594; c=relaxed/simple; bh=zmr6H3d9cs36J4DJWS1L0PwW2+Xx6ax3N3qSLvVbT3A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CPWzOjlVIBYpf/gpV3SD7GUdSMEga9JIB9OoLw0MCyIB58vwSLjxoSFH9qEQcCUoFFGewbmrt2AHVADVycoSa9LKCE7EDw9q5kIKiFMusr6KlhToD4VKQdd2KS8HijfCUOehoKtJdBxbK2f/r6yLm2bv5Yf7i9ghT1SUSdH8V5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=f37GYhCa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="f37GYhCa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1FDAEC4CEF5; Wed, 27 Aug 2025 15:13:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307593; bh=zmr6H3d9cs36J4DJWS1L0PwW2+Xx6ax3N3qSLvVbT3A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=f37GYhCaS57OGblrKqt06t9tRcL3esyi9WsrrXc3dVZxBy00JzW0v5ekLMVAmvtwt gHdIC5vStrKzbqzmHYwXSGtZIp/EtNmmwoA7VabEz3E5fWehkT91PUuOviAvxoATrl lpX4Pv2Hk8t9+j4sluh3tFJqNQcv3SFNL6YUxDBCko/M6fbseJMISqZTrm4BUxYMBy 7ZVg/GTNPlLWp5vVRnJ4UwYjKggU2/JRKIjNmnF9QqwuM6CHGXkKMzwPgydgF21M41 tkVpHtW8l2Xax633iBBOhYvp3o6QX0i+C6AXo42LK78ehr+rGWzgj3wgeE5c3JKS/R KtlDCTJaTBa5w== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:42 +0200 Subject: [PATCH v3 11/14] drm/tidss: dispc: Switch VP_REG_GET to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-11-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2215; i=mripard@kernel.org; h=from:subject:message-id; bh=zmr6H3d9cs36J4DJWS1L0PwW2+Xx6ax3N3qSLvVbT3A=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFdJ3J/pX8qgw3pTsmpm9f+G8t7xnQnV9goP3RjKpz Ez4seRCx1QWBmFOBlkxRZYnMmGnl7cvrnKwX/kDZg4rE8gQBi5OAZjIQXvGhvbIX4dvL/6+U/mi tHEKa4Pv7iC7ngKPrhsb9nw6ezxqxh63uI+Pcr/s+fnRddWpSL6w44wNu6frfpd1eTUzQGh+61q xpuTgiw4Gb1Sfn9Kqf2XK9rKktLUw9WrDu50G93//eD7117F/AA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VP_REG_GET function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VP_REG_GET to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 27ac57d770327707c3b6d8bc97a683e4d770cffa..3d807b129c09f1b78016e9d04fa= 501ed745e5aad 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -617,13 +617,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) u32 _reg =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vid_write(_dispc, _hw_plane, _idx, _reg); \ }) =20 -#define VP_REG_GET(dispc, vp, idx, start, end) \ - ((u32)FIELD_GET(GENMASK((start), (end)), \ - dispc_vp_read((dispc), (vp), (idx)))) +#define VP_REG_GET(dispc, vp, idx, mask) \ + ((u32)FIELD_GET((mask), dispc_vp_read((dispc), (vp), (idx)))) =20 #define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _vp =3D (vp); \ @@ -1258,16 +1257,17 @@ void dispc_vp_unprepare(struct dispc_device *dispc,= u32 hw_videoport) } } =20 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) { - return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5); + return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, + GENMASK(5, 5)); } =20 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { - WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5)); + WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5))); VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); } =20 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; =20 --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D749A2882A7 for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oZI9kyiE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1A295C4CEEB; Wed, 27 Aug 2025 15:13:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307596; bh=Vr81QLsdJfPxTAirR9ZzowAMIpD+4tSxhNs79iOJJeA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oZI9kyiE6QH7Yyac7a+J2tcZ6J4Igc3iNxgSvggozjDxgDJBPTT8qGC3SqBnsbEm/ VEx4bC+b6J8T41vh4qptJQsJ3d7E3Cw7/jTK6GSFO1JV4f1XMMi8C4e+RM56WJg5KS ZgIIw2oS4+MANr+zsRl5pkLGVH8xkJJvtZcU7oN0B598J0m+NpdhzMft45qKDtqR0P 19i3JcXexJYdBc0h9SUIspon8rpPdcJ+sPQXZClmA5yN0efKIoZFrBRZ26cxTzaFp1 JP0gUvDZmGtD2YoVW84y9trufzS/Io47lKnuwvFCO0CQcUFHJ6pGA28OG8PpFOWeAu xReXKd5mWL46A== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:43 +0200 Subject: [PATCH v3 12/14] drm/tidss: dispc: Switch VP_REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-12-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5453; i=mripard@kernel.org; h=from:subject:message-id; bh=Vr81QLsdJfPxTAirR9ZzowAMIpD+4tSxhNs79iOJJeA=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFTJOm9dLNBq5TNg4+dAiU460C11PNJy8jcufzJC1m p9/RHVbx1QWBmFOBlkxRZYnMmGnl7cvrnKwX/kDZg4rE8gQBi5OAZjIGV7GavbcuTnWG50nyt5s PhLe3bzWsUNDWPKym/A6R/mS9g9efRvVuSuqzkwP+OQYkOT00MSTsT5w2rvMVUt2HDzS4zT/DF/ 19Tl/5+Vd3yIjk2gQZn3yyoJlBwsU9p5d4yerwmaqual1thEA X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VP_REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VP_REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 3d807b129c09f1b78016e9d04fa501ed745e5aad..0255f7156f46008c8fee2b37f14= 31957f1c71cad 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -620,17 +620,17 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) }) =20 #define VP_REG_GET(dispc, vp, idx, mask) \ ((u32)FIELD_GET((mask), dispc_vp_read((dispc), (vp), (idx)))) =20 -#define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ +#define VP_REG_FLD_MOD(dispc, vp, idx, val, mask) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _vp =3D (vp); \ u32 _idx =3D (idx); \ u32 _reg =3D dispc_vp_read(_dispc, _vp, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vp_write(_dispc, _vp, _idx, _reg); \ }) =20 #define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end) \ ({ \ @@ -1111,11 +1111,12 @@ static void dispc_set_num_datalines(struct dispc_de= vice *dispc, default: WARN_ON(1); v =3D 3; } =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, + GENMASK(10, 8)); } =20 static void dispc_enable_am65x_oldi(struct dispc_device *dispc, u32 hw_vid= eoport, const struct dispc_bus_format *fmt) { @@ -1238,16 +1239,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, FIELD_PREP(GENMASK(11, 0), mode->crtc_hdisplay - 1) | FIELD_PREP(GENMASK(27, 16), mode->crtc_vdisplay - 1)); =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, + GENMASK(0, 0)); } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) { - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, + GENMASK(0, 0)); } =20 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) { if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) { @@ -1264,11 +1267,12 @@ bool dispc_vp_go_busy(struct dispc_device *dispc, u= 32 hw_videoport) } =20 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5))); - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, + GENMASK(5, 5)); } =20 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; =20 static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) @@ -2438,11 +2442,11 @@ static void dispc_vp_init(struct dispc_device *disp= c) =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* Enable the gamma Shadow bit-field for all VPs*/ for (i =3D 0; i < dispc->feat->num_vps; i++) - VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2); + VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, GENMASK(2, 2)); } =20 static void dispc_initial_config(struct dispc_device *dispc) { dispc_plane_init(dispc); @@ -2671,12 +2675,12 @@ static void dispc_k2g_vp_set_ctm(struct dispc_devic= e *dispc, u32 hw_videoport, dispc_k2g_cpr_from_ctm(ctm, &cpr); dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); cprenable =3D 1; } =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, - cprenable, 15, 15); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, cprenable, + GENMASK(15, 15)); } =20 static s16 dispc_S31_32_to_s3_8(s64 coef) { u64 sign_bit =3D 1ULL << 63; @@ -2737,12 +2741,12 @@ static void dispc_k3_vp_set_ctm(struct dispc_device= *dispc, u32 hw_videoport, dispc_csc_from_ctm(ctm, &csc); dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); colorconvenable =3D 1; } =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, - colorconvenable, 24, 24); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, colorconvenable, + GENMASK(24, 24)); } =20 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state, @@ -2889,11 +2893,12 @@ static void dispc_softreset_k2g(struct dispc_device= *dispc) dispc_set_irqenable(dispc, 0); dispc_read_and_clear_irqstatus(dispc); spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags); =20 for (unsigned int vp_idx =3D 0; vp_idx < dispc->feat->num_vps; ++vp_idx) - VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0); + VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, + GENMASK(0, 0)); } =20 static int dispc_softreset(struct dispc_device *dispc) { u32 val; --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FC6128BABB for ; Wed, 27 Aug 2025 15:13:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 27 Aug 2025 15:13:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307599; bh=YJRlhFRqu1x2YPL2NtIVXHirsUuDmkG2DmqfkWYi4Dg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NBY4YzI87uTE6W8uppAYTMaIWCjAoBLQZVyYXnkg0K7oHjUlwNw+zKDDg+ySfpbA6 8QymGYlaoQmI8YeRZzZEfx53ME4MTqlR5k4dVCiLNmvm0LB4SW2eoL4rBh5/rfyU+Z 61a4QAJk7Ek+CU2Ujk08C2E5tRnzkcsaBRRHyYYyEQMiD4SQfEaBt2rMUQPQYrwpLk Br2+NCdCB97gP/YXogBsWE54sHhTmj4d+IyUozn7ZJAaoToy/bxwzVEGhu9/fZhXvN 4pGME9OnYUcgZnUrZ7K4+Xjt5XwGuOWL9v7loH8gXogH+j1GmWENNo++0LdBvzKnGK G7id0a27s7tMA== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:44 +0200 Subject: [PATCH v3 13/14] drm/tidss: dispc: Switch OVR_REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-13-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3457; i=mripard@kernel.org; h=from:subject:message-id; bh=YJRlhFRqu1x2YPL2NtIVXHirsUuDmkG2DmqfkWYi4Dg=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFTKsJ/7+xnw+/17GCqausDrRHR/YZdRc7ywxOSPXN TONS9isYyoLgzAng6yYIssTmbDTy9sXVznYr/wBM4eVCWQIAxenAExkahVjnQmD+N7ruzLPVbwt 36rR81rRPMJGXdFv7dPTJ56d7Fu5rlsx5MNf919/bnGteL79+oGkQsZa6dS9F8x2eAQlbnwxq2H LPyXmrcyzEw4z/pOq9ZuZ9ODIZiuG9Yv+m7geCz3GKH2HfcMdAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The OVR_REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change OVR_REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 0255f7156f46008c8fee2b37f1431957f1c71cad..9ecbea60d37cf981c8ce00f075f= 19f925cce44be 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -630,17 +630,17 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) u32 _reg =3D dispc_vp_read(_dispc, _vp, _idx); \ FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vp_write(_dispc, _vp, _idx, _reg); \ }) =20 -#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end) \ +#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, mask) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _ovr =3D (ovr); \ u32 _idx =3D (idx); \ u32 _reg =3D dispc_ovr_read(_dispc, _ovr, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_ovr_write(_dispc, _ovr, _idx, _reg); \ }) =20 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) { @@ -1468,29 +1468,29 @@ static void dispc_am65x_ovr_set_plane(struct dispc_= device *dispc, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, 4, 1); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - x, 17, 6); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - y, 30, 19); + hw_id, GENMASK(4, 1)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x, + GENMASK(17, 6)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), y, + GENMASK(30, 19)); } =20 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, 4, 1); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), - x, 13, 0); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), - y, 29, 16); + hw_id, GENMASK(4, 1)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), x, + GENMASK(13, 0)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), y, + GENMASK(29, 16)); } =20 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { @@ -1521,11 +1521,11 @@ void dispc_ovr_enable_layer(struct dispc_device *di= spc, { if (dispc->feat->subrev =3D=3D DISPC_K2G) return; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - !!enable, 0, 0); + !!enable, GENMASK(0, 0)); } =20 /* CSC */ enum csc_ctm { CSC_RR, CSC_RG, CSC_RB, --=20 2.50.1 From nobody Fri Oct 3 16:46:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E21E276027 for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MSPdAfpA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 89081C4CEF5; Wed, 27 Aug 2025 15:13:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756307602; bh=tWsxGVcKib0fDaqq91LOvavfQcyKFv9WvHc0m6iqCjE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MSPdAfpA0B7jrV3ompE5nBjGJRykUUdfgTIxjZth+odWmE+phyecL7T/ZYDQEVjA2 VTn1ZIlxRSP0XIHkiwYgwfNhPr4ZKGVOX3RRW5yT7d83XlGaUr2lCnpMRUv+k5A+Cn PkJxmKlkDN9t1Wgo3PMpLkpQwym2xYI64UxsTibjxUlE7ndEG4DU/ggUE1reHtboKt f5OMRn1pLxIu5ec969IHciWCgSufYaibp+4Uo8dZSpxrkGmdG7WQa23h3Dprx42/d1 GmkYEm2HM0hFlC9FSyLQpqYDSyN6d+O1abUljdHMgO+QdSJRvY1FSwe/8XGVi0ZoHs ZilbMl5nGQMng== From: Maxime Ripard Date: Wed, 27 Aug 2025 17:12:45 +0200 Subject: [PATCH v3 14/14] drm/tidss: dispc: Define field masks being used Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-drm-tidss-field-api-v3-14-7689b664cc63@kernel.org> References: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> In-Reply-To: <20250827-drm-tidss-field-api-v3-0-7689b664cc63@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=27100; i=mripard@kernel.org; h=from:subject:message-id; bh=tWsxGVcKib0fDaqq91LOvavfQcyKFv9WvHc0m6iqCjE=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBnrFTI1wx8tbQ7QeLDqu2CZZP2vQMYZu9Rqix0237qYI fnJ62xNx1QWBmFOBlkxRZYnMmGnl7cvrnKwX/kDZg4rE8gQBi5OAZhIsQdjnaaZwiyxh3cW/Gs8 PtP6qevvRfmaCv+0z95vSdkw+0A/2/7P4RG/GHs3ZgWExXl8CO5OYmyY2dNwX1/u5J6ry3wnKjT OUi01WvC93m3ZI4OtZ9wkOhpCRG+ZyMWsfjr9wqMPBzw5XQwB X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D Now that we have all the accessors taking masks, we can create defines for them and reuse them as needed. It makes the driver easier to read, less prone to consistency issues, and allows to reuse defines when needed. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 139 +++++++++++++++++----------= ---- drivers/gpu/drm/tidss/tidss_dispc_regs.h | 76 +++++++++++++++++ 2 files changed, 154 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 9ecbea60d37cf981c8ce00f075f19f925cce44be..97e2cd7b1e209ed9181a8a5e7d7= 0f03a2470ba1c 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1112,11 +1112,11 @@ static void dispc_set_num_datalines(struct dispc_de= vice *dispc, WARN_ON(1); v =3D 3; } =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, - GENMASK(10, 8)); + DISPC_VP_CONTROL_DATALINES_MASK); } =20 static void dispc_enable_am65x_oldi(struct dispc_device *dispc, u32 hw_vid= eoport, const struct dispc_bus_format *fmt) { @@ -1135,11 +1135,12 @@ static void dispc_enable_am65x_oldi(struct dispc_de= vice *dispc, u32 hw_videoport dev_warn(dispc->dev, "%s: %d port width not supported\n", __func__, fmt->data_width); =20 oldi_cfg |=3D BIT(7); /* DEPOL */ =20 - FIELD_MODIFY(GENMASK(3, 1), &oldi_cfg, fmt->am65x_oldi_mode_reg_val); + FIELD_MODIFY(DISPC_VP_DSS_OLDI_CFG_MAP_MASK, &oldi_cfg, + fmt->am65x_oldi_mode_reg_val); =20 oldi_cfg |=3D BIT(12); /* SOFTRST */ =20 oldi_cfg |=3D BIT(0); /* ENABLE */ =20 @@ -1197,18 +1198,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, vfp =3D mode->crtc_vsync_start - mode->crtc_vdisplay; vsw =3D mode->crtc_vsync_end - mode->crtc_vsync_start; vbp =3D mode->crtc_vtotal - mode->crtc_vsync_end; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, - FIELD_PREP(GENMASK(7, 0), hsw - 1) | - FIELD_PREP(GENMASK(19, 8), hfp - 1) | - FIELD_PREP(GENMASK(31, 20), hbp - 1)); + FIELD_PREP(DISPC_VP_TIMING_H_SYNC_PULSE_MASK, hsw - 1) | + FIELD_PREP(DISPC_VP_TIMING_H_FRONT_PORCH_MASK, hfp - 1) | + FIELD_PREP(DISPC_VP_TIMING_H_BACK_PORCH_MASK, hbp - 1)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, - FIELD_PREP(GENMASK(7, 0), vsw - 1) | - FIELD_PREP(GENMASK(19, 8), vfp) | - FIELD_PREP(GENMASK(31, 20), vbp)); + FIELD_PREP(DISPC_VP_TIMING_V_SYNC_PULSE_MASK, vsw - 1) | + FIELD_PREP(DISPC_VP_TIMING_V_FRONT_PORCH_MASK, vfp) | + FIELD_PREP(DISPC_VP_TIMING_V_BACK_PORCH_MASK, vbp)); =20 ivs =3D !!(mode->flags & DRM_MODE_FLAG_NVSYNC); =20 ihs =3D !!(mode->flags & DRM_MODE_FLAG_NHSYNC); =20 @@ -1227,30 +1228,32 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, /* always use DE_HIGH for OLDI */ if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) ieo =3D false; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, - FIELD_PREP(GENMASK(18, 18), align) | - FIELD_PREP(GENMASK(17, 17), onoff) | - FIELD_PREP(GENMASK(16, 16), rf) | - FIELD_PREP(GENMASK(15, 15), ieo) | - FIELD_PREP(GENMASK(14, 14), ipc) | - FIELD_PREP(GENMASK(13, 13), ihs) | - FIELD_PREP(GENMASK(12, 12), ivs)); + FIELD_PREP(DISPC_VP_POL_FREQ_ALIGN_MASK, align) | + FIELD_PREP(DISPC_VP_POL_FREQ_ONOFF_MASK, onoff) | + FIELD_PREP(DISPC_VP_POL_FREQ_RF_MASK, rf) | + FIELD_PREP(DISPC_VP_POL_FREQ_IEO_MASK, ieo) | + FIELD_PREP(DISPC_VP_POL_FREQ_IPC_MASK, ipc) | + FIELD_PREP(DISPC_VP_POL_FREQ_IHS_MASK, ihs) | + FIELD_PREP(DISPC_VP_POL_FREQ_IVS_MASK, ivs)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, - FIELD_PREP(GENMASK(11, 0), mode->crtc_hdisplay - 1) | - FIELD_PREP(GENMASK(27, 16), mode->crtc_vdisplay - 1)); + FIELD_PREP(DISPC_VP_SIZE_SCREEN_HDISPLAY_MASK, + mode->crtc_hdisplay - 1) | + FIELD_PREP(DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK, + mode->crtc_vdisplay - 1)); =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, - GENMASK(0, 0)); + DISPC_VP_CONTROL_ENABLE_MASK); } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) { VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, - GENMASK(0, 0)); + DISPC_VP_CONTROL_ENABLE_MASK); } =20 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) { if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) { @@ -1261,18 +1264,19 @@ void dispc_vp_unprepare(struct dispc_device *dispc,= u32 hw_videoport) } =20 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) { return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, - GENMASK(5, 5)); + DISPC_VP_CONTROL_GOBIT_MASK); } =20 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { - WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5))); + WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, + DISPC_VP_CONTROL_GOBIT_MASK)); VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, - GENMASK(5, 5)); + DISPC_VP_CONTROL_GOBIT_MASK); } =20 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; =20 static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) @@ -1468,29 +1472,29 @@ static void dispc_am65x_ovr_set_plane(struct dispc_= device *dispc, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, GENMASK(4, 1)); + hw_id, DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x, - GENMASK(17, 6)); + DISPC_OVR_ATTRIBUTES_POSX_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), y, - GENMASK(30, 19)); + DISPC_OVR_ATTRIBUTES_POSY_MASK); } =20 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, GENMASK(4, 1)); + hw_id, DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), x, - GENMASK(13, 0)); + DISPC_OVR_ATTRIBUTES2_POSX_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), y, - GENMASK(29, 16)); + DISPC_OVR_ATTRIBUTES2_POSY_MASK); } =20 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { @@ -1521,11 +1525,11 @@ void dispc_ovr_enable_layer(struct dispc_device *di= spc, { if (dispc->feat->subrev =3D=3D DISPC_K2G) return; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - !!enable, GENMASK(0, 0)); + !!enable, DISPC_OVR_ATTRIBUTES_ENABLE_MASK); } =20 /* CSC */ enum csc_ctm { CSC_RR, CSC_RG, CSC_RB, @@ -1745,11 +1749,11 @@ static void dispc_vid_csc_setup(struct dispc_device= *dispc, u32 hw_plane, =20 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, - GENMASK(9, 9)); + DISPC_VID_ATTRIBUTES_COLORCONVENABLE_MASK); } =20 /* SCALER */ =20 static u32 dispc_calc_fir_inc(u32 in, u32 out) @@ -2003,23 +2007,23 @@ static void dispc_vid_set_scaling(struct dispc_devi= ce *dispc, struct dispc_scaling_params *sp, u32 fourcc) { /* HORIZONTAL RESIZE ENABLE */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_x, - GENMASK(7, 7)); + DISPC_VID_ATTRIBUTES_HRESIZEENABLE_MASK); =20 /* VERTICAL RESIZE ENABLE */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_y, - GENMASK(8, 8)); + DISPC_VID_ATTRIBUTES_VRESIZEENABLE_MASK); =20 /* Skip the rest if no scaling is used */ if (!sp->scale_x && !sp->scale_y) return; =20 /* VERTICAL 5-TAPS */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->five_taps, - GENMASK(21, 21)); + DISPC_VID_ATTRIBUTES_VERTICALTAPS_MASK); =20 if (dispc_fourcc_is_yuv(fourcc)) { if (sp->scale_x) { dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, sp->fir_xinc_uv); @@ -2105,11 +2109,11 @@ static void dispc_plane_set_pixel_format(struct dis= pc_device *dispc, =20 for (i =3D 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { if (dispc_color_formats[i].fourcc =3D=3D fourcc) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, dispc_color_formats[i].dss_code, - GENMASK(6, 1)); + DISPC_VID_ATTRIBUTES_FORMAT_MASK); return; } } =20 WARN_ON(1); @@ -2227,11 +2231,12 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32); dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff); dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32); =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE, - (scale.in_w - 1) | ((scale.in_h - 1) << 16)); + FIELD_PREP(DISPC_VID_PICTURE_SIZE_MEMSIZEY_MASK, scale.in_h - 1) | + FIELD_PREP(DISPC_VID_PICTURE_SIZE_MEMSIZEX_MASK, scale.in_w - 1)); =20 /* For YUV422 format we use the macropixel size for pixel inc */ if (fourcc =3D=3D DRM_FORMAT_YUYV || fourcc =3D=3D DRM_FORMAT_UYVY) dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, pixinc(scale.xinc, cpp * 2)); @@ -2264,12 +2269,14 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, cpp_uv)); } =20 if (!lite) { dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE, - (state->crtc_w - 1) | - ((state->crtc_h - 1) << 16)); + FIELD_PREP(DISPC_VID_SIZE_SIZEY_MASK, + state->crtc_h - 1) | + FIELD_PREP(DISPC_VID_SIZE_SIZEX_MASK, + state->crtc_w - 1)); =20 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc); } =20 /* enable YUV->RGB color conversion */ @@ -2279,56 +2286,63 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, } else { dispc_vid_csc_enable(dispc, hw_plane, false); } =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, - 0xFF & (state->alpha >> 8)); + FIELD_PREP(DISPC_VID_GLOBAL_ALPHA_GLOBALALPHA_MASK, + state->alpha >> 8)); =20 if (state->pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - GENMASK(28, 28)); + DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK); else VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - GENMASK(28, 28)); + DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK); } =20 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool ena= ble) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, - GENMASK(0, 0)); + DISPC_VID_ATTRIBUTES_ENABLE_MASK); } =20 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plan= e) { return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, - GENMASK(15, 0)); + DISPC_VID_BUF_SIZE_STATUS_BUFSIZE_MASK); } =20 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, - FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); + FIELD_PREP(DISPC_VID_MFLAG_THRESHOLD_HT_MFLAG_MASK, high) | + FIELD_PREP(DISPC_VID_MFLAG_THRESHOLD_LT_MFLAG_MASK, low)); } =20 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, - FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); + FIELD_PREP(DISPC_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK, + high) | + FIELD_PREP(DISPC_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK, + low)); } =20 static void dispc_k2g_plane_init(struct dispc_device *dispc) { unsigned int hw_plane; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2361,11 +2375,11 @@ static void dispc_k2g_plane_init(struct dispc_devic= e *dispc) * Prefetch up to fifo high-threshold value to minimize the * possibility of underflows. Note that this means the PRELOAD * register is ignored. */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - GENMASK(19, 19)); + DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK); } } =20 static void dispc_k3_plane_init(struct dispc_device *dispc) { @@ -2373,17 +2387,19 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) u32 cba_lo_pri =3D 1; u32 cba_hi_pri =3D 0; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, GENMASK(2, 0)); - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, GENMASK(5, 3)); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, DSS_CBA_CFG_PRI_LO_MASK); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, DSS_CBA_CFG_PRI_HI_MASK); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2412,11 +2428,11 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); =20 /* Prefech up to PRELOAD value */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - GENMASK(19, 19)); + DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK); } } =20 static void dispc_plane_init(struct dispc_device *dispc) { @@ -2442,23 +2458,24 @@ static void dispc_vp_init(struct dispc_device *disp= c) =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* Enable the gamma Shadow bit-field for all VPs*/ for (i =3D 0; i < dispc->feat->num_vps; i++) - VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, GENMASK(2, 2)); + VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, + DISPC_VP_CONFIG_GAMMAENABLE_MASK); } =20 static void dispc_initial_config(struct dispc_device *dispc) { dispc_plane_init(dispc); dispc_vp_init(dispc); =20 /* Note: Hardcoded DPI routing on J721E for now */ if (dispc->feat->subrev =3D=3D DISPC_J721E) { dispc_write(dispc, DISPC_CONNECTIONS, - FIELD_PREP(GENMASK(3, 0), 2) | /* VP1 to DPI0 */ - FIELD_PREP(GENMASK(7, 4), 8) /* VP3 to DPI1 */ + FIELD_PREP(DISPC_CONNECTIONS_DPI_0_CONN_MASK, 2) | /* VP1 to DPI0 = */ + FIELD_PREP(DISPC_CONNECTIONS_DPI_1_CONN_MASK, 8) /* VP3 to DPI1 */ ); } } =20 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, @@ -2676,11 +2693,11 @@ static void dispc_k2g_vp_set_ctm(struct dispc_devic= e *dispc, u32 hw_videoport, dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); cprenable =3D 1; } =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, cprenable, - GENMASK(15, 15)); + DISPC_VP_CONFIG_CPR_MASK); } =20 static s16 dispc_S31_32_to_s3_8(s64 coef) { u64 sign_bit =3D 1ULL << 63; @@ -2742,11 +2759,11 @@ static void dispc_k3_vp_set_ctm(struct dispc_device= *dispc, u32 hw_videoport, dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); colorconvenable =3D 1; } =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, colorconvenable, - GENMASK(24, 24)); + DISPC_VP_CONFIG_COLORCONVENABLE_MASK); } =20 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state, @@ -2797,11 +2814,11 @@ int dispc_runtime_resume(struct dispc_device *dispc) { dev_dbg(dispc->dev, "resume\n"); =20 clk_prepare_enable(dispc->fclk); =20 - if (REG_GET(dispc, DSS_SYSSTATUS, GENMASK(0, 0)) =3D=3D 0) + if (REG_GET(dispc, DSS_SYSSTATUS, DSS_SYSSTATUS_DISPC_FUNC_RESETDONE) =3D= =3D 0) dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); =20 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", dispc_read(dispc, DSS_REVISION)); =20 @@ -2816,11 +2833,11 @@ int dispc_runtime_resume(struct dispc_device *dispc) REG_GET(dispc, DSS_SYSSTATUS, GENMASK(5, 5)), REG_GET(dispc, DSS_SYSSTATUS, GENMASK(6, 6)), REG_GET(dispc, DSS_SYSSTATUS, GENMASK(7, 7))); =20 dev_dbg(dispc->dev, "DISPC IDLE %d\n", - REG_GET(dispc, DSS_SYSSTATUS, GENMASK(9, 9))); + REG_GET(dispc, DSS_SYSSTATUS, DSS_SYSSTATUS_DISPC_IDLE_STATUS)); =20 dispc_initial_config(dispc); =20 dispc->is_enabled =3D true; =20 @@ -2894,11 +2911,11 @@ static void dispc_softreset_k2g(struct dispc_device= *dispc) dispc_read_and_clear_irqstatus(dispc); spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags); =20 for (unsigned int vp_idx =3D 0; vp_idx < dispc->feat->num_vps; ++vp_idx) VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, - GENMASK(0, 0)); + DISPC_VP_CONTROL_ENABLE_MASK); } =20 static int dispc_softreset(struct dispc_device *dispc) { u32 val; @@ -2908,11 +2925,11 @@ static int dispc_softreset(struct dispc_device *dis= pc) dispc_softreset_k2g(dispc); return 0; } =20 /* Soft reset */ - REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, GENMASK(1, 1)); + REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, DSS_SYSCONFIG_SOFTRESET_MASK); /* Wait for reset to complete */ ret =3D readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, val, val & 1, 100, 5000); if (ret) { dev_err(dispc->dev, "failed to reset dispc\n"); diff --git a/drivers/gpu/drm/tidss/tidss_dispc_regs.h b/drivers/gpu/drm/tid= ss/tidss_dispc_regs.h index 50a3f28250efe61f1d98a456bf8907000109411c..382027dddce894b3b7d11172e23= bf11883e25958 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc_regs.h +++ b/drivers/gpu/drm/tidss/tidss_dispc_regs.h @@ -54,11 +54,16 @@ enum dispc_common_regs { =20 #define REG(r) (dispc_common_regmap[r ## _OFF]) =20 #define DSS_REVISION REG(DSS_REVISION) #define DSS_SYSCONFIG REG(DSS_SYSCONFIG) +#define DSS_SYSCONFIG_SOFTRESET_MASK GENMASK(1, 1) + #define DSS_SYSSTATUS REG(DSS_SYSSTATUS) +#define DSS_SYSSTATUS_DISPC_IDLE_STATUS GENMASK(9, 9) +#define DSS_SYSSTATUS_DISPC_FUNC_RESETDONE GENMASK(0, 0) + #define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI) #define DISPC_IRQSTATUS_RAW REG(DISPC_IRQSTATUS_RAW) #define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS) #define DISPC_IRQENABLE_SET REG(DISPC_IRQENABLE_SET) #define DISPC_IRQENABLE_CLR REG(DISPC_IRQENABLE_CLR) @@ -68,13 +73,19 @@ enum dispc_common_regs { #define DISPC_VP_IRQSTATUS(n) (REG(DISPC_VP_IRQSTATUS) + (n) * 4) #define WB_IRQENABLE REG(WB_IRQENABLE) #define WB_IRQSTATUS REG(WB_IRQSTATUS) =20 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE REG(DISPC_GLOBAL_MFLAG_ATTRIBUTE) +#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK GENMASK(6, 6) +#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK GENMASK(1, 0) + #define DISPC_GLOBAL_OUTPUT_ENABLE REG(DISPC_GLOBAL_OUTPUT_ENABLE) #define DISPC_GLOBAL_BUFFER REG(DISPC_GLOBAL_BUFFER) #define DSS_CBA_CFG REG(DSS_CBA_CFG) +#define DSS_CBA_CFG_PRI_HI_MASK GENMASK(5, 3) +#define DSS_CBA_CFG_PRI_LO_MASK GENMASK(2, 0) + #define DISPC_DBG_CONTROL REG(DISPC_DBG_CONTROL) #define DISPC_DBG_STATUS REG(DISPC_DBG_STATUS) #define DISPC_CLKGATING_DISABLE REG(DISPC_CLKGATING_DISABLE) #define DISPC_SECURE_DISABLE REG(DISPC_SECURE_DISABLE) =20 @@ -86,10 +97,13 @@ enum dispc_common_regs { #define FBDC_REVISION_6 REG(FBDC_REVISION_6) #define FBDC_COMMON_CONTROL REG(FBDC_COMMON_CONTROL) #define FBDC_CONSTANT_COLOR_0 REG(FBDC_CONSTANT_COLOR_0) #define FBDC_CONSTANT_COLOR_1 REG(FBDC_CONSTANT_COLOR_1) #define DISPC_CONNECTIONS REG(DISPC_CONNECTIONS) +#define DISPC_CONNECTIONS_DPI_1_CONN_MASK GENMASK(7, 4) +#define DISPC_CONNECTIONS_DPI_0_CONN_MASK GENMASK(3, 0) + #define DISPC_MSS_VP1 REG(DISPC_MSS_VP1) #define DISPC_MSS_VP3 REG(DISPC_MSS_VP3) =20 /* VID */ =20 @@ -100,17 +114,31 @@ enum dispc_common_regs { #define DISPC_VID_ACCUV_0 0x10 #define DISPC_VID_ACCUV_1 0x14 #define DISPC_VID_ACCUV2_0 0x18 #define DISPC_VID_ACCUV2_1 0x1c #define DISPC_VID_ATTRIBUTES 0x20 +#define DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK GENMASK(28, 28) +#define DISPC_VID_ATTRIBUTES_VERTICALTAPS_MASK GENMASK(21, 21) +#define DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK GENMASK(19, 19) +#define DISPC_VID_ATTRIBUTES_COLORCONVENABLE_MASK GENMASK(9, 9) +#define DISPC_VID_ATTRIBUTES_VRESIZEENABLE_MASK GENMASK(8, 8) +#define DISPC_VID_ATTRIBUTES_HRESIZEENABLE_MASK GENMASK(7, 7) +#define DISPC_VID_ATTRIBUTES_FORMAT_MASK GENMASK(6, 1) +#define DISPC_VID_ATTRIBUTES_ENABLE_MASK GENMASK(0, 0) + #define DISPC_VID_ATTRIBUTES2 0x24 #define DISPC_VID_BA_0 0x28 #define DISPC_VID_BA_1 0x2c #define DISPC_VID_BA_UV_0 0x30 #define DISPC_VID_BA_UV_1 0x34 #define DISPC_VID_BUF_SIZE_STATUS 0x38 +#define DISPC_VID_BUF_SIZE_STATUS_BUFSIZE_MASK GENMASK(15, 0) + #define DISPC_VID_BUF_THRESHOLD 0x3c +#define DISPC_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK GENMASK(31, 16) +#define DISPC_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK GENMASK(15, 0) + #define DISPC_VID_CSC_COEF(n) (0x40 + (n) * 4) =20 #define DISPC_VID_FIRH 0x5c #define DISPC_VID_FIRH2 0x60 #define DISPC_VID_FIRV 0x64 @@ -135,19 +163,30 @@ enum dispc_common_regs { #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) #define DISPC_VID_FIR_COEFS_V12_C 0x1bc #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) =20 #define DISPC_VID_GLOBAL_ALPHA 0x1fc +#define DISPC_VID_GLOBAL_ALPHA_GLOBALALPHA_MASK GENMASK(7, 0) + #define DISPC_VID_K2G_IRQENABLE 0x200 /* K2G */ #define DISPC_VID_K2G_IRQSTATUS 0x204 /* K2G */ #define DISPC_VID_MFLAG_THRESHOLD 0x208 +#define DISPC_VID_MFLAG_THRESHOLD_HT_MFLAG_MASK GENMASK(31, 16) +#define DISPC_VID_MFLAG_THRESHOLD_LT_MFLAG_MASK GENMASK(15, 0) + #define DISPC_VID_PICTURE_SIZE 0x20c +#define DISPC_VID_PICTURE_SIZE_MEMSIZEY_MASK GENMASK(27, 16) +#define DISPC_VID_PICTURE_SIZE_MEMSIZEX_MASK GENMASK(11, 0) + #define DISPC_VID_PIXEL_INC 0x210 #define DISPC_VID_K2G_POSITION 0x214 /* K2G */ #define DISPC_VID_PRELOAD 0x218 #define DISPC_VID_ROW_INC 0x21c #define DISPC_VID_SIZE 0x220 +#define DISPC_VID_SIZE_SIZEY_MASK GENMASK(27, 16) +#define DISPC_VID_SIZE_SIZEX_MASK GENMASK(11, 0) + #define DISPC_VID_BA_EXT_0 0x22c #define DISPC_VID_BA_EXT_1 0x230 #define DISPC_VID_BA_UV_EXT_0 0x234 #define DISPC_VID_BA_UV_EXT_1 0x238 #define DISPC_VID_CSC_COEF7 0x23c @@ -171,15 +210,31 @@ enum dispc_common_regs { #define DISPC_OVR_TRANS_COLOR_MAX 0x10 #define DISPC_OVR_TRANS_COLOR_MAX2 0x14 #define DISPC_OVR_TRANS_COLOR_MIN 0x18 #define DISPC_OVR_TRANS_COLOR_MIN2 0x1c #define DISPC_OVR_ATTRIBUTES(n) (0x20 + (n) * 4) +#define DISPC_OVR_ATTRIBUTES_POSY_MASK GENMASK(30, 19) +#define DISPC_OVR_ATTRIBUTES_POSX_MASK GENMASK(17, 6) +#define DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK GENMASK(4, 1) +#define DISPC_OVR_ATTRIBUTES_ENABLE_MASK GENMASK(0, 0) + #define DISPC_OVR_ATTRIBUTES2(n) (0x34 + (n) * 4) /* J721E */ +#define DISPC_OVR_ATTRIBUTES2_POSY_MASK GENMASK(29, 16) +#define DISPC_OVR_ATTRIBUTES2_POSX_MASK GENMASK(13, 0) + /* VP */ =20 #define DISPC_VP_CONFIG 0x0 +#define DISPC_VP_CONFIG_COLORCONVENABLE_MASK GENMASK(24, 24) +#define DISPC_VP_CONFIG_CPR_MASK GENMASK(15, 15) +#define DISPC_VP_CONFIG_GAMMAENABLE_MASK GENMASK(2, 2) + #define DISPC_VP_CONTROL 0x4 +#define DISPC_VP_CONTROL_DATALINES_MASK GENMASK(10, 8) +#define DISPC_VP_CONTROL_GOBIT_MASK GENMASK(5, 5) +#define DISPC_VP_CONTROL_ENABLE_MASK GENMASK(0, 0) + #define DISPC_VP_CSC_COEF0 0x8 #define DISPC_VP_CSC_COEF1 0xc #define DISPC_VP_CSC_COEF2 0x10 #define DISPC_VP_DATA_CYCLE_0 0x14 #define DISPC_VP_DATA_CYCLE_1 0x18 @@ -187,13 +242,32 @@ enum dispc_common_regs { #define DISPC_VP_K2G_IRQENABLE 0x3c /* K2G */ #define DISPC_VP_K2G_IRQSTATUS 0x40 /* K2G */ #define DISPC_VP_DATA_CYCLE_2 0x1c #define DISPC_VP_LINE_NUMBER 0x44 #define DISPC_VP_POL_FREQ 0x4c +#define DISPC_VP_POL_FREQ_ALIGN_MASK GENMASK(18, 18) +#define DISPC_VP_POL_FREQ_ONOFF_MASK GENMASK(17, 17) +#define DISPC_VP_POL_FREQ_RF_MASK GENMASK(16, 16) +#define DISPC_VP_POL_FREQ_IEO_MASK GENMASK(15, 15) +#define DISPC_VP_POL_FREQ_IPC_MASK GENMASK(14, 14) +#define DISPC_VP_POL_FREQ_IHS_MASK GENMASK(13, 13) +#define DISPC_VP_POL_FREQ_IVS_MASK GENMASK(12, 12) + #define DISPC_VP_SIZE_SCREEN 0x50 +#define DISPC_VP_SIZE_SCREEN_HDISPLAY_MASK GENMASK(11, 0) +#define DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK GENMASK(27, 16) + #define DISPC_VP_TIMING_H 0x54 +#define DISPC_VP_TIMING_H_SYNC_PULSE_MASK GENMASK(7, 0) +#define DISPC_VP_TIMING_H_FRONT_PORCH_MASK GENMASK(19, 8) +#define DISPC_VP_TIMING_H_BACK_PORCH_MASK GENMASK(31, 20) + #define DISPC_VP_TIMING_V 0x58 +#define DISPC_VP_TIMING_V_SYNC_PULSE_MASK GENMASK(7, 0) +#define DISPC_VP_TIMING_V_FRONT_PORCH_MASK GENMASK(19, 8) +#define DISPC_VP_TIMING_V_BACK_PORCH_MASK GENMASK(31, 20) + #define DISPC_VP_CSC_COEF3 0x5c #define DISPC_VP_CSC_COEF4 0x60 #define DISPC_VP_CSC_COEF5 0x64 #define DISPC_VP_CSC_COEF6 0x68 #define DISPC_VP_CSC_COEF7 0x6c @@ -218,10 +292,12 @@ enum dispc_common_regs { #define DISPC_VP_SAFETY_SIZE_2 0xf8 #define DISPC_VP_SAFETY_SIZE_3 0xfc #define DISPC_VP_SAFETY_LFSR_SEED 0x110 #define DISPC_VP_GAMMA_TABLE 0x120 #define DISPC_VP_DSS_OLDI_CFG 0x160 +#define DISPC_VP_DSS_OLDI_CFG_MAP_MASK GENMASK(3, 1) + #define DISPC_VP_DSS_OLDI_STATUS 0x164 #define DISPC_VP_DSS_OLDI_LB 0x168 #define DISPC_VP_DSS_MERGE_SPLIT 0x16c /* J721E */ #define DISPC_VP_DSS_DMA_THREADSIZE 0x170 /* J721E */ #define DISPC_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */ --=20 2.50.1