From nobody Fri Oct 3 16:47:14 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 710F0352FDD for ; Wed, 27 Aug 2025 13:12:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756300362; cv=none; b=uGO7W+mnGaFVn1iz/XO/cjnicJqlFWPSFwpvL/kD6DMp1F+JLjuBgyzulXaT3uv+exbWwY1+yq76JzPVnLFvCVq3qZSXVIvhcRWGBTKCJm66o9LNSD9sHqHdUNLf17TJypoGUHOQ2IFR/yOikKNOBNq6RHQvkKiqxZfdPgzK6yw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756300362; c=relaxed/simple; bh=nKzM8+DhB3mWRo1Uw19AVwyiwRjw8Y1noKAdLwZJkWQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bxCFSTDjQyYwOtXHjpV8WYLwDTtzNEb3BsuYVTOHN2GIW1a29mynerF+OJOJv2CtcHSN4x4ZrO3/tSAHFxeRsFMnqkci/7a94AUHjzon6oXE9UuzXc3iKb5jX0rVun6iTHbcYZUzUA88469BKt51U+gJZeszehWtAgZxD2KhIC8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=hlpX3Cgq; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="hlpX3Cgq" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57R6kHeM031273 for ; Wed, 27 Aug 2025 13:12:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 0K02dLIrIWIN69se35x4CnkEpVg0hHnCCy6M9lvO6aU=; b=hlpX3Cgq9PI8Ogtd ZnmfYnpQ8xVLGqxxpquvw6T4+YvPRuQAMtm59eS0ObxoENEv7uikORUSbGIvYdwg wlfr7RYl6/4dX+lZ2uzUalVqebaBpqVAv9UBRQeDAkBH3r5CNLMtTSfgwl1+KJ6t Zd2G9nPqADz+xFNYovJXBRTVA2Jmj1K94w2TddsvcgRQv798DkjWTvC91ofQG43W dBNH1598mJJvSATE/ejERQc3psYMuaMIgHk2/KAVkcQb9w4/dTJHB8ipk0dT2e+J 1MJrMwk0I1OCLgq0g01D29gnroviDUi6DRng/t4faIsyXkMMgq0o8ys8hZbAONb5 0ccSQg== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48q615mmbv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 27 Aug 2025 13:12:39 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-771e331f176so2815396b3a.1 for ; Wed, 27 Aug 2025 06:12:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756300358; x=1756905158; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0K02dLIrIWIN69se35x4CnkEpVg0hHnCCy6M9lvO6aU=; b=bzLlTbi/wny0AhJZfH5cOY4KZMQnaR5U9uPx9WlGTLUrhGu2OL9dJpTWxOIhEvfuds EWNIHc7qlVdJc5pe6Td9HuVL4orkn8AS+pQfKbyUPnmhBdAngGgL2Tb2frJMLIHjSZHE 59sxD+QZBAAPxgZzu2U0aS6P5fCZ7UBGpks7TCA8qnJLv9rruzVbJeMVZj6CF1207wi/ t2EOkNJzKw6yFGYwp8czMu1rvVp2uOr7CWmSwWNUd7P5PJIe4/aW7GV10VMTDmbXtDiO XLqnyr+KJYd1MZwewD/y5cu3B2XLvZBYtiq+j6OVDm0hmfCux67PNPXrTvSk2e/a1kwF h3CA== X-Forwarded-Encrypted: i=1; AJvYcCXqfUimOopBI/kWMSzbDuy0WBk2ugH8QQAyCY3b7sGVc4aB+AgdARfdGdhZRxgrmMNYaFPJ6BwndJgEHig=@vger.kernel.org X-Gm-Message-State: AOJu0YwhhfvODelLzHfktbNRSEcGrGcFw3jTIzaEulBq72oo7oD4G5c6 7K5FmRYpOv0L2bN+9jOCm+arO/pZpvIVT/VNG5REeGy8itPCnnU9hrBLHSaRiDi72+cILOIMRnz 5DDxqz6hR2ozXlc8LbCAnZ1tbGg0MWE7r+u9G1sAlu/h/cU1pF8M6qz9rn7LMeOZzOAc= X-Gm-Gg: ASbGncuHcO2oknAfEa1nJ5C9SYuYl2f/WijW37uiJ/xLZK8yoCO5BIEiTIm9SYH6iNZ v+gXJLBeOenVf4LMUF+FDT3n8fAuaBUVz2sml7MhOzKw3Esuf/COABkBKVtWpHDo4843z/qFvtT PcVRBxq8JZUCjxOnjhkR3VXHjrb8NDYko2Z0/VBO87HbuQ9XHocMh5jJmaMMx6mnU2h36VcvajF eRdtmzwjS9E2SlLvATTfe9DA8WNQAzuZwTC/o637COMSG2ndB//THG4lj979eBiVVCqaJ/BZEU2 edh86h2od3lTH9HyqF4yCYIxCTV4sx78WVBjJEWdYrDugtC0bAqGYHhVOPCd21lMaWN6qfw4DF5 MBD7vT5UuyPP2D7ruW+j/XsZiIvMHPOkLGspADG1wmxIq1EeNMBf4AO2c X-Received: by 2002:a05:6a20:939d:b0:243:78a:8294 with SMTP id adf61e73a8af0-24340e2f1a5mr30724909637.59.1756300357970; Wed, 27 Aug 2025 06:12:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFBKKDmbMeCpOSy/V169srY8qPeL/qgsPevEwM/hT8H/icksjXaQ5N1HO9nHIp0yrYZozdFGQ== X-Received: by 2002:a05:6a20:939d:b0:243:78a:8294 with SMTP id adf61e73a8af0-24340e2f1a5mr30724851637.59.1756300357399; Wed, 27 Aug 2025 06:12:37 -0700 (PDT) Received: from sziotdisp01-gv.qualcomm.com.ap.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b49cbba615csm11432972a12.44.2025.08.27.06.12.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 06:12:37 -0700 (PDT) From: Fange Zhang Date: Wed, 27 Aug 2025 21:08:38 +0800 Subject: [PATCH v7 1/2] arm64: dts: qcom: Add display support for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-add-display-support-for-qcs615-platform-v7-1-917c3de8f9ca@oss.qualcomm.com> References: <20250827-add-display-support-for-qcs615-platform-v7-0-917c3de8f9ca@oss.qualcomm.com> In-Reply-To: <20250827-add-display-support-for-qcs615-platform-v7-0-917c3de8f9ca@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, xiangxu.yin@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Li Liu , Fange Zhang , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756300349; l=5827; i=fange.zhang@oss.qualcomm.com; s=20250714; h=from:subject:message-id; bh=uXlwezLY7U3gqs8X4zeTpdCd9Lux78E+OqnciVI8/Jk=; b=4QCsko4TNHA7JgPUEWBuuCeWIgOcS62ypyAm4JzHV39qtIaFzMwkIcz0WAvVQsBP8CBYD02bK vipxDCz/ZfyDzndyLIhPVUbiPCd2AGodzIDzFlKfZ+W/c8lhFI30MP6 X-Developer-Key: i=fange.zhang@oss.qualcomm.com; a=ed25519; pk=tn190A7bjF3/EyH7AYy/eNzPoS9lwXGznYamlMv6TE0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzNCBTYWx0ZWRfX3+ZoK1D5mJHw 0bjq3PF8P6J1txpEcE5IMLuRr2Ih43midtrB9lbTU8HiUYP2NhUiBlwNaxHcigsxkoH7/J1zi01 y1Y3gDyR8T5CF+xXdd1wzskPXbRdhz3zY3+xrILJUbgDEyGodRkEJ1UOwjQ10RenRLqRUV13yi8 GfB+Ua+aOOwyuUc7OifZ+k6IDUvrTe1qJwOAolgh3Wiq9HqlJDyehfIzIGZdkM0y0puE4+jjLb/ LBYFtw5Qrmd8aKu0pX3YVZLhrJqA+8jmWIahggRmS83Tt9kQ5QDnFzR1wXR/EhfiDDvvQ2IjeVX 5SZsa9dIdrZw8zZ3EB2ndWUyXxegkELaK5CyW6DZQs6ojisW1V7cDmFsxzGYR6PDhobSFYJ8gzC 57rs6lVd X-Proofpoint-GUID: iiVBHAf-OwEE8HUnRgUl468-4i-iLAmw X-Authority-Analysis: v=2.4 cv=K+AiHzWI c=1 sm=1 tr=0 ts=68af0447 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=Roi-LC9FDB9nNxv02foA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: iiVBHAf-OwEE8HUnRgUl468-4i-iLAmw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-27_03,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 impostorscore=0 priorityscore=1501 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230034 From: Li Liu Add display MDSS and DSI configuration for QCS615 platform. QCS615 has a DP port, and DP support will be added in a later patch. Reviewed-by: Dmitry Baryshkov Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 182 +++++++++++++++++++++++++++++++= +++- 1 file changed, 180 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index 53496241479a05fec7bffa893b96b2d12b2d7614..c0e6485c148a059f6c0b2d221a9= ee34b0220ea06 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 +#include #include #include #include @@ -3579,14 +3580,191 @@ camcc: clock-controller@ad00000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,sm6150-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc MDSS_CORE_GDSC>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x800 0x0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sm6150-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names =3D "mdp", + "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + interrupts-extended =3D <&mdss 0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf0_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-307200000 { + opp-hz =3D /bits/ 64 <307200000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae94000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&dsi0_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + phys =3D <&mdss_dsi0_phy>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-164000000 { + opp-hz =3D /bits/ 64 <164000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,sm6150-dsi-phy-14nm"; + reg =3D <0x0 0x0ae94400 0x0 0x100>, + <0x0 0x0ae94500 0x0 0x300>, + <0x0 0x0ae94800 0x0 0x124>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + status =3D "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible =3D "qcom,qcs615-dispcc"; reg =3D <0 0x0af00000 0 0x20000>; =20 clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, - <0>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, <0>, <0>; --=20 2.34.1 From nobody Fri Oct 3 16:47:14 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F960352FF5 for ; Wed, 27 Aug 2025 13:12:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756300366; cv=none; b=o6QHTExw/cc3qclyd4p9o/PzmS1WM0zr4U+E5nK+ILnsNQOHY56oX7bHALT44RuyQOV6fsEcfkzJpjWL5l5tvuVahx+ASknrvAg6tDlYpfll7UJbiIFpqPPKK9y2mCi+paZ6SdJDXrioFdv8qJ33XbTWBtcKwVTKKz7v39YO12s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756300366; c=relaxed/simple; bh=lkEkNI6U5UMNHhspuDTyPj/+zirteVHnTk56Di9FfME=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jhpe24fSV8p8r8OLDz1/laA711yc6dfecNg3rxGqyGG5nwtTWiCsHiRoAONK/PiDUGWoJE5TRb8m3qlmia9XnDsgozyt0kjc3HAIAFZZaT92C+Pi6xu3DFZJ4ETnsTUOd0sBEjVGO4h2Hqzy3/efcHj1vWpltwTu72ElvQz3GTk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=JhY4Qw17; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="JhY4Qw17" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57R6kgxj031439 for ; Wed, 27 Aug 2025 13:12:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= bl2TJs4T4ux1GQlk8A5Nbj4tfsZuZ244zRVaui58pQM=; b=JhY4Qw17s+bMt+L7 sZhWvqrCeNWST8IP2HDJa9j9I70zvQC4aQxCYgmFv5pNw4AHTKON/mBR1m8QVHUc YhjVVvnfsk1LtKyuvIKHep/wbk/DJxOqRaFk8kElGIPbZN3ZBb4n67IIV7CYokDt //i0k2Jq+IE5XFXRkRcl+sTvVqA6+abEqpm/1vtrF6yLXsIj61rp6n5M2T+Dforh gMAj2PHf28NZsWwI1zQ+atxUmoBJNr2tyObsdIFnScmLzkwiYD0S/lLYWem6hdtA LzTCPLXxx99Q0xqCYqj2oivLTkErj9JUAf715yfdE3WkSZqlgYTHOE+TMqenzsNk 5kjFew== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48q615mmc2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 27 Aug 2025 13:12:43 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-7704769dbb0so4053825b3a.2 for ; Wed, 27 Aug 2025 06:12:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756300362; x=1756905162; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bl2TJs4T4ux1GQlk8A5Nbj4tfsZuZ244zRVaui58pQM=; b=CtNLJj3rXXYPZbpcP3l2bCXJ2PTB3CsN6OZTPIOmWsT3Om/dkuHhq2FlF54hcFLVo8 2l34neUXmL0gZmRydi/OVMjoMdajTyYvq9k/D1TEvnIG3ZGvKwkm2t7UYozD+eZw3ZB8 HeQczw0JBqUUtR7cfPU86Gc1y1U57RdUapbp23KjY9v6NlfvVgBUpVfFd8uHZL5Gfjwx W7p4pbB2L62mDgtPPgvy4Ob0pUVMoTO1C5i0jGAfo5u/iCBOHonAmMFTMZw7kaNrrtVj MyeNWyugLXXFAjvJvg9w8pz1zfHoHsMHnjejTGbHi9AcpQqHmlOovkqEOs3z8fsTrDBf Xq3w== X-Forwarded-Encrypted: i=1; AJvYcCVHikJue1qsgcMxUoaQi6AErrpTSCI+u1D/OJ2UJDcBCHLa13WM/PN+7ICLe86EMooRrF2XleL4P7vAzJM=@vger.kernel.org X-Gm-Message-State: AOJu0Yyi1G8O8x0eVRFo0NxEWfGyvJnDF1NDygrcMR8Sj2afdANuewkl 7fd0UL7RciKNNryTgRSj06BJFi8+dnfaFNmJX2BolitCwXoC1Vtba8aGLsEmYW6iBPaI030EDz2 hk6+FiVofNk8U9aKy5sB6yZO+iWMawN84aso/xGi7DaxaZ5o15gdmnjZcVREKeTXzVTY= X-Gm-Gg: ASbGncueuFI8TFGVmH17vnt4ww0RIC+5yykr3lHfwQFLe4KNwbrVULkLftvF8UJlkIu xdL7EiZRFfgvRZow2zQUXazDyIGOtq3z+zWb55n0eCoHALnkZ06P95al7Mq5SisU+C5NLuZuBMf lsRp2WOTXeGOdK2UHTwnsAFCj+fHvy3j/9zhuioTGaak/yUy4o+oJd0Jb0xLV8i0OjtnpUGSBiI NkXNDwY62J/LqciJuz2MSKwbB9qzcJ6gT4O0Ci4lSXbly1I1dOkW9RHMUMdlfz+HVeeShYI3T/G URN6InbYyr85uSTG6EjPdYdFkhxyppryAoCsd6WS2wn+CzI7FTVSlaICemzt/imQ/d/V0fNkHQY sa0hnq97UXUVbRBJ3k81Nr8mRz6Q+jE/HABiJP/fioucQ0Uj4VStuh1S6 X-Received: by 2002:a05:6a20:939e:b0:21a:e751:e048 with SMTP id adf61e73a8af0-24340d7bb9emr27246344637.35.1756300361753; Wed, 27 Aug 2025 06:12:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEKv0SxiOk8HOhjqipABcYHZo/NM6n3Rzp99dkCa0YkacESHFFYUFbAP41DOIrGC4Tn3dm1tw== X-Received: by 2002:a05:6a20:939e:b0:21a:e751:e048 with SMTP id adf61e73a8af0-24340d7bb9emr27246287637.35.1756300361246; Wed, 27 Aug 2025 06:12:41 -0700 (PDT) Received: from sziotdisp01-gv.qualcomm.com.ap.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b49cbba615csm11432972a12.44.2025.08.27.06.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 06:12:40 -0700 (PDT) From: Fange Zhang Date: Wed, 27 Aug 2025 21:08:39 +0800 Subject: [PATCH v7 2/2] arm64: dts: qcom: Add display support for QCS615 RIDE board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-add-display-support-for-qcs615-platform-v7-2-917c3de8f9ca@oss.qualcomm.com> References: <20250827-add-display-support-for-qcs615-platform-v7-0-917c3de8f9ca@oss.qualcomm.com> In-Reply-To: <20250827-add-display-support-for-qcs615-platform-v7-0-917c3de8f9ca@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, xiangxu.yin@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Li Liu , Fange Zhang , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756300349; l=4229; i=fange.zhang@oss.qualcomm.com; s=20250714; h=from:subject:message-id; bh=0A09/X7LZ/FPKuEalGbQvn6eLOGaYhze9r/cZSPB9CE=; b=UjWhjMIjhsB4/ZoMtsO6oPaI14B3iw7RmRmQ1GfzI23d4kAQbu3yu9diD0pxQZGJmrtjf7ZhJ JL25beEd5OZB3p6trsGHDfi+YU1F5j0tIppIwymtjWfA3Zh3bPYEywP X-Developer-Key: i=fange.zhang@oss.qualcomm.com; a=ed25519; pk=tn190A7bjF3/EyH7AYy/eNzPoS9lwXGznYamlMv6TE0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzNCBTYWx0ZWRfXzjXy8iaOm6CO zbCnfZ3NQf+tHNpfxJRIwTaKIoGyVqi82TDEyOmXsiqWvWXjnGm0gKDM1PKMVKHaJr4jwE4RdET RuCV7up4TfsQbYlGO9aqxOT/s+t+p9oQi6RJTwJfw0Prwj/Gi2ShBJADSIeb4QRK027BDQLu31W zLaz+L9RLuUAQJdAXPZdpsmaZsU7FARVkeOOj+Yv/lZ+Z+AC43NwjS/qifwshtFUEQfG7Jevu7c 3f9dWzVUnl/TCX6Ng6SND/hP4jThanMfVclLSD50KHMk7jZfj8t82tl8dsJX1Z4rbkN+3D7tenm DZhRfGiKvXa4EJSeFQ7XnHixoQIyf9iS2KNr8E17QpI/LQAfi3LJhgiXflSrry+82Y9bmjDubS/ b0gEHTso X-Proofpoint-GUID: qMzPv91J-l_bjKgyw4V1upINsk3870Br X-Authority-Analysis: v=2.4 cv=K+AiHzWI c=1 sm=1 tr=0 ts=68af044b cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=M5YQ4GC9HTMohWAA_GoA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: qMzPv91J-l_bjKgyw4V1upINsk3870Br X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-27_03,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 impostorscore=0 priorityscore=1501 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230034 From: Li Liu Add display MDSS and DSI configuration for QCS615 RIDE board. QCS615 has a DP port, and DP support will be added in a later patch. Reviewed-by: Dmitry Baryshkov Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 150 +++++++++++++++++++++++++++= ++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index e663343df75d59481786192cde647017a83c4191..f6e0c82cf85459d8989332497de= d8b6ea3670c76 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -39,6 +39,76 @@ xo_board_clk: xo-board-clk { }; }; =20 + dp-dsi0-connector { + compatible =3D "dp-connector"; + label =3D "DSI0"; + type =3D "mini"; + + port { + dp_dsi0_connector_in: endpoint { + remote-endpoint =3D <&dsi2dp_bridge_out>; + }; + }; + }; + + vreg_12p0: vreg-12p0-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_12P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vreg_5p0: vreg-5p0-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_5P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + vin-supply =3D <&vreg_12p0>; + }; + + vreg_1p8: vreg-1p8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P8"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + vin-supply =3D <&vreg_5p0>; + }; + + vreg_1p0: vreg-1p0-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + + vin-supply =3D <&vreg_1p8>; + }; + + vreg_3p0: vreg-3p0-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_3P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + vin-supply =3D <&vreg_12p0>; + }; + vreg_conn_1p8: regulator-conn-1p8 { compatible =3D "regulator-fixed"; regulator-name =3D "vreg_conn_1p8"; @@ -288,6 +358,86 @@ vreg_l17a: ldo17 { }; }; =20 +&i2c2 { + clock-frequency =3D <400000>; + status =3D "okay"; + + io_expander: pinctrl@3e { + compatible =3D "semtech,sx1509q"; + reg =3D <0x3e>; + interrupts-extended =3D <&tlmm 58 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + semtech,probe-reset; + }; + + i2c-mux@77 { + compatible =3D "nxp,pca9542"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + bridge@58 { + compatible =3D "analogix,anx7625"; + reg =3D <0x58>; + interrupts-extended =3D <&io_expander 0 IRQ_TYPE_EDGE_FALLING>; + enable-gpios =3D <&tlmm 4 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&tlmm 5 GPIO_ACTIVE_HIGH>; + vdd10-supply =3D <&vreg_1p0>; + vdd18-supply =3D <&vreg_1p8>; + vdd33-supply =3D <&vreg_3p0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dsi2dp_bridge_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + dsi2dp_bridge_out: endpoint { + remote-endpoint =3D <&dp_dsi0_connector_in>; + }; + }; + }; + }; + }; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l11a>; + status =3D "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&dsi2dp_bridge_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vcca-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + &pcie { perst-gpios =3D <&tlmm 101 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 100 GPIO_ACTIVE_HIGH>; --=20 2.34.1