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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cc890b178bsm3272069f8f.52.2025.08.27.05.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 05:59:49 -0700 (PDT) From: Tudor Ambarus Date: Wed, 27 Aug 2025 12:59:46 +0000 Subject: [PATCH v2 1/3] arm64: dts: exynos: gs101: add #clock-cells to the ACPM protocol node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-acpm-dvfs-dt-v2-1-e1d2890d12b4@linaro.org> References: <20250827-acpm-dvfs-dt-v2-0-e1d2890d12b4@linaro.org> In-Reply-To: <20250827-acpm-dvfs-dt-v2-0-e1d2890d12b4@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756299588; l=858; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=lXqAHsVVGobAqxHDBDj2hfAW5L/ixpf0F+OYYJ4nT/w=; b=1hf3mcPjyceW9nVsY3YJaxdSK+F2L7MXoZnBJFli89bCPqeG8RhhWI+dgSmVFITri3grRwv4z cDeXEVit+3jDX/fnKLE9QVz2WyAluN7lZ9fP3bWF51Nsyhbi7g8lZJ0 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Make the ACPM node a clock provider by adding the mandatory "#clock-cells" property, which allows devices to reference its clock outputs. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index c0f8c25861a9ddb5bbd256b62c66a645922ca74e..f00754692bbac39fd828ebd4ef7= c269f746f2522 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -202,6 +202,7 @@ ext_200m: clock-2 { firmware { acpm_ipc: power-management { compatible =3D "google,gs101-acpm-ipc"; + #clock-cells =3D <1>; mboxes =3D <&ap2apm_mailbox>; shmem =3D <&apm_sram>; }; --=20 2.51.0.261.g7ce5a0a67e-goog From nobody Fri Oct 3 16:46:07 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF2F8337694 for ; Wed, 27 Aug 2025 12:59:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756299594; cv=none; b=rQcvVEQzkAaOz9Q5EoN+97vufZfp1lbc57YQD6EywffVbpcIHuKAcDqCPAgfPOto++4arPasErkiUH+CS9O1sviu+fB2/cB2KBkL7TZEdcE52cwIbJMb9+TaLQht2cx0WFGGKIrAnyTc2DZtswnO0eqEYLGlfHC+6AeK5Smo5DY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756299594; c=relaxed/simple; bh=uoqgJ3OhNeN6asyWKYrHarA0VMYib5B/PdW+OT7cv0M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QGjO6Jsd5lzJG4lPke7QOKvvyxvtzhgYNvBDU7UilyRsiBI8suGSi1t2zWyW7RGWmBqK+uiefkPzP3MiKkHS1x1VKHVviCKeqjhc1lp9AQqYQmnLp8ZPlZnxXEe9F+MR/dE8aR1V6UQx3h2DFQZ/brn6hz8dieMwlmN3OwDwUFw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=h/gC66OC; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="h/gC66OC" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-45a1b065d59so39594505e9.1 for ; Wed, 27 Aug 2025 05:59:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756299591; x=1756904391; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OjK6OpIk8kyuSL5lFjeicimOy3JEve15WbehlqoxKGY=; b=h/gC66OCfB1RPBkJ9usBZQrAPpBfc55SUL7i5ZXrZMBFl0QKndqvPmDyiB7iyGr7vU t8k54017UuMo1SEdbpKnkuoLl64fKKhBeDrCBLDQyUJ4FXS4T7dOFZCAdG6FgoavUx8+ w7zqKgE9qw+fxN6lt7ZMQZXjFpZUygNPqTTOY7TIB8T3z6b62NWlM+coLbi59YQ569zj l/VJjL0gblVlDcYGDM2J+UQL+RyYBIKMuQnmx2zb+8N0cFFhc3yUmej+EW8XsOFvdbeJ 8ia1VeIM97g3LRERSZdSspf69gBLAssH3j4Lj/w1jUud0EAkyg5zk3E24CkShBkEKovJ EJ4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756299591; x=1756904391; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OjK6OpIk8kyuSL5lFjeicimOy3JEve15WbehlqoxKGY=; b=E/6jVHH31QsBXEKzotCA4L1bVv7utOh3GNM1lw9cud3uhV1vGUbj6ABFqL7zBTn66a wdDZhyn1RmidopLbWoC6aNz/gYUAVQaWzT20YmqFnL3/eGCw26TKUhjupNKEzgz2J59H Kq1Bn7j/pPgpw7KhCOTG6nP92Px2Zcdu7jzZYwJPUMDL/8UcN+b0gPRta8cQz6SxNSGb aBogWc/3InNnzkKi0M6Aw2CqQLdI76tNM3SkqisTRiuoQloT64n3VkIxYkY2JpQfS8L+ lJUrXL+1yrUs99Vd0GCuFA14cmY/FB8n++nmME7XnHNRXhcrzhFxkBXxywwaJl31BUvX ndtw== X-Forwarded-Encrypted: i=1; AJvYcCXKZzbHmVW0Ul/o55N/r4brIvcX7oa0TXWh+C9TnrfxiW5EC7e/dfgOOif8IeAjnqgPvocUb/ey0mzwKSk=@vger.kernel.org X-Gm-Message-State: AOJu0YyFB/608V3bFMMcwVeZZye8zmH4bG0poQ/XjEbfibvAgUJYbT25 o50CzGSvXMaTJGKUvTE06JEDMSSpy0AySDK0U1MY8YgUSTQf9BRM2V07YQ/kSW8e1WM= X-Gm-Gg: ASbGncvA9cmtVmVqOGkcpey5bLej339wEeeaVuKZHyvGYpoYzJ5mHG84P5lTWc/E2a+ alFlK4DE8VogibO4EtJd9o3P9eNfE0mMFPii3oZJ5/K/VrwyDsw/gccepRpr6HNDTPZlAJc0fqC RYIredBCZXXgkF45kwW7bUidSO615DYmH8Wu0n2cFH4LxX/yQWnE03RRHc+lPKVxL+GvwLprLa0 TQKdB5tpfGlAulQ7/ykGbARgZFNYnIkQ8F82sjp4MciGLzI0z7S/awspLtzRqFRUmHKvltj6WFS d3f4apWWd1OhcCmpV+DxHS9WZMSGx0QhSBAVe0OKjlKegkWr5o4EvEL63RAX7nYUjja2SmyKjmb Ng18vl/x0FWVUXsLR/QtMt6jtXPYW17/xKTFMqiZ5+Fe8WGWP4S3KBV3TJn8VNQLJNqEbKASpaS GYKaLxoeYVH8Zd X-Google-Smtp-Source: AGHT+IHPwrsF3Jtd95IZMfDq3CXcF1TLGO6gNbOm6NJUOa4ZfiI/Wp4VmFA1B9k12eMcZCO8op0PEw== X-Received: by 2002:a05:600c:4689:b0:458:bc3f:6a72 with SMTP id 5b1f17b1804b1-45b517954femr168350295e9.4.1756299590870; Wed, 27 Aug 2025 05:59:50 -0700 (PDT) Received: from ta2.c.googlers.com (219.43.233.35.bc.googleusercontent.com. [35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cc890b178bsm3272069f8f.52.2025.08.27.05.59.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 05:59:50 -0700 (PDT) From: Tudor Ambarus Date: Wed, 27 Aug 2025 12:59:47 +0000 Subject: [PATCH v2 2/3] arm64: dts: exynos: gs101: add CPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-acpm-dvfs-dt-v2-2-e1d2890d12b4@linaro.org> References: <20250827-acpm-dvfs-dt-v2-0-e1d2890d12b4@linaro.org> In-Reply-To: <20250827-acpm-dvfs-dt-v2-0-e1d2890d12b4@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756299588; l=2740; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=uoqgJ3OhNeN6asyWKYrHarA0VMYib5B/PdW+OT7cv0M=; b=vnVVuPmKG+UU58DxmUVjQUGxPgldzUS4A/j/jb9225yIdT/j7J7EUC0BGjTM1lU6pntynAPaO KdDzTE4di3OCQQZG6n3zIstYLljRQ4YZMRzjMl2OPkxhUs7ftmOMYdd X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the GS101 CPU clocks exposed through the ACPM protocol. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index f00754692bbac39fd828ebd4ef7c269f746f2522..746b7d8ecdc90fd746015b83229= 24bac66c6e363 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -72,6 +72,7 @@ cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0000>; + clocks =3D <&acpm_ipc CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -82,6 +83,7 @@ cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0100>; + clocks =3D <&acpm_ipc CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -92,6 +94,7 @@ cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0200>; + clocks =3D <&acpm_ipc CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -102,6 +105,7 @@ cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0300>; + clocks =3D <&acpm_ipc CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -112,6 +116,7 @@ cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a76"; reg =3D <0x0400>; + clocks =3D <&acpm_ipc CLK_ACPM_DVFS_CPUCL1>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -122,6 +127,7 @@ cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a76"; reg =3D <0x0500>; + clocks =3D <&acpm_ipc CLK_ACPM_DVFS_CPUCL1>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -132,6 +138,7 @@ cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-x1"; 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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cc890b178bsm3272069f8f.52.2025.08.27.05.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 05:59:51 -0700 (PDT) From: Tudor Ambarus Date: Wed, 27 Aug 2025 12:59:48 +0000 Subject: [PATCH v2 3/3] arm64: dts: exynos: gs101: add OPPs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-acpm-dvfs-dt-v2-3-e1d2890d12b4@linaro.org> References: <20250827-acpm-dvfs-dt-v2-0-e1d2890d12b4@linaro.org> In-Reply-To: <20250827-acpm-dvfs-dt-v2-0-e1d2890d12b4@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756299588; l=8498; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=ilKTGpL8p+yK7fouXhyJKKJIn3wFUBwNKCBuAYnOCV8=; b=+4DwtbmbSXHX8w9ZZm7MGqJrAgJXHbEKXLufGVn24jsLCZ/kxgUxDSosmoI6WPwggJIhMNpzi Raq7kDhKzQbBcbDRNhbfsyzqLO9tT7VtLUJFnfjt1XEPc8+YlFumYxb X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add operating performance points (OPPs). Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 275 +++++++++++++++++++++++= ++++ 1 file changed, 275 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 746b7d8ecdc90fd746015b8322924bac66c6e363..0bd7e8181c40754f19626a49ded= c3a6fe65525b8 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -77,6 +77,7 @@ cpu0: cpu@0 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu1: cpu@100 { @@ -88,6 +89,7 @@ cpu1: cpu@100 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu2: cpu@200 { @@ -99,6 +101,7 @@ cpu2: cpu@200 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu3: cpu@300 { @@ -110,6 +113,7 @@ cpu3: cpu@300 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu4: cpu@400 { @@ -121,6 +125,7 @@ cpu4: cpu@400 { cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; dynamic-power-coefficient =3D <284>; + operating-points-v2 =3D <&cpucl1_opp_table>; }; =20 cpu5: cpu@500 { @@ -132,6 +137,7 @@ cpu5: cpu@500 { cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; dynamic-power-coefficient =3D <284>; + operating-points-v2 =3D <&cpucl1_opp_table>; }; =20 cpu6: cpu@600 { @@ -143,6 +149,7 @@ cpu6: cpu@600 { cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <650>; + operating-points-v2 =3D <&cpucl2_opp_table>; }; =20 cpu7: cpu@700 { @@ -154,6 +161,7 @@ cpu7: cpu@700 { cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <650>; + operating-points-v2 =3D <&cpucl2_opp_table>; }; =20 idle-states { @@ -191,6 +199,273 @@ hera_cpu_sleep: cpu-hera-sleep { }; }; =20 + cpucl0_opp_table: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-microvolt =3D <537500>; + clock-latency-ns =3D <5000000>; + }; + + opp-574000000 { + opp-hz =3D /bits/ 64 <574000000>; + opp-microvolt =3D <600000>; + clock-latency-ns =3D <5000000>; + }; + + opp-738000000 { + opp-hz =3D /bits/ 64 <738000000>; + opp-microvolt =3D <618750>; + clock-latency-ns =3D <5000000>; + }; + + opp-930000000 { + opp-hz =3D /bits/ 64 <930000000>; + opp-microvolt =3D <668750>; + clock-latency-ns =3D <5000000>; + }; + + opp-1098000000 { + opp-hz =3D /bits/ 64 <1098000000>; + opp-microvolt =3D <712500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1197000000 { + opp-hz =3D /bits/ 64 <1197000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1328000000 { + opp-hz =3D /bits/ 64 <1328000000>; + opp-microvolt =3D <762500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1401000000 { + opp-hz =3D /bits/ 64 <1401000000>; + opp-microvolt =3D <781250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1598000000 { + opp-hz =3D /bits/ 64 <1598000000>; + opp-microvolt =3D <831250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1704000000 { + opp-hz =3D /bits/ 64 <1704000000>; + opp-microvolt =3D <862500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1803000000 { + opp-hz =3D /bits/ 64 <1803000000>; + opp-microvolt =3D <906250>; + clock-latency-ns =3D <5000000>; + }; + }; + + cpucl1_opp_table: opp-table-1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <506250>; + clock-latency-ns =3D <5000000>; + }; + + opp-553000000 { + opp-hz =3D /bits/ 64 <553000000>; + opp-microvolt =3D <537500>; + clock-latency-ns =3D <5000000>; + }; + + opp-696000000 { + opp-hz =3D /bits/ 64 <696000000>; + opp-microvolt =3D <562500>; + clock-latency-ns =3D <5000000>; + }; + + opp-799000000 { + opp-hz =3D /bits/ 64 <799000000>; + opp-microvolt =3D <581250>; + clock-latency-ns =3D <5000000>; + }; + + opp-910000000 { + opp-hz =3D /bits/ 64 <910000000>; + opp-microvolt =3D <606250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1024000000 { + opp-hz =3D /bits/ 64 <1024000000>; + opp-microvolt =3D <625000>; + clock-latency-ns =3D <5000000>; + }; + + opp-1197000000 { + opp-hz =3D /bits/ 64 <1197000000>; + opp-microvolt =3D <662500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1328000000 { + opp-hz =3D /bits/ 64 <1328000000>; + opp-microvolt =3D <687500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1491000000 { + opp-hz =3D /bits/ 64 <1491000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1663000000 { + opp-hz =3D /bits/ 64 <1663000000>; + opp-microvolt =3D <775000>; + clock-latency-ns =3D <5000000>; + }; + + opp-1836000000 { + opp-hz =3D /bits/ 64 <1836000000>; + opp-microvolt =3D <818750>; + clock-latency-ns =3D <5000000>; + }; + + opp-1999000000 { + opp-hz =3D /bits/ 64 <1999000000>; + opp-microvolt =3D <868750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2130000000 { + opp-hz =3D /bits/ 64 <2130000000>; + opp-microvolt =3D <918750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2253000000 { + opp-hz =3D /bits/ 64 <2253000000>; + opp-microvolt =3D <968750>; + clock-latency-ns =3D <5000000>; + }; + }; + + cpucl2_opp_table: opp-table-2 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <500000>; + clock-latency-ns =3D <5000000>; + }; + + opp-851000000 { + opp-hz =3D /bits/ 64 <851000000>; + opp-microvolt =3D <556250>; + clock-latency-ns =3D <5000000>; + }; + + opp-984000000 { + opp-hz =3D /bits/ 64 <984000000>; + opp-microvolt =3D <575000>; + clock-latency-ns =3D <5000000>; + }; + + opp-1106000000 { + opp-hz =3D /bits/ 64 <1106000000>; + opp-microvolt =3D <606250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1277000000 { + opp-hz =3D /bits/ 64 <1277000000>; + opp-microvolt =3D <631250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1426000000 { + opp-hz =3D /bits/ 64 <1426000000>; + opp-microvolt =3D <662500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1582000000 { + opp-hz =3D /bits/ 64 <1582000000>; + opp-microvolt =3D <693750>; + clock-latency-ns =3D <5000000>; + }; + + opp-1745000000 { + opp-hz =3D /bits/ 64 <1745000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1826000000 { + opp-hz =3D /bits/ 64 <1826000000>; + opp-microvolt =3D <750000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2048000000 { + opp-hz =3D /bits/ 64 <2048000000>; + opp-microvolt =3D <793750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2188000000 { + opp-hz =3D /bits/ 64 <2188000000>; + opp-microvolt =3D <831250>; + clock-latency-ns =3D <5000000>; + }; + + opp-2252000000 { + opp-hz =3D /bits/ 64 <2252000000>; + opp-microvolt =3D <850000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2401000000 { + opp-hz =3D /bits/ 64 <2401000000>; + opp-microvolt =3D <887500>; + clock-latency-ns =3D <5000000>; + }; + + opp-2507000000 { + opp-hz =3D /bits/ 64 <2507000000>; + opp-microvolt =3D <925000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2630000000 { + opp-hz =3D /bits/ 64 <2630000000>; + opp-microvolt =3D <968750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2704000000 { + opp-hz =3D /bits/ 64 <2704000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2802000000 { + opp-hz =3D /bits/ 64 <2802000000>; + opp-microvolt =3D <1056250>; + clock-latency-ns =3D <5000000>; + }; + }; + /* ect node is required to be present by bootloader */ ect { }; --=20 2.51.0.261.g7ce5a0a67e-goog