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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cbab3ead0dsm6439420f8f.29.2025.08.27.05.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 05:42:16 -0700 (PDT) From: Tudor Ambarus Date: Wed, 27 Aug 2025 12:42:11 +0000 Subject: [PATCH v2 1/5] dt-bindings: firmware: google,gs101-acpm-ipc: add #clock-cells Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-acpm-clk-v2-1-de5c86b49b64@linaro.org> References: <20250827-acpm-clk-v2-0-de5c86b49b64@linaro.org> In-Reply-To: <20250827-acpm-clk-v2-0-de5c86b49b64@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756298535; l=2754; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=ivbLWWSo2AaBA+S6bzVV0jpPuv1cVq4qNDd5/EibisY=; b=jl6fjNfftMkX+rPDiw2pF9HsB0qXrHHMzr8xpgTmZfEOJY03K4MIPCWkyzWB/j3LgkvZrBT68 GDx/C3dBu+4A66KQUUz7VWUAOuuKPFIsClt1SzgoiSICpAyQE4+ChYq X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= The firmware exposes clocks that can be controlled via the Alive Clock and Power Manager (ACPM) interface. Make the ACPM node a clock provider by adding the mandatory "#clock-cells" property, which allows devices to reference its clock outputs. Signed-off-by: Tudor Ambarus Reviewed-by: Rob Herring (Arm) --- .../bindings/firmware/google,gs101-acpm-ipc.yaml | 11 +++++++++++ include/dt-bindings/clock/google,gs101.h | 15 +++++++++++= ++++ 2 files changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-i= pc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.= yaml index 9785aac3b5f34955bbfe2718eec48581d050954f..d3bca6088d128485618bb2b538e= d8596b4ba14f0 100644 --- a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -24,6 +24,15 @@ properties: compatible: const: google,gs101-acpm-ipc =20 + "#clock-cells": + const: 1 + description: + Clocks that are variable and index based. These clocks don't provide + an entire range of values between the limits but only discrete points + within the range. The firmware also manages the voltage scaling + appropriately with the clock scaling. The argument is the ID of the + clock contained by the firmware messages. + mboxes: maxItems: 1 =20 @@ -45,6 +54,7 @@ properties: =20 required: - compatible + - "#clock-cells" - mboxes - shmem =20 @@ -56,6 +66,7 @@ examples: =20 power-management { compatible =3D "google,gs101-acpm-ipc"; + #clock-cells =3D <1>; mboxes =3D <&ap2apm_mailbox>; shmem =3D <&apm_sram>; =20 diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings= /clock/google,gs101.h index 442f9e9037dc33198a1cee20af62fc70bbd96605..f1d0df412fdd49b300db4ba88bc= 0b1674cf0cdf8 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -634,4 +634,19 @@ #define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45 #define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46 =20 +#define CLK_ACPM_DVFS_MIF 0 +#define CLK_ACPM_DVFS_INT 1 +#define CLK_ACPM_DVFS_CPUCL0 2 +#define CLK_ACPM_DVFS_CPUCL1 3 +#define CLK_ACPM_DVFS_CPUCL2 4 +#define CLK_ACPM_DVFS_G3D 5 +#define CLK_ACPM_DVFS_G3DL2 6 +#define CLK_ACPM_DVFS_TPU 7 +#define CLK_ACPM_DVFS_INTCAM 8 +#define CLK_ACPM_DVFS_TNR 9 +#define CLK_ACPM_DVFS_CAM 10 +#define CLK_ACPM_DVFS_MFC 11 +#define CLK_ACPM_DVFS_DISP 12 +#define CLK_ACPM_DVFS_BO 13 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ --=20 2.51.0.261.g7ce5a0a67e-goog From nobody Fri Oct 3 16:46:07 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74E3534DCF6 for ; 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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cbab3ead0dsm6439420f8f.29.2025.08.27.05.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 05:42:17 -0700 (PDT) From: Tudor Ambarus Date: Wed, 27 Aug 2025 12:42:12 +0000 Subject: [PATCH v2 2/5] firmware: exynos-acpm: add DVFS protocol Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-acpm-clk-v2-2-de5c86b49b64@linaro.org> References: <20250827-acpm-clk-v2-0-de5c86b49b64@linaro.org> In-Reply-To: <20250827-acpm-clk-v2-0-de5c86b49b64@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756298535; l=6599; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=hxMcE7MRiIJXv//ASvuI744f53HEqEa5zNpqOkTvDes=; b=zAssuZW+Qm18GDKV7k/CCeZa4oZUq1Cp8+cLNEmuG2PU8y4tEzF6A7NhtFDCQBNSggLFOv4dd op5WdKZEfQ9BjgU8kgo+CAkoHlDHN63EOUyS010qA+9NOzP4Fs+0URa X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add ACPM DVFS protocol handler. It constructs DVFS messages that the APM firmware can understand. Signed-off-by: Tudor Ambarus --- drivers/firmware/samsung/Makefile | 4 +- drivers/firmware/samsung/exynos-acpm-dvfs.c | 83 ++++++++++++++++++= ++++ drivers/firmware/samsung/exynos-acpm-dvfs.h | 21 ++++++ drivers/firmware/samsung/exynos-acpm.c | 5 ++ .../linux/firmware/samsung/exynos-acpm-protocol.h | 10 +++ 5 files changed, 122 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/samsung/Makefile b/drivers/firmware/samsung/M= akefile index 7b4c9f6f34f54fd731886d97a615fe1aa97ba9a0..80d4f89b33a9558b68c9083da67= 5c70ec3d05f19 100644 --- a/drivers/firmware/samsung/Makefile +++ b/drivers/firmware/samsung/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only =20 -acpm-protocol-objs :=3D exynos-acpm.o exynos-acpm-pmic.o +acpm-protocol-objs :=3D exynos-acpm.o +acpm-protocol-objs +=3D exynos-acpm-pmic.o +acpm-protocol-objs +=3D exynos-acpm-dvfs.o obj-$(CONFIG_EXYNOS_ACPM_PROTOCOL) +=3D acpm-protocol.o diff --git a/drivers/firmware/samsung/exynos-acpm-dvfs.c b/drivers/firmware= /samsung/exynos-acpm-dvfs.c new file mode 100644 index 0000000000000000000000000000000000000000..a8763bf9374d41952a8d26124cc= 77baae0f1c723 --- /dev/null +++ b/drivers/firmware/samsung/exynos-acpm-dvfs.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2025 Linaro Ltd. + */ + +#include +#include +#include +#include +#include + +#include "exynos-acpm.h" +#include "exynos-acpm-dvfs.h" + +#define ACPM_DVFS_ID GENMASK(11, 0) +#define ACPM_DVFS_REQ_TYPE GENMASK(15, 0) + +#define ACPM_DVFS_FREQ_REQ 0 +#define ACPM_DVFS_FREQ_GET 1 + +static void acpm_dvfs_set_xfer(struct acpm_xfer *xfer, u32 *cmd, size_t cm= dlen, + unsigned int acpm_chan_id, bool response) +{ + xfer->acpm_chan_id =3D acpm_chan_id; + xfer->txd =3D cmd; + xfer->txlen =3D cmdlen; + + if (response) { + xfer->rxd =3D cmd; + xfer->rxlen =3D cmdlen; + } +} + +static void acpm_dvfs_init_set_rate_cmd(u32 cmd[4], unsigned int clk_id, + unsigned long rate) +{ + cmd[0] =3D FIELD_PREP(ACPM_DVFS_ID, clk_id); + cmd[1] =3D rate / HZ_PER_KHZ; + cmd[2] =3D FIELD_PREP(ACPM_DVFS_REQ_TYPE, ACPM_DVFS_FREQ_REQ); + cmd[3] =3D ktime_to_ms(ktime_get()); +} + +int acpm_dvfs_set_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + unsigned long rate) +{ + struct acpm_xfer xfer =3D {0}; + u32 cmd[4]; + + acpm_dvfs_init_set_rate_cmd(cmd, clk_id, rate); + acpm_dvfs_set_xfer(&xfer, cmd, sizeof(cmd), acpm_chan_id, false); + + return acpm_do_xfer(handle, &xfer); +} + +static void acpm_dvfs_init_get_rate_cmd(u32 cmd[4], unsigned int clk_id, + u32 dbg_val) +{ + cmd[0] =3D FIELD_PREP(ACPM_DVFS_ID, clk_id); + cmd[1] =3D dbg_val; + cmd[2] =3D FIELD_PREP(ACPM_DVFS_REQ_TYPE, ACPM_DVFS_FREQ_GET); + cmd[3] =3D ktime_to_ms(ktime_get()); +} + +unsigned long acpm_dvfs_get_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + u32 dbg_val) +{ + struct acpm_xfer xfer; + unsigned int cmd[4]; + int ret; + + acpm_dvfs_init_get_rate_cmd(cmd, clk_id, dbg_val); + acpm_dvfs_set_xfer(&xfer, cmd, sizeof(cmd), acpm_chan_id, true); + + ret =3D acpm_do_xfer(handle, &xfer); + if (ret) + return 0; + + return xfer.rxd[1] * HZ_PER_KHZ; +} diff --git a/drivers/firmware/samsung/exynos-acpm-dvfs.h b/drivers/firmware= /samsung/exynos-acpm-dvfs.h new file mode 100644 index 0000000000000000000000000000000000000000..85a10bd535d118f2f36e9888e41= b9b705b08ea59 --- /dev/null +++ b/drivers/firmware/samsung/exynos-acpm-dvfs.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2025 Linaro Ltd. + */ +#ifndef __EXYNOS_ACPM_DVFS_H__ +#define __EXYNOS_ACPM_DVFS_H__ + +#include + +struct acpm_handle; + +int acpm_dvfs_set_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int id, + unsigned long rate); +unsigned long acpm_dvfs_get_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + u32 dbg_val); + +#endif /* __EXYNOS_ACPM_DVFS_H__ */ diff --git a/drivers/firmware/samsung/exynos-acpm.c b/drivers/firmware/sams= ung/exynos-acpm.c index 3a69fe3234c75e0b5a93cbea6bb210dc6f69d2a6..9fa0335ccf5db32892fdf09e8d4= b0a885a8f8fb5 100644 --- a/drivers/firmware/samsung/exynos-acpm.c +++ b/drivers/firmware/samsung/exynos-acpm.c @@ -29,6 +29,7 @@ #include =20 #include "exynos-acpm.h" +#include "exynos-acpm-dvfs.h" #include "exynos-acpm-pmic.h" =20 #define ACPM_PROTOCOL_SEQNUM GENMASK(21, 16) @@ -590,8 +591,12 @@ static int acpm_channels_init(struct acpm_info *acpm) */ static void acpm_setup_ops(struct acpm_info *acpm) { + struct acpm_dvfs_ops *dvfs_ops =3D &acpm->handle.ops.dvfs_ops; struct acpm_pmic_ops *pmic_ops =3D &acpm->handle.ops.pmic_ops; =20 + dvfs_ops->set_rate =3D acpm_dvfs_set_rate; + dvfs_ops->get_rate =3D acpm_dvfs_get_rate; + pmic_ops->read_reg =3D acpm_pmic_read_reg; pmic_ops->bulk_read =3D acpm_pmic_bulk_read; pmic_ops->write_reg =3D acpm_pmic_write_reg; diff --git a/include/linux/firmware/samsung/exynos-acpm-protocol.h b/includ= e/linux/firmware/samsung/exynos-acpm-protocol.h index f628bf1862c25fa018a2fe5e7e123bf05c5254b9..e41055316bb578bb8250a1b1177= f1059eeeb2611 100644 --- a/include/linux/firmware/samsung/exynos-acpm-protocol.h +++ b/include/linux/firmware/samsung/exynos-acpm-protocol.h @@ -13,6 +13,15 @@ struct acpm_handle; struct device_node; =20 +struct acpm_dvfs_ops { + int (*set_rate)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + unsigned long rate); + unsigned long (*get_rate)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, + unsigned int clk_id, u32 dbg_val); +}; + struct acpm_pmic_ops { int (*read_reg)(const struct acpm_handle *handle, unsigned int acpm_chan_id, u8 type, u8 reg, u8 chan, @@ -32,6 +41,7 @@ struct acpm_pmic_ops { }; =20 struct acpm_ops { + struct acpm_dvfs_ops dvfs_ops; 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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cbab3ead0dsm6439420f8f.29.2025.08.27.05.42.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 05:42:17 -0700 (PDT) From: Tudor Ambarus Date: Wed, 27 Aug 2025 12:42:13 +0000 Subject: [PATCH v2 3/5] clk: samsung: add Exynos ACPM clock driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-acpm-clk-v2-3-de5c86b49b64@linaro.org> References: <20250827-acpm-clk-v2-0-de5c86b49b64@linaro.org> In-Reply-To: <20250827-acpm-clk-v2-0-de5c86b49b64@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756298535; l=7253; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=CjPSf0JcvfE5W5RPnVdJxx5tBeiX99q+c7xebVDWfmk=; b=0Ba+Ymd/OUWS8Zi93fBaCsEVXNgbYq78bO0mwgK4kg9TlZDI6WFDwGs7+rI9Z0K4sI8CHUorN CG+HjumlfJhDktCvJuIyjJ+H2cH4OiKHmSeTNLKVoB3TA8dHZBqJ7ab X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the Exynos ACPM clock driver. It provides support for clocks that are controlled by firmware that implements the ACPM interface. Signed-off-by: Tudor Ambarus --- drivers/clk/samsung/Kconfig | 10 +++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-acpm.c | 148 +++++++++++++++++++++++++++++= ++++ include/linux/platform_data/clk-acpm.h | 24 ++++++ 4 files changed, 183 insertions(+) diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 76a494e95027af26272e30876a87ac293bd56dfa..fe05212d7dd882adde9cd5c656c= d0d58d501c42f 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -95,6 +95,16 @@ config EXYNOS_CLKOUT status of the certains clocks from SoC, but it could also be tied to other devices as an input clock. =20 +config EXYNOS_ACPM_CLK + tristate "Clock driver controlled via ACPM interface" + depends on EXYNOS_ACPM_PROTOCOL || COMPILE_TEST + help + This driver provides support for clocks that are controlled by + firmware that implements the ACPM interface. + + This driver uses the ACPM interface to interact with the firmware + providing all the clock controlls. + config TESLA_FSD_COMMON_CLK bool "Tesla FSD clock controller support" if COMPILE_TEST depends on COMMON_CLK_SAMSUNG diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index b77fe288e4bb484c68d1ff497acc0b83d132ea03..04b63436b12f6f5169575d74f54= b105e97bbb052 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos990.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynosautov9.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynosautov920.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-gs101.o +obj-$(CONFIG_EXYNOS_ACPM_CLK) +=3D clk-acpm.o obj-$(CONFIG_S3C64XX_COMMON_CLK) +=3D clk-s3c64xx.o obj-$(CONFIG_S5PV210_COMMON_CLK) +=3D clk-s5pv210.o clk-s5pv210-audss.o obj-$(CONFIG_TESLA_FSD_COMMON_CLK) +=3D clk-fsd.o diff --git a/drivers/clk/samsung/clk-acpm.c b/drivers/clk/samsung/clk-acpm.c new file mode 100644 index 0000000000000000000000000000000000000000..e0db63ba1e07efdae53e340bc24= c3576b2a5fd04 --- /dev/null +++ b/drivers/clk/samsung/clk-acpm.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung Exynos ACPM protocol based clock driver. + * + * Copyright 2025 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct acpm_clk { + u32 id; + struct clk_hw hw; + unsigned int mbox_chan_id; + const struct acpm_handle *handle; +}; + +#define to_acpm_clk(clk) container_of(clk, struct acpm_clk, hw) + +static unsigned long acpm_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct acpm_clk *clk =3D to_acpm_clk(hw); + + return clk->handle->ops.dvfs_ops.get_rate(clk->handle, + clk->mbox_chan_id, clk->id, 0); +} + +static int acpm_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + /* + * We can't figure out what rate it will be, so just return the + * rate back to the caller. acpm_clk_recalc_rate() will be called + * after the rate is set and we'll know what rate the clock is + * running at then. + */ + return 0; +} + +static int acpm_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct acpm_clk *clk =3D to_acpm_clk(hw); + + return clk->handle->ops.dvfs_ops.set_rate(clk->handle, + clk->mbox_chan_id, clk->id, rate); +} + +static const struct clk_ops acpm_clk_ops =3D { + .recalc_rate =3D acpm_clk_recalc_rate, + .determine_rate =3D acpm_clk_determine_rate, + .set_rate =3D acpm_clk_set_rate, +}; + +static int acpm_clk_ops_init(struct device *dev, struct acpm_clk *aclk, + const char *name) +{ + struct clk_init_data init =3D {}; + + init.name =3D name; + init.ops =3D &acpm_clk_ops; + aclk->hw.init =3D &init; + + return devm_clk_hw_register(dev, &aclk->hw); +} + +static int acpm_clk_probe(struct platform_device *pdev) +{ + const struct acpm_clk_platform_data *pdata; + const struct acpm_handle *acpm_handle; + struct clk_hw_onecell_data *clk_data; + struct clk_hw **hws; + struct device *dev =3D &pdev->dev; + struct acpm_clk *aclks; + unsigned int mbox_chan_id; + int i, err, count; + + pdata =3D dev_get_platdata(&pdev->dev); + if (!pdata) + return dev_err_probe(dev, -EINVAL, + "Failed to get platform data.\n"); + + acpm_handle =3D devm_acpm_get_by_node(dev, dev->parent->of_node); + if (IS_ERR(acpm_handle)) + return dev_err_probe(dev, PTR_ERR(acpm_handle), + "Failed to get acpm handle.\n"); + + count =3D pdata->nr_clks; + mbox_chan_id =3D pdata->mbox_chan_id; + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, count), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num =3D count; + hws =3D clk_data->hws; + + aclks =3D devm_kcalloc(dev, count, sizeof(*aclks), GFP_KERNEL); + if (!aclks) + return -ENOMEM; + + for (i =3D 0; i < count; i++) { + const struct acpm_clk_variant *variant =3D &pdata->clks[i]; + unsigned int id =3D variant->id; + struct acpm_clk *aclk; + + if (id >=3D count) + return dev_err_probe(dev, -EINVAL, + "Invalid ACPM clock ID.\n"); + + aclk =3D &aclks[id]; + aclk->id =3D id; + aclk->handle =3D acpm_handle; + aclk->mbox_chan_id =3D mbox_chan_id; + + hws[id] =3D &aclk->hw; + + err =3D acpm_clk_ops_init(dev, aclk, variant->name); + if (err) + return dev_err_probe(dev, err, + "Failed to register clock.\n"); + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clk_data); +} + +static struct platform_driver acpm_clk_driver =3D { + .driver =3D { + .name =3D "acpm-clocks", + }, + .probe =3D acpm_clk_probe, +}; +module_platform_driver(acpm_clk_driver); + +MODULE_ALIAS("platform:acpm-clocks"); +MODULE_AUTHOR("Tudor Ambarus "); +MODULE_DESCRIPTION("Samsung Exynos ACPM clock driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/platform_data/clk-acpm.h b/include/linux/platfor= m_data/clk-acpm.h new file mode 100644 index 0000000000000000000000000000000000000000..8327435fbb603472346b14b8116= 0ffe98a79486b --- /dev/null +++ b/include/linux/platform_data/clk-acpm.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Samsung Exynos Alive Clock and Power Manager (ACPM) clock driver. + * + * Copyright 2025 Linaro Ltd. + */ + +#ifndef __LINUX_PLATFORM_DATA_CLK_ACPM_H__ +#define __LINUX_PLATFORM_DATA_CLK_ACPM_H__ + +#include + +struct acpm_clk_variant { + unsigned int id; + const char *name; +}; + +struct acpm_clk_platform_data { + const struct acpm_clk_variant *clks; + unsigned int nr_clks; + unsigned int mbox_chan_id; +}; + +#endif /* __LINUX_PLATFORM_DATA_CLK_ACPM_H__ */ --=20 2.51.0.261.g7ce5a0a67e-goog From nobody Fri Oct 3 16:46:07 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FB8F34F47E for ; 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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cbab3ead0dsm6439420f8f.29.2025.08.27.05.42.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 05:42:18 -0700 (PDT) From: Tudor Ambarus Date: Wed, 27 Aug 2025 12:42:14 +0000 Subject: [PATCH v2 4/5] firmware: exynos-acpm: register ACPM clocks dev Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-acpm-clk-v2-4-de5c86b49b64@linaro.org> References: <20250827-acpm-clk-v2-0-de5c86b49b64@linaro.org> In-Reply-To: <20250827-acpm-clk-v2-0-de5c86b49b64@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756298535; l=5210; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=GciBv6TscMWoUL5NOWHvgdZWg70tQo2b5jzt+et6cck=; b=GS+9vzYJP6T4ggVpRCRv6J4WvF9fBE/H6F09fimItPewcc/1VJ9tRuthqg3yPNy+9zXnUVBvU ukecEb66+HWAfBZ7JoAEuzjmTBSm7Uw9ybIAmdsFdHdZYdNJKT/66XL X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Register by hand a platform device for the ACPM clocks. The ACPM clocks are not modeled as a DT child of ACPM because: 1/ they don't have their own resources. 2/ they are not a block that can be reused. The clock identifying data is reduced (clock ID, clock name and mailbox channel ID) and may differ from a SoC to another. Signed-off-by: Tudor Ambarus --- drivers/firmware/samsung/exynos-acpm.c | 64 ++++++++++++++++++++++++++++++= +++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/samsung/exynos-acpm.c b/drivers/firmware/sams= ung/exynos-acpm.c index 9fa0335ccf5db32892fdf09e8d4b0a885a8f8fb5..86a220a845d2934aa28e9bb8996= cf914f65cdae6 100644 --- a/drivers/firmware/samsung/exynos-acpm.c +++ b/drivers/firmware/samsung/exynos-acpm.c @@ -24,10 +24,13 @@ #include #include #include +#include #include #include #include =20 +#include + #include "exynos-acpm.h" #include "exynos-acpm-dvfs.h" #include "exynos-acpm-pmic.h" @@ -160,6 +163,7 @@ struct acpm_chan { * struct acpm_info - driver's private data. * @shmem: pointer to the SRAM configuration data. * @sram_base: base address of SRAM. + * @clk_pdev: ACPM clocks platform device. * @chans: pointer to the ACPM channel parameters retrieved from SRAM. * @dev: pointer to the exynos-acpm device. * @handle: instance of acpm_handle to send to clients. @@ -168,6 +172,7 @@ struct acpm_chan { struct acpm_info { struct acpm_shmem __iomem *shmem; void __iomem *sram_base; + struct platform_device *clk_pdev; struct acpm_chan *chans; struct device *dev; struct acpm_handle handle; @@ -177,14 +182,39 @@ struct acpm_info { /** * struct acpm_match_data - of_device_id data. * @initdata_base: offset in SRAM where the channels configuration resides. + * @acpm_clk_pdata: ACPM clocks platform data. */ struct acpm_match_data { loff_t initdata_base; + const struct acpm_clk_platform_data *acpm_clk_pdata; }; =20 #define client_to_acpm_chan(c) container_of(c, struct acpm_chan, cl) #define handle_to_acpm_info(h) container_of(h, struct acpm_info, handle) =20 +#define ACPM_CLK(_id, cname) \ + { \ + .id =3D _id, \ + .name =3D cname, \ + } + +static const struct acpm_clk_variant gs101_acpm_clks[] =3D { + ACPM_CLK(CLK_ACPM_DVFS_MIF, "mif"), + ACPM_CLK(CLK_ACPM_DVFS_INT, "int"), + ACPM_CLK(CLK_ACPM_DVFS_CPUCL0, "cpucl0"), + ACPM_CLK(CLK_ACPM_DVFS_CPUCL1, "cpucl1"), + ACPM_CLK(CLK_ACPM_DVFS_CPUCL2, "cpucl2"), + ACPM_CLK(CLK_ACPM_DVFS_G3D, "g3d"), + ACPM_CLK(CLK_ACPM_DVFS_G3DL2, "g3dl2"), + ACPM_CLK(CLK_ACPM_DVFS_TPU, "tpu"), + ACPM_CLK(CLK_ACPM_DVFS_INTCAM, "intcam"), + ACPM_CLK(CLK_ACPM_DVFS_TNR, "tnr"), + ACPM_CLK(CLK_ACPM_DVFS_CAM, "cam"), + ACPM_CLK(CLK_ACPM_DVFS_MFC, "mfc"), + ACPM_CLK(CLK_ACPM_DVFS_DISP, "disp"), + ACPM_CLK(CLK_ACPM_DVFS_BO, "b0"), +}; + /** * acpm_get_saved_rx() - get the response if it was already saved. * @achan: ACPM channel info. @@ -606,6 +636,7 @@ static void acpm_setup_ops(struct acpm_info *acpm) =20 static int acpm_probe(struct platform_device *pdev) { + const struct acpm_clk_platform_data *acpm_clk_pdata; const struct acpm_match_data *match_data; struct device *dev =3D &pdev->dev; struct device_node *shmem; @@ -647,7 +678,30 @@ static int acpm_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, acpm); =20 - return devm_of_platform_populate(dev); + acpm_clk_pdata =3D match_data->acpm_clk_pdata; + acpm->clk_pdev =3D platform_device_register_data(dev, "acpm-clocks", + PLATFORM_DEVID_NONE, + acpm_clk_pdata, + sizeof(*acpm_clk_pdata)); + if (IS_ERR(acpm->clk_pdev)) + return dev_err_probe(dev, PTR_ERR(acpm->clk_pdev), + "Failed to register ACPM clocks device.\n"); + + ret =3D devm_of_platform_populate(dev); + if (ret) { + platform_device_unregister(acpm->clk_pdev); + return dev_err_probe(dev, ret, + "Failed to populate platform devices.\n"); + } + + return 0; +} + +static void acpm_remove(struct platform_device *pdev) +{ + struct acpm_info *acpm =3D platform_get_drvdata(pdev); + + platform_device_unregister(acpm->clk_pdev); } =20 /** @@ -744,8 +798,15 @@ const struct acpm_handle *devm_acpm_get_by_node(struct= device *dev, } EXPORT_SYMBOL_GPL(devm_acpm_get_by_node); =20 +static const struct acpm_clk_platform_data acpm_clk_gs101 =3D { + .clks =3D gs101_acpm_clks, + .nr_clks =3D ARRAY_SIZE(gs101_acpm_clks), + .mbox_chan_id =3D 0, +}; + static const struct acpm_match_data acpm_gs101 =3D { .initdata_base =3D ACPM_GS101_INITDATA_BASE, + .acpm_clk_pdata =3D &acpm_clk_gs101, }; =20 static const struct of_device_id acpm_match[] =3D { @@ -759,6 +820,7 @@ MODULE_DEVICE_TABLE(of, acpm_match); =20 static struct platform_driver acpm_driver =3D { .probe =3D acpm_probe, + .remove =3D acpm_remove, .driver =3D { .name =3D "exynos-acpm-protocol", .of_match_table =3D acpm_match, --=20 2.51.0.261.g7ce5a0a67e-goog From nobody Fri Oct 3 16:46:07 2025 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CD19350D45 for ; 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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cbab3ead0dsm6439420f8f.29.2025.08.27.05.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 05:42:19 -0700 (PDT) From: Tudor Ambarus Date: Wed, 27 Aug 2025 12:42:15 +0000 Subject: [PATCH v2 5/5] arm64: defconfig: enable Exynos ACPM clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250827-acpm-clk-v2-5-de5c86b49b64@linaro.org> References: <20250827-acpm-clk-v2-0-de5c86b49b64@linaro.org> In-Reply-To: <20250827-acpm-clk-v2-0-de5c86b49b64@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756298535; l=820; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=FUVnP6N7cHQr47dLL4bin/JIRmBbPwyaNW8naNR4SC8=; b=vr4YUS7k2uOJpKSWAUY/kzAsaucmPj03Ajnab4gJvYwF+6XrFjwzDMIGkG2H/vJmrLX4DqF85 Z56PRG77k/rBpCAlx0bGdbJTtH91a+wz1P3HRfiu3UXboI+aGKI2hkH X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Enable the Exynos ACPM clocks driver. Samsung Exynos platforms implement ACPM to provide support for clock configuration, PMIC and temperature sensors. Signed-off-by: Tudor Ambarus --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 58f87d09366cd12ae212a1d107660afe8be6c5ef..4255bc885545fb3bb7e9cf02760= cac35bf2872fa 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1445,6 +1445,7 @@ CONFIG_CLK_GFM_LPASS_SM8250=3Dm CONFIG_SM_VIDEOCC_8450=3Dm CONFIG_CLK_RCAR_USB2_CLOCK_SEL=3Dy CONFIG_CLK_RENESAS_VBATTB=3Dm +CONFIG_EXYNOS_ACPM_CLK=3Dm CONFIG_CLK_SOPHGO_CV1800=3Dy CONFIG_HWSPINLOCK=3Dy CONFIG_HWSPINLOCK_OMAP=3Dm --=20 2.51.0.261.g7ce5a0a67e-goog