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charset="utf-8" Add optional "limit-hs-gear" and "limit-rate" properties to the UFS controller common binding. These properties allow limiting the maximum HS gear and rate. This is useful in cases where the customer board may have signal integrity, clock configuration or layout issues that prevent reliable operation at higher gears. Such limitations are especially critical in those platforms, where stability is prioritized over peak performance. Signed-off-by: Ram Kumar Dwivedi --- .../devicetree/bindings/ufs/ufs-common.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml b/Docume= ntation/devicetree/bindings/ufs/ufs-common.yaml index 31fe7f30ff5b..1af658207901 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-common.yaml +++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml @@ -89,6 +89,24 @@ properties: =20 msi-parent: true =20 + limit-hs-gear: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 5 + default: 5 + description: + Restricts the maximum HS gear used in both TX and RX directions, + typically for hardware or power constraints in automotive use cases. + + limit-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + default: 2 + description: + Restricts the UFS controller to Rate A (1) or Rate B (2) for both + TX and RX directions, often required in automotive environments due + to hardware limitations. + dependencies: freq-table-hz: [ clocks ] operating-points-v2: [ clocks, clock-names ] --=20 2.50.1 From nobody Fri Oct 3 20:30:03 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2567D275AE6; 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charset="utf-8" Remove the redundant else block that assigns PA_HS_MODE_B to hs_rate, as it is already assigned in ufshcd_init_host_params(). This avoids unnecessary reassignment and prevents overwriting hs_rate when it is explicitly set to a different value. Signed-off-by: Ram Kumar Dwivedi --- drivers/ufs/host/ufs-qcom.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 9574fdc2bb0f..1a93351fb70e 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -494,12 +494,8 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *= hba) * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, * so that the subsequent power mode change shall stick to Rate-A. */ - if (host->hw_ver.major =3D=3D 0x5) { - if (host->phy_gear =3D=3D UFS_HS_G5) - host_params->hs_rate =3D PA_HS_MODE_A; - else - host_params->hs_rate =3D PA_HS_MODE_B; - } + if (host->hw_ver.major =3D=3D 0x5 && host->phy_gear =3D=3D UFS_HS_G5) + host_params->hs_rate =3D PA_HS_MODE_A; =20 mode =3D host_params->hs_rate =3D=3D PA_HS_MODE_B ? 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Tue, 26 Aug 2025 15:09:30 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57QF9TkX007899 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Aug 2025 15:09:29 GMT Received: from hu-rdwivedi-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Tue, 26 Aug 2025 08:09:24 -0700 From: Ram Kumar Dwivedi To: , , , , , , , , CC: , , , Subject: [PATCH V3 3/4] ufs: pltfrm: Allow limiting HS gear and rate via DT Date: Tue, 26 Aug 2025 20:38:54 +0530 Message-ID: <20250826150855.7725-4-quic_rdwivedi@quicinc.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250826150855.7725-1-quic_rdwivedi@quicinc.com> References: <20250826150855.7725-1-quic_rdwivedi@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfX/9Ms/SzpsZra j0G1KKcaGf7Cq/4vzmyEl5caNpTNX0wB/waVEbVbXWH6csKlBjIhNp124cikWEtxdfE57S6LdfE +mI5fsGrpiK0Xn3up9hg2cveZffscgPQfoIRTQDiXrkfdNPmtOunMeGW94LFR47imuSwDocn5mT Od8bCeiQMpqWHRs6IMoc1Oioi66au3j7uR5+/Bn462iOqknmvi/drduBYOrF8rS9K238g6ON0UZ NxX14t53qb9O1z9lj4/qDdpOYcFFKzyQgvg3vFMvmTNPqMxJycZDTyLbgS5bdErGKYfepTMZl0V GfGaMP39TZNT62Dt3W0Nu1T6Xc0O9IHSyyS74GjdHol2JWsV2SXzPTBlXfv+/RP22AjZH6Bfm6q tOtokXzF X-Proofpoint-GUID: mSQ2QnReZfEbERiDoDEEWFwZDwosvuqg X-Authority-Analysis: v=2.4 cv=MutS63ae c=1 sm=1 tr=0 ts=68adce2a cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=eseaCGvrkytYtZHUcXsA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: mSQ2QnReZfEbERiDoDEEWFwZDwosvuqg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 malwarescore=0 suspectscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 Content-Type: text/plain; charset="utf-8" Add support for parsing 'limit-hs-gear' and 'limit-rate' device tree properties to restrict high-speed gear and rate during initialization. This is useful in cases where the customer board may have signal integrity, clock configuration or layout issues that prevent reliable operation at higher gears. Such limitations are especially critical in those platforms, where stability is prioritized over peak performance. Signed-off-by: Ram Kumar Dwivedi --- drivers/ufs/host/ufshcd-pltfrm.c | 29 +++++++++++++++++++++++++++++ drivers/ufs/host/ufshcd-pltfrm.h | 1 + 2 files changed, 30 insertions(+) diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-plt= frm.c index ffe5d1d2b215..d9be6c86f044 100644 --- a/drivers/ufs/host/ufshcd-pltfrm.c +++ b/drivers/ufs/host/ufshcd-pltfrm.c @@ -430,6 +430,35 @@ int ufshcd_negotiate_pwr_params(const struct ufs_host_= params *host_params, } EXPORT_SYMBOL_GPL(ufshcd_negotiate_pwr_params); =20 +/** + * ufshcd_parse_limits - Parse DT-based gear and rate limits for UFS + * @hba: Pointer to UFS host bus adapter instance + * @host_params: Pointer to UFS host parameters structure to be updated + * + * This function reads optional device tree properties to apply + * platform-specific constraints. + * + * "limit-hs-gear": Specifies the max HS gear. + * "limit-rate": Specifies the max High-Speed rate. + */ +void ufshcd_parse_limits(struct ufs_hba *hba, struct ufs_host_params *host= _params) +{ + struct device_node *np =3D hba->dev->of_node; + u32 hs_gear, hs_rate; + + if (!np) + return; + + if (!of_property_read_u32(np, "limit-hs-gear", &hs_gear)) { + host_params->hs_tx_gear =3D hs_gear; + host_params->hs_rx_gear =3D hs_gear; + } + + if (!of_property_read_u32(np, "limit-rate", &hs_rate)) + host_params->hs_rate =3D hs_rate; +} +EXPORT_SYMBOL_GPL(ufshcd_parse_limits); + void ufshcd_init_host_params(struct ufs_host_params *host_params) { *host_params =3D (struct ufs_host_params){ diff --git a/drivers/ufs/host/ufshcd-pltfrm.h b/drivers/ufs/host/ufshcd-plt= frm.h index 3017f8e8f93c..1617f2541273 100644 --- a/drivers/ufs/host/ufshcd-pltfrm.h +++ b/drivers/ufs/host/ufshcd-pltfrm.h @@ -29,6 +29,7 @@ int ufshcd_negotiate_pwr_params(const struct ufs_host_par= ams *host_params, const struct ufs_pa_layer_attr *dev_max, struct ufs_pa_layer_attr *agreed_pwr); void ufshcd_init_host_params(struct ufs_host_params *host_params); +void ufshcd_parse_limits(struct ufs_hba *hba, struct ufs_host_params *host= _params); int ufshcd_pltfrm_init(struct platform_device *pdev, const struct ufs_hba_variant_ops *vops); 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charset="utf-8" Add support to limit Tx/Rx gear and rate during UFS initialization based on DT property. Also update the phy_gear to ensure PHY calibrations align with the required gear and rate. Signed-off-by: Ram Kumar Dwivedi --- drivers/ufs/host/ufs-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 1a93351fb70e..53c64d5fb95d 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1092,6 +1092,18 @@ static void ufs_qcom_set_phy_gear(struct ufs_qcom_ho= st *host) } } =20 +static void ufs_qcom_parse_limits(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + struct ufs_host_params *host_params =3D &host->host_params; + u32 hs_gear_old =3D host_params->hs_tx_gear; + + ufshcd_parse_limits(hba, host_params); + if (host_params->hs_tx_gear !=3D hs_gear_old) { + host->phy_gear =3D host_params->hs_tx_gear; + } +} + static void ufs_qcom_set_host_params(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); @@ -1333,6 +1345,7 @@ static int ufs_qcom_init(struct ufs_hba *hba) ufs_qcom_advertise_quirks(hba); ufs_qcom_set_host_params(hba); ufs_qcom_set_phy_gear(host); + ufs_qcom_parse_limits(hba); =20 err =3D ufs_qcom_ice_init(host); if (err) --=20 2.50.1