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MBa335x is an evaluation mainboard for this SOM. Signed-off-by: Matthias Schiffer Signed-off-by: Alexander Stein Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/ti/omap.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/omap.yaml b/Documenta= tion/devicetree/bindings/arm/ti/omap.yaml index aa5df4692e372..14f1b9d8f59d9 100644 --- a/Documentation/devicetree/bindings/arm/ti/omap.yaml +++ b/Documentation/devicetree/bindings/arm/ti/omap.yaml @@ -129,6 +129,13 @@ properties: - const: phytec,am335x-phycore-som - const: ti,am33xx =20 + - description: TQ-Systems TQMa335x[L] SoM + items: + - enum: + - tq,tqma3359-mba335x # MBa335x carrier board + - const: tq,tqma3359 + - const: ti,am33xx + - description: TI OMAP4430 SoC based platforms items: - enum: --=20 2.43.0 From nobody Fri Oct 3 20:29:58 2025 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3F5535207B; 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charset="utf-8" From: Matthias Schiffer Board Device Trees often want to set the cpu0-supply. Provide a label to reference the cpu@0 node. Signed-off-by: Matthias Schiffer Signed-off-by: Alexander Stein --- arch/arm/boot/dts/ti/omap/am33xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/am33xx.dtsi b/arch/arm/boot/dts/ti/o= map/am33xx.dtsi index 0614ffdc1578f..231c31074293e 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx.dtsi @@ -45,7 +45,7 @@ aliases { cpus { #address-cells =3D <1>; #size-cells =3D <0>; - cpu@0 { + cpu: cpu@0 { compatible =3D "arm,cortex-a8"; enable-method =3D "ti,am3352"; device_type =3D "cpu"; --=20 2.43.0 From nobody Fri Oct 3 20:29:58 2025 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC0A93568E4; Tue, 26 Aug 2025 14:09:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; 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charset="utf-8" From: Matthias Schiffer TQMa335x[L] is a SoM family using TI AM335x CPU family. MBa335x is an evaluation mainboard for this SoM. Signed-off-by: Matthias Schiffer Signed-off-by: Alexander Stein --- arch/arm/boot/dts/ti/omap/Makefile | 1 + arch/arm/boot/dts/ti/omap/am335x-mba335x.dts | 632 ++++++++++++++++++ .../arm/boot/dts/ti/omap/am335x-tqma335x.dtsi | 270 ++++++++ 3 files changed, 903 insertions(+) create mode 100644 arch/arm/boot/dts/ti/omap/am335x-mba335x.dts create mode 100644 arch/arm/boot/dts/ti/omap/am335x-tqma335x.dtsi diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap= /Makefile index 1aef60eef6718..14e500846875e 100644 --- a/arch/arm/boot/dts/ti/omap/Makefile +++ b/arch/arm/boot/dts/ti/omap/Makefile @@ -101,6 +101,7 @@ dtb-$(CONFIG_SOC_AM33XX) +=3D \ am335x-guardian.dtb \ am335x-icev2.dtb \ am335x-lxm.dtb \ + am335x-mba335x.dtb \ am335x-moxa-uc-2101.dtb \ am335x-moxa-uc-8100-me-t.dtb \ am335x-myirtech-myd.dtb \ diff --git a/arch/arm/boot/dts/ti/omap/am335x-mba335x.dts b/arch/arm/boot/d= ts/ti/omap/am335x-mba335x.dts new file mode 100644 index 0000000000000..e51a8a17e74c9 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-mba335x.dts @@ -0,0 +1,632 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2025 TQ-Systems GmbH , D-8222= 9 Seefeld, Germany. + * Authors: Gregor Herburger, Matthias Schiffer + * + * Based on: + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include +#include +#include "am335x-tqma335x.dtsi" + +/ { + model =3D "TQ-Systems TQMa335x[L] SoM on MBa335x carrier board"; + compatible =3D "tq,tqma3359-mba335x", "tq,tqma3359", "ti,am33xx"; + chassis-type =3D "embedded"; + + chosen { + stdout-path =3D &uart4; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 58 61 66 75 90 125 170 255>; + default-brightness-level =3D <7>; + enable-gpios =3D <&expander1 4 GPIO_ACTIVE_HIGH>; + power-supply =3D <®_mba335x_12v>; + status =3D "disabled"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + button-s5 { + label =3D "S5"; + linux,code =3D ; + gpios =3D <&expander2 0 GPIO_ACTIVE_LOW>; + }; + + button-s6 { + label =3D "S6"; + linux,code =3D ; + gpios =3D <&expander2 1 GPIO_ACTIVE_LOW>; + }; + + button-s7 { + label =3D "S7"; + linux,code =3D ; + gpios =3D <&expander2 2 GPIO_ACTIVE_LOW>; + }; + }; + + reg_mba335x_12v: regulator-12v { + compatible =3D "regulator-fixed"; + regulator-name =3D "MBa335x-V12"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-always-on; + }; + + vcc3v3: regulator-vcc3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VCC3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "tqm-tlv320aic32"; + simple-audio-card,widgets =3D + "Headphone", "Headphone Jack", + "Line", "Line In", + "Line", "Line Out", + "Microphone", "Mic Jack"; + simple-audio-card,routing =3D + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Line Out", "LOL", + "Line Out", "LOR", + "Mic Jack", "IN3_L", + "Line In", "IN1_L", + "Line In", "IN1_R"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,bitclock-master =3D <&sound_master>; + simple-audio-card,frame-master =3D <&sound_master>; + + simple-audio-card,cpu { + sound-dai =3D <&mcasp0>; + #sound-dai-cells =3D <0>; + system-clock-direction-out; + }; + + sound_master: simple-audio-card,codec { + sound-dai =3D <&tlv320aic32x4>; + system-clock-frequency =3D <24000000>; + system-clock-direction-out; + }; + }; +}; + +&am33xx_pinmux { + codec_pins: codec-pins { + pinctrl-single,pins =3D < + /* xdma_event_intr0.clkout1 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) + >; + }; + + cpsw_default_pins: cpsw-default-pins { + pinctrl-single,pins =3D < + /* Port 1 */ + /* mii1_tx_en.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_rx_dv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_tx_clk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_rx_clk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd0.rgmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) + + /* Port 2 */ + /* gpmc_a0.rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a1.rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a2.rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a3.rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a4.rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a5.rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a6.rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a7.rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a8.rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a9.rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a10.rgmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a11.rgmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) + >; + }; + + cpsw_sleep_pins: cpsw-sleep-pins { + pinctrl-single,pins =3D < + /* Port 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + + /* Port 2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default_pins: davinci_mdio-default-pins { + pinctrl-single,pins =3D < + /* mdio.mdio_data */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_M= ODE0) + /* mdc.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep_pins: davinci_mdio-sleep-pins { + pinctrl-single,pins =3D < + /* mdio.mdio_data */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP, MUX_MODE7) + /* mdc.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + davinci_mdio_phy0_pins: davinci_mdio-phy0-pins { + pinctrl-single,pins =3D < + /* usb0_drvvbus.gpio0_18 - PHY interrupt */ + AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_INPUT, MUX_MODE7) + >; + }; + + davinci_mdio_phy1_pins: davinci_mdio-phy1-pins { + pinctrl-single,pins =3D < + /* gpmc_csn0.gpio1_29 - PHY interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) + >; + }; + + dcan0_pins: dcan0-pins { + pinctrl-single,pins =3D < + /* uart1_ctsn.d_can0_tx */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* uart1_rtsn.d_can0_rx */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) + >; + }; + + dcan1_pins: dcan1-pins { + pinctrl-single,pins =3D < + /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* uart0_rtsn.d_can1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) + >; + }; + + ecap2_pins: ecap2-pins { + pinctrl-single,pins =3D < + /* mcasp0_ahclkr.ecap2_in_pwm2_out */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE4) + >; + }; + + expander1_pins: expander1-pins { + pinctrl-single,pins =3D < + /* /* gpmc_csn3.gpio2_0 - interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE7 ) + >; + }; + + expander2_pins: expander2-pins { + pinctrl-single,pins =3D < + /* /* gpmc_ben1.gpio1_28 - interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins =3D < + /* uart1_rxd.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE3) + /* uart1_txd.i2c1_scl */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE3) + >; + }; + + lcd_pins: lcd-pins { + pinctrl-single,pins =3D < + /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) + /* lcd_data0.lcd_data0 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + /* lcd_data1.lcd_data1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + /* lcd_data2.lcd_data2 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + /* lcd_data3.lcd_data3 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + /* lcd_data4.lcd_data4 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + /* lcd_data5.lcd_data5 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + /* lcd_data6.lcd_data6 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + /* lcd_data7.lcd_data7 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + /* lcd_data8.lcd_data8 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + /* lcd_data9.lcd_data9 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + /* lcd_data10.lcd_data10 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + /* lcd_data11.lcd_data11 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + /* lcd_data12.lcd_data12 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + /* lcd_data13.lcd_data13 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + /* lcd_data14.lcd_data14 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + /* lcd_data15.lcd_data15 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + /* lcd_vsync.lcd_vsync */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + /* lcd_hsync.lcd_hsync */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + /* lcd_pclk.lcd_pclk */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + >; + }; + + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins =3D < + /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_aclkx.mcasp0_aclkx*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_axr0.mcasp0_axr0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_axr1.mcasp0_axr1 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_aclkr.mcasp0_aclkr */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_fsr.mcasp0_fsr */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT_PULLDOWN, MUX_MODE0) + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins =3D < + /* mmc0_dat3.mmc0_dat3 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_dat2.mmc0_dat2 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_dat1.mmc0_dat1 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_dat0.mmc0_dat0 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_clk.mmc0_clk */ + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_cmd.mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + polytouch_pins: polytouch-pins { + pinctrl-single,pins =3D < + /* gpmc_clk.gpio2_1 - touch interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins =3D < + /* uart0_rxd.uart0_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins =3D < + /* spi0_cs1.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) + /* ecap0_in_pwm0_out.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_M= ODE1) + >; + }; + + uart4_pins: uart4-pins { + pinctrl-single,pins =3D < + /* gpmc_wait0.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) + /* gpmc_wpn.uart4_txd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) + >; + }; +}; + +&cpsw_port1 { + phy-handle =3D <ðphy0>; + phy-mode =3D "rgmii-id"; + ti,dual-emac-pvid =3D <1>; +}; + +&cpsw_port2 { + phy-handle =3D <ðphy1>; + phy-mode =3D "rgmii-id"; + ti,dual-emac-pvid =3D <2>; +}; + +&davinci_mdio_sw { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&davinci_mdio_default_pins>; + pinctrl-1 =3D <&davinci_mdio_sleep_pins>; + status =3D "okay"; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&davinci_mdio_phy0_pins>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <18 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-ps =3D <1860>; + rxd0-skew-ps =3D <0>; + rxd1-skew-ps =3D <0>; + rxd2-skew-ps =3D <0>; + rxd3-skew-ps =3D <0>; + rxdv-skew-ps =3D <0>; + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&davinci_mdio_phy1_pins>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <29 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-ps =3D <1860>; + rxd0-skew-ps =3D <0>; + rxd1-skew-ps =3D <0>; + rxd2-skew-ps =3D <0>; + rxd3-skew-ps =3D <0>; + rxdv-skew-ps =3D <0>; + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; + }; +}; + +&dcan0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dcan0_pins>; + status =3D "okay"; +}; + +&dcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dcan1_pins>; + status =3D "okay"; +}; + +&ds1339 { + interrupt-parent =3D <&expander2>; + interrupts =3D <3 IRQ_TYPE_EDGE_RISING>; +}; + +&ecap2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ecap2_pins>; +}; + +&i2c0 { + tlv320aic32x4: audio-codec@18 { + compatible =3D "ti,tlv320aic32x4"; + reg =3D <0x18>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&codec_pins>; + clocks =3D <&clk_24mhz>; + clock-names =3D "mclk"; + iov-supply =3D <&vcc3v3>; + ldoin-supply =3D <&vcc3v3>; + #sound-dai-cells =3D <0>; + }; + + jc42_2: temperature-sensor@19 { + compatible =3D "nxp,se97b", "jedec,jc-42.4-temp"; + reg =3D <0x19>; + }; + + expander1: gpio@20 { + compatible =3D "nxp,pca9554"; + reg =3D <0x20>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&expander1_pins>; + vcc-supply =3D <&vcc3v3>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio2>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + }; + + expander2: gpio@21 { + compatible =3D "nxp,pca9554"; + reg =3D <0x21>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&expander2_pins>; + vcc-supply =3D <&vcc3v3>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <28 IRQ_TYPE_EDGE_FALLING>; + }; + + eeprom3: eeprom@51 { + compatible =3D "nxp,se97b", "atmel,24c02"; + reg =3D <0x51>; + pagesize =3D <16>; + vcc-supply =3D <&vcc3v3>; + }; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&lcdc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lcd_pins>; + blue-and-red-wiring =3D "crossed"; +}; + +&mac_sw { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&cpsw_default_pins>; + pinctrl-1 =3D <&cpsw_sleep_pins>; + status =3D "okay"; +}; + +&mcasp0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcasp0_pins>; + #sound-dai-cells =3D <0>; + op-mode =3D <0>; + tdm-slots =3D <2>; + /* 16 serializer */ + serial-dir =3D < /* 0: INACTIVE, 1: TX, 2: RX */ + 2 1 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt =3D <32>; + rx-num-evt =3D <32>; + status =3D "okay"; +}; + +&mmc1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc1_pins>; + vmmc-supply =3D <&vcc3v3>; + bus-width =3D <4>; + no-1-8-v; + no-mmc; + no-sdio; + status =3D "okay"; +}; + +&tps { + interrupt-parent =3D <&expander2>; + interrupts =3D <4 IRQ_TYPE_EDGE_RISING>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; + status =3D "okay"; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3_pins>; + status =3D "okay"; +}; + +&uart4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart4_pins>; + status =3D "okay"; +}; + +&usb0 { + dr_mode =3D "host"; +}; + +&usb1 { + /* Should be "otg", but role switching currently doesn't work */ + dr_mode =3D "peripheral"; +}; + +/* SOM supply */ +&vcc3v3in { + vin-supply =3D <&vcc3v3>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-tqma335x.dtsi b/arch/arm/boot= /dts/ti/omap/am335x-tqma335x.dtsi new file mode 100644 index 0000000000000..b75949f0f023a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-tqma335x.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2025 TQ-Systems GmbH , D-8222= 9 Seefeld, Germany. + * Authors: Gregor Herburger, Matthias Schiffer + * + * Based on: + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include "am33xx.dtsi" + +/ { + compatible =3D "tq,tqma3359", "ti,am33xx"; + + aliases { + mmc0 =3D &mmc2; + mmc1 =3D &mmc1; + /delete-property/ mmc2; + rtc0 =3D &tps; + rtc1 =3D &ds1339; + rtc2 =3D &rtc; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x10000000>; /* 256 MB */ + }; + + /* SOM input voltage */ + vcc3v3in: regulator-vcc3v3in { + compatible =3D "regulator-fixed"; + regulator-name =3D "VCC3V3IN"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + }; + + /* + * Regulator is enabled by PMIC power sequence. The supplied voltage + * rail is also usable on baseboard. + */ + vddshv: regulator-vddshv { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDDSHV"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + vin-supply =3D <&vcc3v3in>; + }; +}; + +&am33xx_pinmux { + i2c0_pins: i2c0-pins { + pinctrl-single,pins =3D < + /* i2c0_sda.i2c0_sda */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins =3D < + /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, M= UX_MODE1) + /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, M= UX_MODE1) + /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, M= UX_MODE1) + /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, M= UX_MODE1) + /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, M= UX_MODE1) + /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, M= UX_MODE1) + /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, M= UX_MODE1) + /* gpmc_ad7.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, M= UX_MODE1) + /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) + /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, = MUX_MODE2) + >; + }; + + spi0_pins: spi0-pins { + pinctrl-single,pins =3D < + /* spi0_sclk.spi0_sclk */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) + /* spi0_d0.spi0_d0 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* spi0_d1.spi0_d1 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE0) + /* spi0_cs0.spi0_cs0 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0) + >; + }; +}; + +&cpu { + cpu0-supply =3D <&vdd1_reg>; +}; + +&elm { + status =3D "okay"; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + clock-frequency =3D <100000>; + status =3D "okay"; + + /* optional, not on TQMa335xL */ + jc42_1: temperature-sensor@1f { + compatible =3D "nxp,se97b", "jedec,jc-42.4-temp"; + reg =3D <0x1f>; + }; + + tps: pmic@2d { + reg =3D <0x2d>; + ti,en-ck32k-xtal; + /* Filled in by tps65910.dtsi */ + }; + + /* optional, not on TQMa335xL */ + eeprom: eeprom@50 { + compatible =3D "st,24c64", "atmel,24c64"; + reg =3D <0x50>; + pagesize =3D <32>; + vcc-supply =3D <&vddshv>; + }; + + /* optional, not on TQMa335xL */ + se97btp: eeprom@57 { + compatible =3D "nxp,se97b", "atmel,24c02"; + reg =3D <0x57>; + pagesize =3D <16>; + vcc-supply =3D <&vddshv>; + }; + + /* optional, not on TQMa335xL */ + ds1339: rtc@68 { + compatible =3D "dallas,ds1339"; + reg =3D <0x68>; + }; +}; + +#include "../../tps65910.dtsi" + +&mmc2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc2_pins>; + bus-width =3D <8>; + no-1-8-v; + no-sd; + no-sdio; + vmmc-supply =3D <&vddshv>; + non-removable; + status =3D "okay"; +}; + +&rtc { + status =3D "disabled"; +}; + +&tps { + vcc1-supply =3D <&vcc3v3in>; + vcc2-supply =3D <&vcc3v3in>; + vcc3-supply =3D <&vcc3v3in>; + vcc4-supply =3D <&vcc3v3in>; + vcc5-supply =3D <&vcc3v3in>; + vcc6-supply =3D <&vcc3v3in>; + vcc7-supply =3D <&vcc3v3in>; + vccio-supply =3D <&vcc3v3in>; +}; + +/* TPS outputs */ +&vrtc_reg { + regulator-always-on; +}; + +&vio_reg { + regulator-always-on; +}; + +&vdd1_reg { + regulator-name =3D "vdd_mpu"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <1500000>; + regulator-boot-on; + regulator-always-on; +}; + +&vdd2_reg { + regulator-name =3D "vdd_core"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <1500000>; + regulator-boot-on; + regulator-always-on; +}; + +&vdd3_reg { + regulator-always-on; +}; + +&vdig1_reg { + regulator-always-on; +}; + +&vdig2_reg { + regulator-always-on; +}; + +&vpll_reg { + regulator-always-on; +}; + +&vdac_reg { + regulator-always-on; +}; + +&vaux1_reg { + regulator-always-on; +}; + +&vaux2_reg { + regulator-always-on; +}; + +&vaux33_reg { + regulator-always-on; +}; + +&vmmc_reg { + regulator-always-on; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-max-frequency =3D <24000000>; + vcc-supply =3D <&vddshv>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + }; +}; + +&usb0_phy { + vcc-supply =3D <&vaux1_reg>; +}; + +&usb1_phy { + vcc-supply =3D <&vaux1_reg>; +}; + +&wkup_m3_ipc { + firmware-name =3D "am335x-evm-scale-data.bin"; +}; --=20 2.43.0 From nobody Fri Oct 3 20:29:58 2025 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C78E3353371; Tue, 26 Aug 2025 14:09:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756217371; cv=none; b=Tp7ZS3woK9pRJ56xjsQMs3uFN+jIu1FSjKu1bvd3pwn7ZLoxUXrC9IMhrmE7h0e/TJM8XbGhetbdOdr3bEAgTXOtKJ4GsIcGI6o/6QjZx++3OR6PkF+KJbxs8p4wBKfGRoYfQeTGEEYdiLZCiL1QSaDBhJ/p6cqxmFN9/RBr4rc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756217371; c=relaxed/simple; bh=VxxAn9TFOpcsguCx9K7fewvhM/0wUPUfrJxjMbCBnWM=; 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Tue, 26 Aug 2025 16:09:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1756217362; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=po8HbtbKHvoyjA3ItsX05bpzUQlEqnSkxM1AR2Md81M=; b=RSjV5kNkAMiu1Sv9U+xzryHRAsHT8WpvwmvPPWcFgGysiN82GSAZG4OaHxRxJSC0zQnRIQ Qor+Ps04LuLoIk9isDJk5CtYg/dvCvOHUR2M9ns9ieQYaKIOfsfl72Ztrmmv/6Sf2y0tok e+g8YCWEYwIT9kLsWEDo3UAXFdAUPdb+K9V8ha3xoTy/l6z0kaMaZFm1TMc00H7cKli+nS 9XAzag8BXm+W0gh4yY+7tTrXEDVy1TkUMB/dryY2U0YUQKFHN1A5ARa7uKDoe+JYCqpTWs W6GMduz4Hy7c5y9KXKMX99nQnwzBEwtWIsUxH1xKK1n9Aq6jC56urd1kLno1TA== From: Alexander Stein To: Aaro Koskinen , Andreas Kemnade , Kevin Hilman , Roger Quadros , Tony Lindgren , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Alexander Stein , linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com Subject: [PATCH 4/4] MAINTAINERS: Add entry for TQ-Systems AM335 device trees Date: Tue, 26 Aug 2025 16:08:50 +0200 Message-ID: <20250826140853.2570528-5-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250826140853.2570528-1-alexander.stein@ew.tq-group.com> References: <20250826140853.2570528-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" This includes the TQMa335x series and the corresponding mainboard MBa335x. Signed-off-by: Alexander Stein --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0110a497a19fa..3976bf909c0c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25667,6 +25667,8 @@ S: Supported W: https://www.tq-group.com/en/products/tq-embedded/ F: arch/arm/boot/dts/nxp/imx/*mba*.dts* F: arch/arm/boot/dts/nxp/imx/*tqma*.dts* +F: arch/arm/boot/dts/ti/omap/*mba*.dts* +F: arch/arm/boot/dts/ti/omap/*tqma*.dts* F: arch/arm64/boot/dts/freescale/fsl-*tqml*.dts* F: arch/arm64/boot/dts/freescale/imx*mba*.dts* F: arch/arm64/boot/dts/freescale/imx*tqma*.dts* --=20 2.43.0