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Tue, 26 Aug 2025 04:42:56 -0700 (PDT) From: Anand Moon To: Shawn Guo , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR HISILICON STB), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v1 1/2] PCI: dwc: histb: Simplify clock handling by using clk_bulk*() functions Date: Tue, 26 Aug 2025 17:12:40 +0530 Message-ID: <20250826114245.112472-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250826114245.112472-1-linux.amoon@gmail.com> References: <20250826114245.112472-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the driver acquires clocks and prepare/enable/disable/unprepare the clocks individually thereby making the driver complex to read. The driver can be simplified by using the clk_bulk*() APIs. Use: - devm_clk_bulk_get_all() API to acquire all the clocks - clk_bulk_prepare_enable() to prepare/enable clocks - clk_bulk_disable_unprepare() APIs to disable/unprepare them in bulk Signed-off-by: Anand Moon --- drivers/pci/controller/dwc/pcie-histb.c | 70 ++++--------------------- 1 file changed, 11 insertions(+), 59 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controll= er/dwc/pcie-histb.c index a52071589377..4022349e85d2 100644 --- a/drivers/pci/controller/dwc/pcie-histb.c +++ b/drivers/pci/controller/dwc/pcie-histb.c @@ -51,10 +51,8 @@ =20 struct histb_pcie { struct dw_pcie *pci; - struct clk *aux_clk; - struct clk *pipe_clk; - struct clk *sys_clk; - struct clk *bus_clk; + struct clk_bulk_data *clks; + int num_clks; struct phy *phy; struct reset_control *soft_reset; struct reset_control *sys_reset; @@ -204,10 +202,7 @@ static void histb_pcie_host_disable(struct histb_pcie = *hipcie) reset_control_assert(hipcie->sys_reset); reset_control_assert(hipcie->bus_reset); =20 - clk_disable_unprepare(hipcie->aux_clk); - clk_disable_unprepare(hipcie->pipe_clk); - clk_disable_unprepare(hipcie->sys_clk); - clk_disable_unprepare(hipcie->bus_clk); + clk_bulk_disable_unprepare(hipcie->num_clks, hipcie->clks); =20 if (hipcie->reset_gpio) gpiod_set_value_cansleep(hipcie->reset_gpio, 1); @@ -235,28 +230,10 @@ static int histb_pcie_host_enable(struct dw_pcie_rp *= pp) if (hipcie->reset_gpio) gpiod_set_value_cansleep(hipcie->reset_gpio, 0); =20 - ret =3D clk_prepare_enable(hipcie->bus_clk); + ret =3D clk_bulk_prepare_enable(hipcie->num_clks, hipcie->clks); if (ret) { - dev_err(dev, "cannot prepare/enable bus clk\n"); - goto err_bus_clk; - } - - ret =3D clk_prepare_enable(hipcie->sys_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable sys clk\n"); - goto err_sys_clk; - } - - ret =3D clk_prepare_enable(hipcie->pipe_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable pipe clk\n"); - goto err_pipe_clk; - } - - ret =3D clk_prepare_enable(hipcie->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clk\n"); - goto err_aux_clk; + ret =3D dev_err_probe(dev, ret, "failed to enable clocks\n"); + goto reg_dis; } =20 reset_control_assert(hipcie->soft_reset); @@ -270,13 +247,7 @@ static int histb_pcie_host_enable(struct dw_pcie_rp *p= p) =20 return 0; =20 -err_aux_clk: - clk_disable_unprepare(hipcie->pipe_clk); -err_pipe_clk: - clk_disable_unprepare(hipcie->sys_clk); -err_sys_clk: - clk_disable_unprepare(hipcie->bus_clk); -err_bus_clk: +reg_dis: if (hipcie->vpcie) regulator_disable(hipcie->vpcie); =20 @@ -345,29 +316,10 @@ static int histb_pcie_probe(struct platform_device *p= dev) return ret; } =20 - hipcie->aux_clk =3D devm_clk_get(dev, "aux"); - if (IS_ERR(hipcie->aux_clk)) { - dev_err(dev, "Failed to get PCIe aux clk\n"); - return PTR_ERR(hipcie->aux_clk); - } - - hipcie->pipe_clk =3D devm_clk_get(dev, "pipe"); - if (IS_ERR(hipcie->pipe_clk)) { - dev_err(dev, "Failed to get PCIe pipe clk\n"); - return PTR_ERR(hipcie->pipe_clk); - } - - hipcie->sys_clk =3D devm_clk_get(dev, "sys"); - if (IS_ERR(hipcie->sys_clk)) { - dev_err(dev, "Failed to get PCIEe sys clk\n"); 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Tue, 26 Aug 2025 04:43:02 -0700 (PDT) Received: from rockpi-5b ([45.112.0.216]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4a8b7b301csm5612958a12.35.2025.08.26.04.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 04:43:01 -0700 (PDT) From: Anand Moon To: Shawn Guo , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR HISILICON STB), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v1 2/2] PCI: dwc: histb: Simplify reset control handling by using reset_control_bulk*() function Date: Tue, 26 Aug 2025 17:12:41 +0530 Message-ID: <20250826114245.112472-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250826114245.112472-1-linux.amoon@gmail.com> References: <20250826114245.112472-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the driver acquires and asserts/deasserts the resets individually thereby making the driver complex to read. This can be simplified by using the reset_control_bulk() APIs. Use devm_reset_control_bulk_get_exclusive() API to acquire all the resets and use reset_control_bulk_{assert/deassert}() APIs to assert/deassert them in bulk. Signed-off-by: Anand Moon Reviewed-by: Philipp Zabel --- drivers/pci/controller/dwc/pcie-histb.c | 57 ++++++++++++------------- 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controll= er/dwc/pcie-histb.c index 4022349e85d2..4ba5c9af63a0 100644 --- a/drivers/pci/controller/dwc/pcie-histb.c +++ b/drivers/pci/controller/dwc/pcie-histb.c @@ -49,14 +49,20 @@ #define PCIE_LTSSM_STATE_MASK GENMASK(5, 0) #define PCIE_LTSSM_STATE_ACTIVE 0x11 =20 +#define PCIE_HISTB_NUM_RESETS ARRAY_SIZE(histb_pci_rsts) + +static const char * const histb_pci_rsts[] =3D { + "soft", + "sys", + "bus", +}; + struct histb_pcie { struct dw_pcie *pci; struct clk_bulk_data *clks; int num_clks; struct phy *phy; - struct reset_control *soft_reset; - struct reset_control *sys_reset; - struct reset_control *bus_reset; + struct reset_control_bulk_data reset[PCIE_HISTB_NUM_RESETS]; void __iomem *ctrl; struct gpio_desc *reset_gpio; struct regulator *vpcie; @@ -198,9 +204,8 @@ static const struct dw_pcie_host_ops histb_pcie_host_op= s =3D { =20 static void histb_pcie_host_disable(struct histb_pcie *hipcie) { - reset_control_assert(hipcie->soft_reset); - reset_control_assert(hipcie->sys_reset); - reset_control_assert(hipcie->bus_reset); + reset_control_bulk_assert(PCIE_HISTB_NUM_RESETS, + hipcie->reset); =20 clk_bulk_disable_unprepare(hipcie->num_clks, hipcie->clks); =20 @@ -236,14 +241,19 @@ static int histb_pcie_host_enable(struct dw_pcie_rp *= pp) goto reg_dis; } =20 - reset_control_assert(hipcie->soft_reset); - reset_control_deassert(hipcie->soft_reset); - - reset_control_assert(hipcie->sys_reset); - reset_control_deassert(hipcie->sys_reset); + ret =3D reset_control_bulk_assert(PCIE_HISTB_NUM_RESETS, + hipcie->reset); + if (ret) { + dev_err(dev, "Couldn't assert reset %d\n", ret); + goto reg_dis; + } =20 - reset_control_assert(hipcie->bus_reset); - reset_control_deassert(hipcie->bus_reset); + ret =3D reset_control_bulk_deassert(PCIE_HISTB_NUM_RESETS, + hipcie->reset); + if (ret) { + dev_err(dev, "Couldn't dessert reset %d\n", ret); + goto reg_dis; + } =20 return 0; =20 @@ -321,23 +331,12 @@ static int histb_pcie_probe(struct platform_device *p= dev) return dev_err_probe(dev, hipcie->num_clks, "failed to get clocks\n"); =20 - hipcie->soft_reset =3D devm_reset_control_get(dev, "soft"); - if (IS_ERR(hipcie->soft_reset)) { - dev_err(dev, "couldn't get soft reset\n"); - return PTR_ERR(hipcie->soft_reset); - } + ret =3D devm_reset_control_bulk_get_exclusive(dev, + PCIE_HISTB_NUM_RESETS, + hipcie->reset); + if (ret) + return dev_err_probe(dev, ret, "Cannot get the Core resets\n"); =20 - hipcie->sys_reset =3D devm_reset_control_get(dev, "sys"); - if (IS_ERR(hipcie->sys_reset)) { - dev_err(dev, "couldn't get sys reset\n"); - return PTR_ERR(hipcie->sys_reset); - } - - hipcie->bus_reset =3D devm_reset_control_get(dev, "bus"); - if (IS_ERR(hipcie->bus_reset)) { - dev_err(dev, "couldn't get bus reset\n"); - return PTR_ERR(hipcie->bus_reset); - } =20 hipcie->phy =3D devm_phy_get(dev, "phy"); if (IS_ERR(hipcie->phy)) { --=20 2.50.1