From nobody Fri Oct 3 20:26:55 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29BCB2F83AF; Tue, 26 Aug 2025 09:12:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756199546; cv=none; b=QevJMuApA/ktRb0g5UVhFU8ju6C/YVGDvBp08cZGeicuEhtv1RSGgoFGqkLNyXKOKzGU+c5xvK38kmqpmyrcg/EzezDwyp5vYoyvPCTevmyaRmAe18Fc6cUfiGiBIZE3cZ0GgJ60x/ODET9Q4vCuONxV9ga8Y0cesvwlVQHD+KY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756199546; c=relaxed/simple; bh=WbkmVPjjSGySwhfNslMb4+0ZFydn2v0MxujT8omDxos=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V/jfng6rLv5nxkrWdru2ItzUU3iQuo3z/j8oT+GzJUYW/Lg4zFGDrYIA4jAb9PwKKOXa/dbCRDxTN1qUW/qXbpOPd0d1Rx++wFn823b3nVuVk4vuqEi05MZkEkbdlrf37k2jtjAwf+O8H6RyAkNhm6khvRYZQQTuy6RG7pL9NcQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=H4bf4aQI; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="H4bf4aQI" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57Q983HY026007; Tue, 26 Aug 2025 09:12:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=qSkBE2nL6TC 1NPTiqr4dygVDx+HUcoUfXChqJhvX6GM=; b=H4bf4aQIf7PyG5KnWgMhc13rzn3 H4lc/YScntEIZTzf1MLQr7USEnGrmExj6NnFF6p4x1wIJsDWkI5P04CwuXivze+M 7p/745bFmsKFbcMaBzJ/JAyFUp3rH9rVgSWTxEQRJ3PhfaBqVYhyL8EmuywDSri1 q0iKrY2peSmldnvH3OPiqDdbiVrWZF+/fdWPFPPb63YRQlhLhk5SBd7NnyVOI/a7 KHNQZ17wxzXA71yVERS6KQnBfpyerWgEYIY92xeVQLTNjsHY1U1BkEXkIcsfK22X D00/f7tiikOCoHUhU4tH7OAuNb3CK5ld4jfiYZ6sNnTety/HK1whLOIShwA== Received: from aptaippmta02.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com [103.229.16.4]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48s2euhan5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Aug 2025 09:12:14 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 57Q9CBG5017663; Tue, 26 Aug 2025 09:12:11 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 48q6qksts3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Aug 2025 09:12:11 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 57Q9CB06017647; Tue, 26 Aug 2025 09:12:11 GMT Received: from ziyuzhan-gv.ap.qualcomm.com (ziyuzhan-gv.qualcomm.com [10.64.66.102]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 57Q9CAXD017642 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Aug 2025 09:12:11 +0000 Received: by ziyuzhan-gv.ap.qualcomm.com (Postfix, from userid 4438065) id 981C6526; Tue, 26 Aug 2025 17:12:09 +0800 (CST) From: Ziyue Zhang To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang , Konrad Dybcio , Manivannan Sadhasivam Subject: [PATCH v11 4/5] arm64: dts: qcom: qcs8300: enable pcie1 Date: Tue, 26 Aug 2025 17:12:04 +0800 Message-ID: <20250826091205.3625138-5-ziyue.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250826091205.3625138-1-ziyue.zhang@oss.qualcomm.com> References: <20250826091205.3625138-1-ziyue.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hecuo4i7QFt8PKfBu5lnAqCbr4ZhpOZg X-Proofpoint-GUID: hecuo4i7QFt8PKfBu5lnAqCbr4ZhpOZg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODI2MDAwMSBTYWx0ZWRfX+SHe+kagSjr8 8gSOGy9LVybfktfqni0cf+wkjacKT8hRATaMTQqbj93COZaf5/YQEsmrYbedBvtbVTg6aa/MkXs VW1jmYIUmK0LvFJ5q40nNJktCUmT4lE7hLHJ6adY967BZfbSJhP2vfxr9DuWtD5N7xHArOxR5YO KvXRgKz1pjSAAa9am762QZRCu8wK+nKftxc3uWKl0/rOOOYlE4DiV+PhCS/2/J2WzvhqIT/wKBA 6cYtvMNKWr7X5zaEMNmCZWMoAXWf6MY9kXgG4WukqusGk4Yh3LVNZvro602n422B5eowF8r3vjA gTKejI2mj5V3bb7ta8hjUHfxbTPFLBN+kJIOZ8dVU2yHZ/zUs6Oi+lUBm44fUKCowypCRPd8F4i SBe3h+2j X-Authority-Analysis: v=2.4 cv=PJUP+eqC c=1 sm=1 tr=0 ts=68ad7a6e cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=K7kricVwaqq8vgrxYV0A:9 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 spamscore=0 adultscore=0 clxscore=1015 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508260001 Content-Type: text/plain; charset="utf-8" Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s. Acked-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 131 +++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index a64890033ef1..3c5d5af1a691 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -903,7 +903,7 @@ gcc: clock-controller@100000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <0>, + <&pcie1_phy>, <0>, <0>, <0>, @@ -2426,6 +2426,135 @@ pcie0_phy: phy@1c04000 { status =3D "disabled"; }; =20 + pcie1: pci@1c10000 { + device_type =3D "pci"; + compatible =3D "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <1>; + num-lanes =3D <4>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_1_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcieport1: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie1_phy>; + }; + }; + + pcie1_phy: phy@1c14000 { + compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg =3D <0x0 0x01c14000 0x0 0x4000>; + + clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names =3D "phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie_1_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + ufs_mem_hc: ufs@1d84000 { compatible =3D "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg =3D <0x0 0x01d84000 0x0 0x3000>; --=20 2.43.0