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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Aug 2025 08:33:25.3680 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5b082c7-d69a-47d4-8c53-08dde47b3999 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6363 Content-Type: text/plain; charset="utf-8" Add support for SW mutex register introduced in Tegra264 to provide an option to share the interface between multiple firmwares and/or VMs. However, the hardware does not ensure any protection based on the values. The driver/firmware should honor the peer who already holds the mutex. Signed-off-by: Kartik Rajput Signed-off-by: Akhil R --- v3 -> v4: * Update timeout logic of tegra_i2c_mutex_lock() to use read_poll_timeout APIs for improving timeout logic. * Add tegra_i2c_mutex_acquired() to check if mutex is acquired or not. * Rename I2C_SW_MUTEX_ID as I2C_SW_MUTEX_ID_CCPLEX. * Function tegra_i2c_poll_register() was moved unnecessarily, it has now been moved to its original location. * Use tegra_i2c_mutex_lock/unlock APIs in the tegra_i2c_xfer() function. This ensures proper propagation of error in case mutex lock fails. Please note that as the function tegra_i2c_xfer() is already guarded by the bus lock operation there is no need of additional lock for the tegra_i2c_mutex_lock/unlock APIs. v2 -> v3: * Update tegra_i2c_mutex_trylock and tegra_i2c_mutex_unlock to use readl and writel APIs instead of i2c_readl and i2c_writel which use relaxed APIs. * Use dev_warn instead of WARN_ON if mutex lock/unlock fails. v1 -> v2: * Fixed typos. * Fix tegra_i2c_mutex_lock() logic. * Add a timeout in tegra_i2c_mutex_lock() instead of polling for mutex indefinitely. --- drivers/i2c/busses/i2c-tegra.c | 92 ++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 20d5c8a6925d..aae1645dfd92 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -137,6 +137,14 @@ =20 #define I2C_MASTER_RESET_CNTRL 0x0a8 =20 +#define I2C_SW_MUTEX 0x0ec +#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0) +#define I2C_SW_MUTEX_GRANT GENMASK(7, 4) +#define I2C_SW_MUTEX_ID_CCPLEX 9 + +/* SW mutex acquire timeout value in microseconds. */ +#define I2C_SW_MUTEX_TIMEOUT_US (25 * USEC_PER_MSEC) + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 =20 @@ -210,6 +218,7 @@ enum msg_end_type { * @has_interface_timing_reg: Has interface timing register to program the= tuned * timing settings. * @has_hs_mode_support: Has support for high speed (HS) mode transfers. + * @has_mutex: Has mutex register for mutual exclusion with other firmware= s or VMs. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -237,6 +246,7 @@ struct tegra_i2c_hw_feature { u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; bool has_hs_mode_support; + bool has_mutex; }; =20 /** @@ -381,6 +391,73 @@ static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, = void *data, readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); } =20 +static int tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val =3D readl(i2c_dev->base + reg); + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + + if (id !=3D I2C_SW_MUTEX_ID_CCPLEX) + return 0; + + return 1; +} + +static int tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val =3D readl(i2c_dev->base + reg); + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id !=3D 0 && id !=3D I2C_SW_MUTEX_ID_CCPLEX) + return 0; + + val =3D FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX); + writel(val, i2c_dev->base + reg); + + return tegra_i2c_mutex_acquired(i2c_dev); +} + +static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev) +{ + int locked; + int ret; + + if (i2c_dev->atomic_mode) + ret =3D read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked, + USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US, + false, i2c_dev); + else + ret =3D read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_= PER_MSEC, + I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev); + + if (!tegra_i2c_mutex_acquired(i2c_dev)) + dev_warn(i2c_dev->dev, "failed to acquire mutex\n"); + + return ret; +} + +static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val =3D readl(i2c_dev->base + reg); + + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id && id !=3D I2C_SW_MUTEX_ID_CCPLEX) { + dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n"= , id); + return -EPERM; + } + + writel(0, i2c_dev->base + reg); + + return 0; +} + static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) { u32 int_mask; @@ -1422,6 +1499,10 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, = struct i2c_msg msgs[], return ret; } =20 + ret =3D tegra_i2c_mutex_lock(i2c_dev); + if (ret) + return ret; + for (i =3D 0; i < num; i++) { enum msg_end_type end_type =3D MSG_END_STOP; =20 @@ -1451,6 +1532,10 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, = struct i2c_msg msgs[], break; } =20 + ret =3D tegra_i2c_mutex_unlock(i2c_dev); + if (ret) + return ret; + pm_runtime_put(i2c_dev->dev); =20 return ret ?: i; @@ -1527,6 +1612,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_= hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra30_i2c_hw =3D { @@ -1553,6 +1639,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1579,6 +1666,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1605,6 +1693,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1631,6 +1720,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra186_i2c_hw =3D { @@ -1657,6 +1747,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra194_i2c_hw =3D { @@ -1685,6 +1776,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D true, + .has_mutex =3D false, }; =20 static const struct of_device_id tegra_i2c_of_match[] =3D { --=20 2.43.0