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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-770b5bed428sm5628582b3a.16.2025.08.26.00.01.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 00:01:59 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v1 1/3] coresight: tpda: Add sysfs node for tpda cross-trigger configuration Date: Tue, 26 Aug 2025 15:01:48 +0800 Message-Id: <20250826070150.5603-2-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250826070150.5603-1-jie.gan@oss.qualcomm.com> References: <20250826070150.5603-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Z/vsHGRA c=1 sm=1 tr=0 ts=68ad5be9 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=Hl4cRc3ft4hpfJdQRooA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfX90N6kQzmtoVd OoHLk9W51jG/PmRvx3p13E8hcCoFKp37w1rCJyF/9jzYGW58H83G9h4gxvTJbZu7WRuWFTSVZDA TgItF6LAL4KZwy6yZZZ7N/2mRZXOh7RdYy9/mozJY5hCx305YKZCniY5YEbkC4rsONYUVRdYqmL KSUYWGNqzEQ/STehzq7d469DFL4WzTCedrQdz2N/qY6xrRQQDsKi10lNwKdonYA/XG5eeud1zGF c27KzFHLO2ihMq85uq9KhPOkKGbQB9Ez1NWQ8UnJLsnFRI+DSov2ZJyX3u8yqE3FfumwBB4RTmo iYf037q6O/c8l9UtK3EbMO8Dslg7SCr8JYzbUTfC9rE3v34BcSDuDmjD9ozKEXh7h64IHFmhzpr o13hLORO X-Proofpoint-GUID: uFj9slStG_m809xnJjgTT8FZcgc7ZoVm X-Proofpoint-ORIG-GUID: uFj9slStG_m809xnJjgTT8FZcgc7ZoVm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 phishscore=0 clxscore=1015 suspectscore=0 impostorscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 Content-Type: text/plain; charset="utf-8" From: Tao Zhang Introduce sysfs nodes to configure cross-trigger parameters for TPDA. These registers define the characteristics of cross-trigger packets, including generation frequency and flag values. Signed-off-by: Tao Zhang Co-developed-by: Jie Gan Signed-off-by: Jie Gan --- .../testing/sysfs-bus-coresight-devices-tpda | 43 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 241 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 27 ++ 3 files changed, 311 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-t= pda diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-tpda new file mode 100644 index 000000000000..e827396a0fa1 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -0,0 +1,43 @@ +What: /sys/bus/coresight/devices//trig_async_enable +Date: August 2025 +KernelVersion: 6.17 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger synchronization sequence interface. + +What: /sys/bus/coresight/devices//trig_flag_ts_enable +Date: August 2025 +KernelVersion: 6.17 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger FLAG packet request interface. + +What: /sys/bus/coresight/devices//trig_freq_enable +Date: August 2025 +KernelVersion: 6.17 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger FREQ packet request interface. + +What: /sys/bus/coresight/devices//freq_ts_enable +Date: August 2025 +KernelVersion: 6.17 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable the timestamp for all FREQ packets. + +What: /sys/bus/coresight/devices//global_flush_req +Date: August 2025 +KernelVersion: 6.17 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Set/unset global (all ports) flush request bit. The bit remains set= until a + global flush request sequence completes. + +What: /sys/bus/coresight/devices//cmbchan_mode +Date: August 2025 +KernelVersion: 6.17 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Configure the CMB/MCMB channel mode for all enabled ports. + Value 0 means raw channel mapping mode. Value 1 means channel pair marki= ng mode. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index 4e93fa5bace4..cc254d53b8ec 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -156,9 +156,37 @@ static void tpda_enable_pre_port(struct tpda_drvdata *= drvdata) u32 val; =20 val =3D readl_relaxed(drvdata->base + TPDA_CR); + val &=3D ~TPDA_CR_MID; val &=3D ~TPDA_CR_ATID; val |=3D FIELD_PREP(TPDA_CR_ATID, drvdata->atid); + if (drvdata->trig_async) + val =3D val | TPDA_CR_SRIE; + else + val =3D val & ~TPDA_CR_SRIE; + if (drvdata->trig_flag_ts) + val =3D val | TPDA_CR_FLRIE; + else + val =3D val & ~TPDA_CR_FLRIE; + if (drvdata->trig_freq) + val =3D val | TPDA_CR_FRIE; + else + val =3D val & ~TPDA_CR_FRIE; + if (drvdata->freq_ts) + val =3D val | TPDA_CR_FREQTS; + else + val =3D val & ~TPDA_CR_FREQTS; + if (drvdata->cmbchan_mode) + val =3D val | TPDA_CR_CMBCHANMODE; + else + val =3D val & ~TPDA_CR_CMBCHANMODE; writel_relaxed(val, drvdata->base + TPDA_CR); + + /* + * If FLRIE bit is set, set the master and channel + * id as zero + */ + if (drvdata->trig_flag_ts) + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); } =20 static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) @@ -274,6 +302,217 @@ static const struct coresight_ops tpda_cs_ops =3D { .link_ops =3D &tpda_link_ops, }; =20 +static ssize_t trig_async_enable_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async); +} + +static ssize_t trig_async_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + if (val) + drvdata->trig_async =3D true; + else + drvdata->trig_async =3D false; + + return size; +} +static DEVICE_ATTR_RW(trig_async_enable); + +static ssize_t trig_flag_ts_enable_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_flag_ts); +} + +static ssize_t trig_flag_ts_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + if (val) + drvdata->trig_flag_ts =3D true; + else + drvdata->trig_flag_ts =3D false; + + return size; +} +static DEVICE_ATTR_RW(trig_flag_ts_enable); + +static ssize_t trig_freq_enable_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_freq); +} + +static ssize_t trig_freq_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + if (val) + drvdata->trig_freq =3D true; + else + drvdata->trig_freq =3D false; + + return size; +} +static DEVICE_ATTR_RW(trig_freq_enable); + +static ssize_t freq_ts_enable_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts); +} + +static ssize_t freq_ts_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + if (val) + drvdata->freq_ts =3D true; + else + drvdata->freq_ts =3D false; + + return size; +} +static DEVICE_ATTR_RW(freq_ts_enable); + +static ssize_t global_flush_req_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + guard(spinlock)(&drvdata->spinlock); + if (!drvdata->csdev->refcnt) + return -EPERM; + + val =3D readl_relaxed(drvdata->base + TPDA_CR); + return sysfs_emit(buf, "%lx\n", val); +} + +static ssize_t global_flush_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + if (!drvdata->csdev->refcnt) + return -EPERM; + + if (val) { + CS_UNLOCK(drvdata->base); + val =3D readl_relaxed(drvdata->base + TPDA_CR); + val =3D val | BIT(0); + writel_relaxed(val, drvdata->base + TPDA_CR); + CS_LOCK(drvdata->base); + } + + return size; +} +static DEVICE_ATTR_RW(global_flush_req); + +static ssize_t cmbchan_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode); +} + +static ssize_t cmbchan_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + bool val; + + if (kstrtobool(buf, &val)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + if (val) + drvdata->cmbchan_mode =3D true; + else + drvdata->cmbchan_mode =3D false; + + return size; +} +static DEVICE_ATTR_RW(cmbchan_mode); + +static struct attribute *tpda_attrs[] =3D { + &dev_attr_trig_async_enable.attr, + &dev_attr_trig_flag_ts_enable.attr, + &dev_attr_trig_freq_enable.attr, + &dev_attr_freq_ts_enable.attr, + &dev_attr_global_flush_req.attr, + &dev_attr_cmbchan_mode.attr, + NULL, +}; + +static struct attribute_group tpda_attr_grp =3D { + .attrs =3D tpda_attrs, +}; + +static const struct attribute_group *tpda_attr_grps[] =3D { + &tpda_attr_grp, + NULL, +}; + static int tpda_init_default_data(struct tpda_drvdata *drvdata) { int atid; @@ -289,6 +528,7 @@ static int tpda_init_default_data(struct tpda_drvdata *= drvdata) return atid; =20 drvdata->atid =3D atid; + drvdata->freq_ts =3D true; return 0; } =20 @@ -332,6 +572,7 @@ static int tpda_probe(struct amba_device *adev, const s= truct amba_id *id) desc.ops =3D &tpda_cs_ops; desc.pdata =3D adev->dev.platform_data; desc.dev =3D &adev->dev; + desc.groups =3D tpda_attr_grps; desc.access =3D CSDEV_ACCESS_IOMEM(base); drvdata->csdev =3D coresight_register(&desc); if (IS_ERR(drvdata->csdev)) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtraci= ng/coresight/coresight-tpda.h index c6af3d2da3ef..b651372d4c88 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -8,17 +8,34 @@ =20 #define TPDA_CR (0x000) #define TPDA_Pn_CR(n) (0x004 + (n * 4)) +#define TPDA_FPID_CR (0x084) + +/* Cross trigger FREQ packets timestamp bit */ +#define TPDA_CR_FREQTS BIT(2) +/* Cross trigger FREQ packet request bit */ +#define TPDA_CR_FRIE BIT(3) +/* Cross trigger FLAG packet request interface bit */ +#define TPDA_CR_FLRIE BIT(4) +/* Cross trigger synchronization bit */ +#define TPDA_CR_SRIE BIT(5) +/* Packetize CMB/MCMB traffic bit */ +#define TPDA_CR_CMBCHANMODE BIT(20) + /* Aggregator port enable bit */ #define TPDA_Pn_CR_ENA BIT(0) /* Aggregator port CMB data set element size bit */ #define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6) /* Aggregator port DSB data set element size bit */ #define TPDA_Pn_CR_DSBSIZE BIT(8) +/* Mode control bit */ +#define TPDA_MODE_CTRL BIT(12) =20 #define TPDA_MAX_INPORTS 32 =20 /* Bits 6 ~ 12 is for atid value */ #define TPDA_CR_ATID GENMASK(12, 6) +/* Bits 13 ~ 19 is for mid value */ +#define TPDA_CR_MID GENMASK(19, 13) =20 /** * struct tpda_drvdata - specifics associated to an TPDA component @@ -29,6 +46,11 @@ * @enable: enable status of the component. * @dsb_esize Record the DSB element size. * @cmb_esize Record the CMB element size. + * @trig_async: Enable/disable cross trigger synchronization sequence inte= rface. + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request interfa= ce. + * @trig_freq: Enable/disable cross trigger FREQ packet request interface. + * @freq_ts: Enable/disable the timestamp for all FREQ packets. + * @cmbchan_mode: Configure the CMB/MCMB channel mode. */ struct tpda_drvdata { void __iomem *base; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-770b5bed428sm5628582b3a.16.2025.08.26.00.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 00:02:02 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v1 2/3] coresight: tpda: add function to configure TPDA_SYNCR register Date: Tue, 26 Aug 2025 15:01:49 +0800 Message-Id: <20250826070150.5603-3-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250826070150.5603-1-jie.gan@oss.qualcomm.com> References: <20250826070150.5603-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfX6U3aEd3Lq0MX lTf7u13bx/HrS0g2hc4ijOoWvYUChkSird2Up+Bu+K0RhyyXHykgh7MNngHpyluD993EimykFri 5bJTpCwZIdLoOYFbUzq7zlKcugamwfn/DH3vq7FszFl6OzJEzgiAEiUBZSwBA7xG9xcH+s+0Mb4 8MfgfBonDKk2Hjgzr67nFFgJFw41AmTOA8paTgjap9UufIxaVBqTAhuhqVybKzSkl3obqK8ONSp 2IKoZ0/JDLq7oRXLknMTs03Jo5gfipoPy6oClAiswgOlIEsy+7xt6dIudYcp3/xFxE2mQGAfr+a ApDBGcgxEWA9xCUtD6c2yMVlk7VCKHGZbOn2U0h746gK1fGEpEvjSC00SZpjnC6s1i36bs73EL1 fM3AQPyD X-Proofpoint-GUID: zp93blGefTjX3fdQHiu8PHjalniUIQA2 X-Authority-Analysis: v=2.4 cv=MutS63ae c=1 sm=1 tr=0 ts=68ad5bed cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=8xtsYS7Ed2DtWhKBhe4A:9 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: zp93blGefTjX3fdQHiu8PHjalniUIQA2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 malwarescore=0 suspectscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 Content-Type: text/plain; charset="utf-8" From: Tao Zhang The TPDA_SYNCR register defines the frequency at which TPDA generates ASYNC packets, enabling userspace tools to accurately parse each valid packet. Signed-off-by: Tao Zhang Co-developed-by: Jie Gan Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tpda.c | 15 +++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index cc254d53b8ec..9e623732d1e7 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -189,6 +189,18 @@ static void tpda_enable_pre_port(struct tpda_drvdata *= drvdata) writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); } =20 +static void tpda_enable_post_port(struct tpda_drvdata *drvdata) +{ + uint32_t val; + + val =3D readl_relaxed(drvdata->base + TPDA_SYNCR); + /* Clear the mode */ + val =3D val & ~TPDA_MODE_CTRL; + /* Program the counter value */ + val =3D val | 0xFFF; + writel_relaxed(val, drvdata->base + TPDA_SYNCR); +} + static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) { u32 val; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-770b5bed428sm5628582b3a.16.2025.08.26.00.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 00:02:06 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v1 3/3] coresight: tpda: add sysfs node to flush specific port Date: Tue, 26 Aug 2025 15:01:50 +0800 Message-Id: <20250826070150.5603-4-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250826070150.5603-1-jie.gan@oss.qualcomm.com> References: <20250826070150.5603-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=KOlaDEFo c=1 sm=1 tr=0 ts=68ad5bf0 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=UsKUHg3HdU6Ygep39SEA:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: EfFwMngyCK64dvwk4NHRFBOQa0mYfFSd X-Proofpoint-ORIG-GUID: EfFwMngyCK64dvwk4NHRFBOQa0mYfFSd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfX5H3pGPovO3ci ljKg1pcgg5c2mgs2WZhbrO9wtkz35Ek/7KRJGa+K2xNySZL7LTz6wk+5ztM0paB9ym946Yfh/M1 1RCxuqbzUQv0WsRBWDPwaWCvjvAC6SBv/5rik61wNu59b6kC1m1bH17rpZ/9ooee4hU70X+fNx3 ipPaUmwqS6mMMFPSgl7mt8ZUkC5F+fLUJNSgRbMabwctBzh2GwGrN94Zxn1ceUkgXrJi5QHqiIK AI9hcrTS2YvIgkNOVMTN9wUnDNrtZU/y3DWONtxmk3fTzYgKSQP6l2i5QQ1jYIEYcjhdaIeDbWa rpJZY64OGe1SnJbwugM3rMM1mpj9ynyBPP8v78u+2aePMj4S7yPbzq4NT+T53udxqNgCjS5hS7O lBiOK+FI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 bulkscore=0 adultscore=0 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 Content-Type: text/plain; charset="utf-8" From: Tao Zhang Setting bit i in the TPDA_FLUSH_CR register initiates a flush request for port i, forcing the data to synchronize and be transmitted to the sink device. Signed-off-by: Tao Zhang Co-developed-by: Jie Gan Signed-off-by: Jie Gan --- .../testing/sysfs-bus-coresight-devices-tpda | 7 +++ drivers/hwtracing/coresight/coresight-tpda.c | 45 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 1 + 3 files changed, 53 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-tpda index e827396a0fa1..8803158ba42f 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -41,3 +41,10 @@ Contact: Jinlong Mao , Tao= Zhang /port_flush_req +Date: August 2025 +KernelVersion: 6.17 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Configure the bit i to requests a flush operation of port i on the = TPDA. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index 9e623732d1e7..c5f169facc51 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -509,6 +509,50 @@ static ssize_t cmbchan_mode_store(struct device *dev, } static DEVICE_ATTR_RW(cmbchan_mode); =20 +static ssize_t port_flush_req_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + guard(spinlock)(&drvdata->spinlock); + if (!drvdata->csdev->refcnt) + return -EPERM; + + val =3D readl_relaxed(drvdata->base + TPDA_FLUSH_CR); + return sysfs_emit(buf, "%lx\n", val); +} + +static ssize_t port_flush_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + /* The valid value ranges from 0 to 127 */ + if (val > 127) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + if (!drvdata->csdev->refcnt) + return -EPERM; + + if (val) { + CS_UNLOCK(drvdata->base); + writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); + CS_LOCK(drvdata->base); + } + + return size; +} +static DEVICE_ATTR_RW(port_flush_req); + static struct attribute *tpda_attrs[] =3D { &dev_attr_trig_async_enable.attr, &dev_attr_trig_flag_ts_enable.attr, @@ -516,6 +560,7 @@ static struct attribute *tpda_attrs[] =3D { &dev_attr_freq_ts_enable.attr, &dev_attr_global_flush_req.attr, &dev_attr_cmbchan_mode.attr, + &dev_attr_port_flush_req.attr, NULL, }; =20 diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtraci= ng/coresight/coresight-tpda.h index 00d146960d81..55a18d718357 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,7 @@ #define TPDA_Pn_CR(n) (0x004 + (n * 4)) #define TPDA_FPID_CR (0x084) #define TPDA_SYNCR (0x08C) +#define TPDA_FLUSH_CR (0x090) =20 /* Cross trigger FREQ packets timestamp bit */ #define TPDA_CR_FREQTS BIT(2) --=20 2.34.1