From nobody Fri Oct 3 21:05:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4257C221555; Tue, 26 Aug 2025 02:10:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756174212; cv=none; b=t1GWUrp1IWSG+06/5bYdtFjlVd9c4Zxx+5fg28WB9TRdv8y64eeB61njgb5d+1/QBfEqManxR5PakNFYhkS5PAdU8w+zFl7xIBK750tv8u3ntVjFcDnCVnRzXpm2v9ZJlMyG9pZ5aECs/l6txBIAbbN4934xc4Jg0ZmYeC160EM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756174212; c=relaxed/simple; bh=GlgpP4aSy/X3lcFsQSpchLxm7GsCiqdy3J2u9KSg5Xk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KqdBdz3utQOKJEUUrBL9S7LhtBPeW/sPNDHVPdsHotnc5pchv9m9F/mkWdx955v5/fpbMgQpdc3pfRFyHjsuYHoyARS4bTVke9HUpA5PH6vrgxnxWFYymclkT8aAsqPNQbv8U4Qd1nAX0t7OCrXj98J0W603AIS/OpkjGz+3bno= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SECtojZ5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SECtojZ5" Received: by smtp.kernel.org (Postfix) with ESMTPS id A347AC4CEF1; Tue, 26 Aug 2025 02:10:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756174211; bh=GlgpP4aSy/X3lcFsQSpchLxm7GsCiqdy3J2u9KSg5Xk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SECtojZ5SIi5CIPplOUtDz+Y+11qnwgrDVsaExgh9xezMWD7avO2OAl5LYyc/MDqm sA+VR5aZXPE0C5EZdHNKBEwNXM+9uAjHOQMAZZPBhLYnWO77VrnXZp5irWKKOXAhEv eribIYiGnY2aLj3PVBy7tuT2JoGj5DWPnFmb6BlgvMpCH7/fPyluAZkcVu2NuF0dtz rG9KvLvdqB1F6cr2TZLCe2Bv+TKs+sUINLTeThQYGzJ0Az9ZtBWpxlwkDiBpXDmesc PDuPACE0+yvAswwt7cDmTqGQS39U4CmpZHuaMtppONbmKPosk/y6Khb9teU/BCMtkM rGmv7JG9Jsa0g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EA1ACA0FE7; Tue, 26 Aug 2025 02:10:11 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Tue, 26 Aug 2025 10:10:09 +0800 Subject: [PATCH v3 1/3] spi: dt-bindings: add Amlogic A113L2 SFC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-spifc-v3-1-7e926041d7f6@amlogic.com> References: <20250826-spifc-v3-0-7e926041d7f6@amlogic.com> In-Reply-To: <20250826-spifc-v3-0-7e926041d7f6@amlogic.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liang Yang , Feng Chen Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756174209; l=2882; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=nMIimNuJem3Ad+WE57H9ayTye/RTSID7JvSbdPjhHgE=; b=SQqv+O/jv+z7GPwTBZKFS9gTdHrF7OkLVLWldB+3IIs0jIdORjnwmc2FtpawYj1yUlN7xnefa VQGV7vgjusFA3ivPHXfungy6Bki1jrnVTM10aDIBn/pMhdMCwOezDjP X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Feng Chen The Flash Controller is derived by adding an SPI path to the original raw NAND controller. This controller supports two modes: raw mode and SPI mode. The raw mode has already been implemented in the community, and the SPI mode is described here. Add bindings for Amlogic A113L2 SPI Flash Controller. Signed-off-by: Feng Chen Signed-off-by: Xianwei Zhao --- .../devicetree/bindings/spi/amlogic,a4-spifc.yaml | 82 ++++++++++++++++++= ++++ 1 file changed, 82 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml b/= Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml new file mode 100644 index 000000000000..80a89408a832 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/amlogic,a4-spifc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPI flash controller for Amlogic ARM SoCs + +maintainers: + - Liang Yang + - Feng Chen + - Xianwei Zhao + +description: + The Amlogic SPI flash controller is an extended version of the Amlogic N= AND + flash controller. It supports SPI Nor Flash and SPI NAND Flash(where the= Host + ECC HW engine could be enabled). + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: amlogic,a4-spifc + + reg: + maxItems: 1 + + clocks: + items: + - description: clock apb gate + - description: clock used for the controller + + clock-names: + items: + - const: gate + - const: core + + interrupts: + maxItems: 1 + + amlogic,rx-adj: + description: + Adjust sample timing for RX, Sampling time move later by 1 bus clock. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + sfc0: spi@fe08d000 { + compatible =3D "amlogic,a4-spifc"; + reg =3D <0xfe08d000 0x800>; + clocks =3D <&clkc_periphs 31>, + <&clkc_periphs 102>; + clock-names =3D "gate", "core"; + + pinctrl-0 =3D <&spiflash_default>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-ecc-engine =3D <&sfc0>; + nand-ecc-strength =3D <8>; + nand-ecc-step-size =3D <512>; + }; + }; --=20 2.37.1