From nobody Fri Oct 3 20:27:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0612D2F657A; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192718; cv=none; b=YcRiaHEOTRLWRJHB92gbUzMk9pAJOWwl7zFQX/LQ2rfruscExFzgqciE5G4Yr6y84FnYSmizNFjCB2NgZIKvuY5nGUWt96j6Ipk5xmPIESftYQhm5qdZpB6Y92ltfpihP8Y3csqtQxAG5D/oPZM/4zCjzQMDMoOCWG2zYcxJc4s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192718; c=relaxed/simple; bh=r3sY4ytaz+niwJh3RnoLADMn3LVz4c7xzRhnQ6L8M+k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QpbV70DTM+NtYhjkH7h43P6VignrVto0ec64yejkRsvssbb6HZ0UHmjwflL7ODyPd5RURER3p7RsaZZFf2zzAsVkGxhDiQE+vdQM7aSr2yuYZzN22exJ6/3wshsgpFJ4AQiVU6f00tHPdeGPs4FUgON6nhBBFJmpIVPobl+HWGk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MYVXftP/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MYVXftP/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 717D0C2BC86; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756192717; bh=r3sY4ytaz+niwJh3RnoLADMn3LVz4c7xzRhnQ6L8M+k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MYVXftP/ggG39anM0HdnuEVVSo6qB6bV/gCJUyUUBzExCfYLV2c+Q85Ive1eZ92aC wph5qg2BEINmOgJBhsIlE4R0GqmHuMKf0h8wMoKbXBWByvEOCsEDVVuOOkTQYAoFoB TPfM+wbTuH5s0EkV7DjNUSGI9nxjppHr96CClKAq4lQ8WUnXaRyPODccA6WkNAorK6 IB8U3sPf6uRt+Q2uDG5q0s9ayDyo1XjjIqp7huB9npkiSaPhABws4ew8TsDbo3n5yc 1ep9uhq/RS/XGndTfetf4/AWylxZmnGSRhM/IKyFex0HmtkP5Vno3NrTFjh1Zo4MaE Cd9GgsDEqCrxw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68949CA0FE9; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 26 Aug 2025 15:18:32 +0800 Subject: [PATCH v3 5/8] power: supply: qcom_battmgr: update compats for SM8550 and X1E80100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-qcom_battmgr_update-v3-5-74ea410ef146@oss.qualcomm.com> References: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> In-Reply-To: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> To: Sebastian Reichel , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , Dmitry Baryshkov , Bryan O'Donoghue , Konrad Dybcio Cc: Subbaraman Narayanamurthy , David Collins , =?utf-8?q?Gy=C3=B6rgy_Kurucz?= , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@oss.qualcomm.com, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756192715; l=1579; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=+qDRNAGRuy9qBxJBOT77eHOX4R2i3kyoPtbI3yzOFKI=; b=j+3uDWtnN6GirByhE5ARQmiAIBk8ASdKFTYiwe9Kj8mFEoFVVmtXMuqUXMLEjulIK5l00xEY1 F6AIT98DjtkAxdBkeq4Fd64MRjvhvtTsSO2vlZ2KtV+uNXhUXTbsX5e X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Add variant definitions for SM8550 and X1E80100 platforms. Add a compat for SM8550 and update match data for X1E80100 specifically so that they could be handled differently in supporting charge control functionality. Signed-off-by: Fenglin Wu --- drivers/power/supply/qcom_battmgr.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qco= m_battmgr.c index 008e241e3eac3574a78459a2256e006e48c9f508..174d3f83ac2b070bb90c21a4986= 86e91cc629ebe 100644 --- a/drivers/power/supply/qcom_battmgr.c +++ b/drivers/power/supply/qcom_battmgr.c @@ -19,8 +19,10 @@ #define BATTMGR_STRING_LEN 128 =20 enum qcom_battmgr_variant { - QCOM_BATTMGR_SM8350, QCOM_BATTMGR_SC8280XP, + QCOM_BATTMGR_SM8350, + QCOM_BATTMGR_SM8550, + QCOM_BATTMGR_X1E80100, }; =20 #define BATTMGR_BAT_STATUS 0x1 @@ -1333,7 +1335,8 @@ static void qcom_battmgr_pdr_notify(void *priv, int s= tate) static const struct of_device_id qcom_battmgr_of_variants[] =3D { { .compatible =3D "qcom,sc8180x-pmic-glink", .data =3D (void *)QCOM_BATTM= GR_SC8280XP }, { .compatible =3D "qcom,sc8280xp-pmic-glink", .data =3D (void *)QCOM_BATT= MGR_SC8280XP }, - { .compatible =3D "qcom,x1e80100-pmic-glink", .data =3D (void *)QCOM_BATT= MGR_SC8280XP }, + { .compatible =3D "qcom,sm8550-pmic-glink", .data =3D (void *)QCOM_BATTMG= R_SM8550 }, + { .compatible =3D "qcom,x1e80100-pmic-glink", .data =3D (void *)QCOM_BATT= MGR_X1E80100 }, /* Unmatched devices falls back to QCOM_BATTMGR_SM8350 */ {} }; --=20 2.34.1