From nobody Fri Oct 3 20:30:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A60E623C4FF; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192717; cv=none; b=k69/3IcPvOZYLtAoI2skLn7SAzAS0YpnSOblhqWmM74fc66ltFjvwtGFCPxRDq4eGpAEcahr937bafAj/T8KbzqRVMBD+M69NncVGCj6KC0/XX9C/hUIfn7k1YIw5ief2XJBIzaG/fgw+5DQUzwFOHckkC/sckggwofiYz3ZV/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192717; c=relaxed/simple; bh=NUKM72dsQsPVocfi0VrAIryfe6vjKQ5F2Pt17V7EWkc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JapDg/eHTWiZQK5rposCtHrAWT4aN58hep6XAqClKQYDXSvIndeTvwFBRNvzOnJV7eY3mYM+YEGe7sLhpOnwH53atxAYIgvdoUHykxMNfRnOUsOJ7nBx/bYWabSj6PJTWvLcmfz2YVpvYIOHo1UU0EvVmRxWH75vxU0no+GJCcY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bcq/DQT4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bcq/DQT4" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4A2DCC116B1; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756192717; bh=NUKM72dsQsPVocfi0VrAIryfe6vjKQ5F2Pt17V7EWkc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bcq/DQT4XuOQ8neh50cO8X+10jM07CnY1pyhf03XWcRL+8EwQ9S+Ch96a64tRS+gp laQmU96KAZJst7jYFyduJ1RRU7jmbU8lmZRWI872cnzz6KiKXpRS6lKeRrnsFQQPm6 NPuj2+1233Iegs99z/oJMTFM5g/XFwRznvccac7H+A7yq+am8tcnMXMlJBsgZIM2/M 33Yj3giT8I2Rsj5wUp2KPs9WxMPeQdtUapHprpxlAi1DV1EkGFhFWwsLed35U9ppO/ b3VcZjI367/V8/hqbVGsX71ojIMtuow3p3skj+SEWCTSbZZIjdlUKIgTYTMYAkJUiw s7fINKNaGST1w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30F43CA0EFA; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 26 Aug 2025 15:18:28 +0800 Subject: [PATCH v3 1/8] power: supply: core: Add resistance power supply property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-qcom_battmgr_update-v3-1-74ea410ef146@oss.qualcomm.com> References: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> In-Reply-To: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> To: Sebastian Reichel , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , Dmitry Baryshkov , Bryan O'Donoghue , Konrad Dybcio Cc: Subbaraman Narayanamurthy , David Collins , =?utf-8?q?Gy=C3=B6rgy_Kurucz?= , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@oss.qualcomm.com, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756192715; l=2838; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=PTxob4cVzRUR26yIMTWBec2QDLrpnnMTw9w6sqWmfeM=; b=vDJfRJYXvYAXw4lynpDhyRefJSwonykdYgRnQ2Q2FfWC0d4lKHKW2FI7M440YNbvibJsLRcoL lQEFnSpVfptAiMDlNbT0f4hqlQLfnjE4oMHxdWV4Zwdxj8H0uXpocJb X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Some battery drivers provide the ability to export internal resistance as a parameter. Add internal_resistance power supply property for that purpose. Signed-off-by: Fenglin Wu Tested-by: Neil Armstrong # on Thinkpad T14S OL= ED --- Documentation/ABI/testing/sysfs-class-power | 16 ++++++++++++++++ drivers/power/supply/power_supply_sysfs.c | 1 + include/linux/power_supply.h | 1 + 3 files changed, 18 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-class-power b/Documentation/AB= I/testing/sysfs-class-power index 560124cc31770cde03bcdbbba0d85a5bd78b15a0..cea1a38f5a8fb754d4e6323967e= f6cf2e20a68ce 100644 --- a/Documentation/ABI/testing/sysfs-class-power +++ b/Documentation/ABI/testing/sysfs-class-power @@ -552,6 +552,22 @@ Description: Integer > 0: representing full cycles Integer =3D 0: cycle_count info is not available =20 +What: /sys/class/power_supply//internal_resistance +Date: August 2025 +Contact: linux-arm-msm@vger.kernel.org +Description: + Represent the battery's internal resistance, often referred + to as Equivalent Series Resistance (ESR). It is a dynamic + parameter that reflects the opposition to current flow within + the cell. It is not a fixed value but varies significantly + based on several operational conditions, including battery + state of charge (SoC), temperature, and whether the battery + is in a charging or discharging state. + + Access: Read + + Valid values: Represented in microohms + **USB Properties** =20 What: /sys/class/power_supply//input_current_limit diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supp= ly/power_supply_sysfs.c index a438f7983d4f6a832e9d479184c7c35453e1757c..cfa8f90a88ebc8fc1c7447198f1= 38e5d2e699e5a 100644 --- a/drivers/power/supply/power_supply_sysfs.c +++ b/drivers/power/supply/power_supply_sysfs.c @@ -220,6 +220,7 @@ static struct power_supply_attr power_supply_attrs[] __= ro_after_init =3D { POWER_SUPPLY_ATTR(MANUFACTURE_YEAR), POWER_SUPPLY_ATTR(MANUFACTURE_MONTH), POWER_SUPPLY_ATTR(MANUFACTURE_DAY), + POWER_SUPPLY_ATTR(INTERNAL_RESISTANCE), /* Properties of type `const char *' */ POWER_SUPPLY_ATTR(MODEL_NAME), POWER_SUPPLY_ATTR(MANUFACTURER), diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index c4cb854971f53a244ba7742a15ce7a5515da6199..8bc3b7a67eb5693a16db9b7d123= e7881711c6bf4 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -174,6 +174,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_MANUFACTURE_YEAR, POWER_SUPPLY_PROP_MANUFACTURE_MONTH, POWER_SUPPLY_PROP_MANUFACTURE_DAY, + POWER_SUPPLY_PROP_INTERNAL_RESISTANCE, /* Properties of type `const char *' */ POWER_SUPPLY_PROP_MODEL_NAME, POWER_SUPPLY_PROP_MANUFACTURER, --=20 2.34.1 From nobody Fri Oct 3 20:30:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6D8E264F85; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192717; cv=none; b=KvoYPsZRFP7A4w9jf7RxwVfV971KP4RIwiaZ+pdRlXktuhQlgBoYD2YwsGHkqG2Ks4fpjqbRTGFMvwhyCE5CLtgX2XnoH+o7/znjtdCxpWzbjIiBhEuQz9VnICwaK0UbYnMFQAlI8iSiIUYtaYWGWrYKiis9SHSgkYjq8yp7ZVk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192717; c=relaxed/simple; bh=ws6SJdcKc3kyPrdCKKozPZCK/AOynWcUwJcuoVLAVzU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=T7qXnmlvyNIvPuCKgdR0XUDCOviCZSu+YVrCbiSf8dIvZK60xhziLd5WQGYKJKQP75KQ4CS+iZnpFjMJkwMkcaFkg2tiH8M8bf6OslHHWf4plhiwoVnYF9wWk9myTgXlAtWkYOgqPKacsk+iU8kj7VIPWkyDpcmBOdGQcGc0I5Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pokg6iFO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pokg6iFO" Received: by smtp.kernel.org (Postfix) with ESMTPS id 566EAC4CEF4; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756192717; bh=ws6SJdcKc3kyPrdCKKozPZCK/AOynWcUwJcuoVLAVzU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pokg6iFOP5Q26X7AXXCy7VnLhiOF5BZVV8ucCJPsiLv7nXvYi8YwxzcNA4LyOS/7z 4GQcG6l4rGYspNqw59LDUfzMJIxA0ghyzpCvzuxaSxtQ0+kU8VGX/3p94LDg5TxZ89 Idduhj4oCilyvpj9SBrhXzNCqa73/GglCI78Eq1DXCLC42Z6A2G/M5dhkNJj10iReW s5PNqgAV9uenuVMoQxlTpWkZ7vfSK2Ka9paU6drS9ur2GMLDs3o8BuxJncWkoHKPvO BZG/yYamBsQ2VPkA7THbYqxp0faacZrQG3FnHq0N1IAH3yzfofE93cS0gNog2bIjWv kUdUwZkFtnRoQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E197CA0FF0; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 26 Aug 2025 15:18:29 +0800 Subject: [PATCH v3 2/8] power: supply: core: Add state_of_health power supply property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-qcom_battmgr_update-v3-2-74ea410ef146@oss.qualcomm.com> References: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> In-Reply-To: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> To: Sebastian Reichel , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , Dmitry Baryshkov , Bryan O'Donoghue , Konrad Dybcio Cc: Subbaraman Narayanamurthy , David Collins , =?utf-8?q?Gy=C3=B6rgy_Kurucz?= , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@oss.qualcomm.com, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756192715; l=2652; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=RoS25nFVJl76zUEzPkYpvp8qPvjRe2//mJxGa0TPgJY=; b=8H/7E8QTWCiSp8Hx6ijyJyMdV7f51F5qEFZ6Z2gxHT2EptXAGs9AyJ1FltUjeUvIuNL0J+C28 /3V1Y00ona5CYcRS5aWR+91NmIljna7PovTftznmQt+KjboJvIJnSCK X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Add state_of_health power supply property to represent battery health percentage. Signed-off-by: Fenglin Wu Tested-by: Neil Armstrong # on Thinkpad T14S OL= ED --- Documentation/ABI/testing/sysfs-class-power | 15 +++++++++++++++ drivers/power/supply/power_supply_sysfs.c | 1 + include/linux/power_supply.h | 1 + 3 files changed, 17 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-class-power b/Documentation/AB= I/testing/sysfs-class-power index cea1a38f5a8fb754d4e6323967ef6cf2e20a68ce..04f82e3e33aad6e16dc4fbace06= 6b5d26069bf44 100644 --- a/Documentation/ABI/testing/sysfs-class-power +++ b/Documentation/ABI/testing/sysfs-class-power @@ -568,6 +568,21 @@ Description: =20 Valid values: Represented in microohms =20 +What: /sys/class/power_supply//state_of_health +Date: August 2025 +Contact: linux-arm-msm@vger.kernel.org +Description: + The state_of_health parameter quantifies the overall condition + of a battery as a percentage, reflecting its ability to deliver + rated performance relative to its original specifications. It is + dynamically computed using a combination of learned capacity + and impedance-based degradation indicators, both of which evolve + over the battery's lifecycle. + + Access: Read + + Valid values: 0 - 100 (percent) + **USB Properties** =20 What: /sys/class/power_supply//input_current_limit diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supp= ly/power_supply_sysfs.c index cfa8f90a88ebc8fc1c7447198f138e5d2e699e5a..d96a8578308e3af60cc1a352845= 662aa922c29b3 100644 --- a/drivers/power/supply/power_supply_sysfs.c +++ b/drivers/power/supply/power_supply_sysfs.c @@ -221,6 +221,7 @@ static struct power_supply_attr power_supply_attrs[] __= ro_after_init =3D { POWER_SUPPLY_ATTR(MANUFACTURE_MONTH), POWER_SUPPLY_ATTR(MANUFACTURE_DAY), POWER_SUPPLY_ATTR(INTERNAL_RESISTANCE), + POWER_SUPPLY_ATTR(STATE_OF_HEALTH), /* Properties of type `const char *' */ POWER_SUPPLY_ATTR(MODEL_NAME), POWER_SUPPLY_ATTR(MANUFACTURER), diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 8bc3b7a67eb5693a16db9b7d123e7881711c6bf4..ccb43fe44381965069dc3bd9505= d45050b9b1bd8 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -175,6 +175,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_MANUFACTURE_MONTH, POWER_SUPPLY_PROP_MANUFACTURE_DAY, POWER_SUPPLY_PROP_INTERNAL_RESISTANCE, + POWER_SUPPLY_PROP_STATE_OF_HEALTH, /* Properties of type `const char *' */ POWER_SUPPLY_PROP_MODEL_NAME, POWER_SUPPLY_PROP_MANUFACTURER, --=20 2.34.1 From nobody Fri Oct 3 20:30:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9084F17A2E1; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192717; cv=none; b=A13+bizRgoGZzMd346jLr08yyNq6ehIIkRgUd79+xogCJ80pmPM1WYdpoeafBCNI7aEDVk0XYAqhAJqX155oVURh2P+DJehdLGusmAYFwABEg8W1ANMMwks80D37AsZ9ThylmDxj4Nh8RPHUTrIisZacZbPwXE0X7ptSlpx/6jY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192717; c=relaxed/simple; bh=th/xW83aBeFoGO0hEkmPF1u8WTaW4iQP3V4pb7YIS3E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CfmYUsU/aDDVQiHoAS6HK4owiLX/7627U7proOtmPHnYZ829oJ12Qu2LjMQsXrxGp5AeuhxKCudk/bSroZCEzpn7eDlxyZAdMMfqY6y8ARVgRC6HkIXOW6dQ8xm35zeV4B+cT1CYWUbjCjPPVXc9sEjkoAe44iw2uALVvYgL91w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=T3WLIEZl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="T3WLIEZl" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5FD8EC4AF0C; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756192717; bh=th/xW83aBeFoGO0hEkmPF1u8WTaW4iQP3V4pb7YIS3E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=T3WLIEZltJNuYPW/xK4FBjaimp+Yn5DYp0Ppjrf7R2T0YI65E6mHN3dzOeUsO/ST1 bGRz5aVty+bisR3OK6PV972PLe9lHyDX6O8y+INkLjDBdlqRNqCAz9Riwc5SCjkcxq bNF3fCfDJNGnZpGq16v3tWpmdZI0Ku0qs97B8IOMqqT4TMu/DQyReNYuG8acBw1sWk HBFW4+ZdwX6GTVaF6oORxwWKrL9UXKpIqIOQO6wh2fzpmJQdShOr5Jj3Y72wJy+UUL CylE2NvlrTuStEU1dU5l5R5N+Ayyar38WEgZRTLHSo2F56/eeT19f0RnKhfU7QZaHO lyH38rdS90Hlg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AA37CA0FEB; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 26 Aug 2025 15:18:30 +0800 Subject: [PATCH v3 3/8] power: supply: qcom_battmgr: Add resistance power supply property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-qcom_battmgr_update-v3-3-74ea410ef146@oss.qualcomm.com> References: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> In-Reply-To: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> To: Sebastian Reichel , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , Dmitry Baryshkov , Bryan O'Donoghue , Konrad Dybcio Cc: Subbaraman Narayanamurthy , David Collins , =?utf-8?q?Gy=C3=B6rgy_Kurucz?= , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@oss.qualcomm.com, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756192715; l=2473; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=zi7yrMpAus4YPx9C7Vqz+BBGGIxG0pJ58Kd1/KkUxEk=; b=CGPIfUQGXSxWECziA/MijgMweL4PH+LcwC3O9EtYxiQEW5JF0pSXMZ9tsttAcqeNqz8mBfzos hbLS+gt0sLUCP4OJl475PPqHyByr9ZSLeVV1d+CfGmMIo3qK8Bg5ZjT X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Add power supply property to get battery internal resistance from the battery management firmware. Signed-off-by: Fenglin Wu Tested-by: Neil Armstrong # on Thinkpad T14S OL= ED --- drivers/power/supply/qcom_battmgr.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qco= m_battmgr.c index fe27676fbc7cd12292caa6fb3b5b46a18c426e6d..55477ae92fd56ede465b32d6f7e= d9da78ebd869c 100644 --- a/drivers/power/supply/qcom_battmgr.c +++ b/drivers/power/supply/qcom_battmgr.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2022, Linaro Ltd + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -254,6 +255,7 @@ struct qcom_battmgr_status { unsigned int voltage_now; unsigned int voltage_ocv; unsigned int temperature; + unsigned int resistance; =20 unsigned int discharge_time; unsigned int charge_time; @@ -418,6 +420,7 @@ static const u8 sm8350_bat_prop_map[] =3D { [POWER_SUPPLY_PROP_MODEL_NAME] =3D BATT_MODEL_NAME, [POWER_SUPPLY_PROP_TIME_TO_FULL_AVG] =3D BATT_TTF_AVG, [POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG] =3D BATT_TTE_AVG, + [POWER_SUPPLY_PROP_INTERNAL_RESISTANCE] =3D BATT_RESISTANCE, [POWER_SUPPLY_PROP_POWER_NOW] =3D BATT_POWER_NOW, }; =20 @@ -582,6 +585,9 @@ static int qcom_battmgr_bat_get_property(struct power_s= upply *psy, case POWER_SUPPLY_PROP_TEMP: val->intval =3D battmgr->status.temperature; break; + case POWER_SUPPLY_PROP_INTERNAL_RESISTANCE: + val->intval =3D battmgr->status.resistance; + break; case POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG: val->intval =3D battmgr->status.discharge_time; break; @@ -665,6 +671,7 @@ static const enum power_supply_property sm8350_bat_prop= s[] =3D { POWER_SUPPLY_PROP_MODEL_NAME, POWER_SUPPLY_PROP_TIME_TO_FULL_AVG, POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG, + POWER_SUPPLY_PROP_INTERNAL_RESISTANCE, POWER_SUPPLY_PROP_POWER_NOW, }; =20 @@ -1174,6 +1181,9 @@ static void qcom_battmgr_sm8350_callback(struct qcom_= battmgr *battmgr, case BATT_TTE_AVG: battmgr->status.discharge_time =3D le32_to_cpu(resp->intval.value); break; + case BATT_RESISTANCE: + battmgr->status.resistance =3D le32_to_cpu(resp->intval.value); + break; case BATT_POWER_NOW: battmgr->status.power_now =3D le32_to_cpu(resp->intval.value); break; --=20 2.34.1 From nobody Fri Oct 3 20:30:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6D24248869; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192717; cv=none; b=JbeuPTch0v4avqtjW7u3Odamic7zxnKO1aozqoHXpg8idhs3FHfGEuYGE+pgAnBRKEBweaJJRdjrxY47+tbeCkQg8/VaulRRVJWD76P5qd9Tkdep+Y7i1e/MWK+s659oQH5NteEPIcxYV3O8Wy0emfEtGyjagVF4LuQx+CSvShM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192717; c=relaxed/simple; bh=HaCeFgeBKgW1ML1s8fwj4FRsXH/GRZ7CayunP31zXgw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NobFsqbPg85KBUURayYlH/F9EegCH1Fr3tHeHv9eQpKNl7QY5n8cV43xIkI2iQ4Jotpo8OYo4M2qyJdHjp/id/EmDlHwGj8e4FQ6HzPZLtXt9QzD94HZTlB7nugRT4wHMYS8FWeCFrsTi7TSAIXRG50WGzE5cNqkXKFXCG3XMJk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Sg1qdmW6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Sg1qdmW6" Received: by smtp.kernel.org (Postfix) with ESMTPS id 64C60C19422; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756192717; bh=HaCeFgeBKgW1ML1s8fwj4FRsXH/GRZ7CayunP31zXgw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Sg1qdmW6KN/HncXfO3wKeYhwhbeEhF1/JVyZKgjIkbqIULLqhzfM6KdbEJ3R6F20l hORrUlVDDStMfDAlDujkBePmP3HVA1jwhFbLeUoSddcAod6zSeckGB2U5gDtts3WKW vploHqTQymjDEaZuImpd7xQCg6upJWO+VIWo00qaxblwp1l5fwcjHsayEgdjZhM5aH 9RvBJbAOq7HiOVNdbM/Lv4ZjkA7IsbI5NFUesYcpTKynNRVFJkfEN+oTUPq1fN6szq IdcGUhxHAv6E3rqeq0l2CP/Ib0um8qXP4aRDog0MHLjlQC2rl2gSC6IVFkOs901s5F 3X4hAl1UDDEqg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A717CA0FF2; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 26 Aug 2025 15:18:31 +0800 Subject: [PATCH v3 4/8] power: supply: qcom_battmgr: Add state_of_health property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-qcom_battmgr_update-v3-4-74ea410ef146@oss.qualcomm.com> References: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> In-Reply-To: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> To: Sebastian Reichel , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , Dmitry Baryshkov , Bryan O'Donoghue , Konrad Dybcio Cc: Subbaraman Narayanamurthy , David Collins , =?utf-8?q?Gy=C3=B6rgy_Kurucz?= , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@oss.qualcomm.com, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756192715; l=2199; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=4hGGGPKO891NP5TSVeZv1e7gVhGgtpNPWpkz9SPxNA8=; b=YjCFlxxMJuxHvuVm1mXz8AWq6HWeT0K66Z4CJWQRfxpuRlYQE+UZZqYualrbre/q8Y20Axujp bLXB+wqf4XXAoi97DSzP/Ujv3/CMuSZR2aUqvAs6XEZM37GcTughtVb X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Add state_of_health property to read battery health percentage from battery management firmware. Signed-off-by: Fenglin Wu Tested-by: Neil Armstrong # on Thinkpad T14S OL= ED --- drivers/power/supply/qcom_battmgr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qco= m_battmgr.c index 55477ae92fd56ede465b32d6f7ed9da78ebd869c..008e241e3eac3574a78459a2256= e006e48c9f508 100644 --- a/drivers/power/supply/qcom_battmgr.c +++ b/drivers/power/supply/qcom_battmgr.c @@ -256,6 +256,7 @@ struct qcom_battmgr_status { unsigned int voltage_ocv; unsigned int temperature; unsigned int resistance; + unsigned int soh_percent; =20 unsigned int discharge_time; unsigned int charge_time; @@ -421,6 +422,7 @@ static const u8 sm8350_bat_prop_map[] =3D { [POWER_SUPPLY_PROP_TIME_TO_FULL_AVG] =3D BATT_TTF_AVG, [POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG] =3D BATT_TTE_AVG, [POWER_SUPPLY_PROP_INTERNAL_RESISTANCE] =3D BATT_RESISTANCE, + [POWER_SUPPLY_PROP_STATE_OF_HEALTH] =3D BATT_SOH, [POWER_SUPPLY_PROP_POWER_NOW] =3D BATT_POWER_NOW, }; =20 @@ -588,6 +590,9 @@ static int qcom_battmgr_bat_get_property(struct power_s= upply *psy, case POWER_SUPPLY_PROP_INTERNAL_RESISTANCE: val->intval =3D battmgr->status.resistance; break; + case POWER_SUPPLY_PROP_STATE_OF_HEALTH: + val->intval =3D battmgr->status.soh_percent; + break; case POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG: val->intval =3D battmgr->status.discharge_time; break; @@ -672,6 +677,7 @@ static const enum power_supply_property sm8350_bat_prop= s[] =3D { POWER_SUPPLY_PROP_TIME_TO_FULL_AVG, POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG, POWER_SUPPLY_PROP_INTERNAL_RESISTANCE, + POWER_SUPPLY_PROP_STATE_OF_HEALTH, POWER_SUPPLY_PROP_POWER_NOW, }; =20 @@ -1141,6 +1147,9 @@ static void qcom_battmgr_sm8350_callback(struct qcom_= battmgr *battmgr, case BATT_CAPACITY: battmgr->status.percent =3D le32_to_cpu(resp->intval.value) / 100; break; + case BATT_SOH: + battmgr->status.soh_percent =3D le32_to_cpu(resp->intval.value); + break; case BATT_VOLT_OCV: battmgr->status.voltage_ocv =3D le32_to_cpu(resp->intval.value); break; --=20 2.34.1 From nobody Fri Oct 3 20:30:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0612D2F657A; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192718; cv=none; b=YcRiaHEOTRLWRJHB92gbUzMk9pAJOWwl7zFQX/LQ2rfruscExFzgqciE5G4Yr6y84FnYSmizNFjCB2NgZIKvuY5nGUWt96j6Ipk5xmPIESftYQhm5qdZpB6Y92ltfpihP8Y3csqtQxAG5D/oPZM/4zCjzQMDMoOCWG2zYcxJc4s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192718; c=relaxed/simple; bh=r3sY4ytaz+niwJh3RnoLADMn3LVz4c7xzRhnQ6L8M+k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QpbV70DTM+NtYhjkH7h43P6VignrVto0ec64yejkRsvssbb6HZ0UHmjwflL7ODyPd5RURER3p7RsaZZFf2zzAsVkGxhDiQE+vdQM7aSr2yuYZzN22exJ6/3wshsgpFJ4AQiVU6f00tHPdeGPs4FUgON6nhBBFJmpIVPobl+HWGk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MYVXftP/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MYVXftP/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 717D0C2BC86; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756192717; bh=r3sY4ytaz+niwJh3RnoLADMn3LVz4c7xzRhnQ6L8M+k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MYVXftP/ggG39anM0HdnuEVVSo6qB6bV/gCJUyUUBzExCfYLV2c+Q85Ive1eZ92aC wph5qg2BEINmOgJBhsIlE4R0GqmHuMKf0h8wMoKbXBWByvEOCsEDVVuOOkTQYAoFoB TPfM+wbTuH5s0EkV7DjNUSGI9nxjppHr96CClKAq4lQ8WUnXaRyPODccA6WkNAorK6 IB8U3sPf6uRt+Q2uDG5q0s9ayDyo1XjjIqp7huB9npkiSaPhABws4ew8TsDbo3n5yc 1ep9uhq/RS/XGndTfetf4/AWylxZmnGSRhM/IKyFex0HmtkP5Vno3NrTFjh1Zo4MaE Cd9GgsDEqCrxw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68949CA0FE9; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 26 Aug 2025 15:18:32 +0800 Subject: [PATCH v3 5/8] power: supply: qcom_battmgr: update compats for SM8550 and X1E80100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-qcom_battmgr_update-v3-5-74ea410ef146@oss.qualcomm.com> References: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> In-Reply-To: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> To: Sebastian Reichel , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , Dmitry Baryshkov , Bryan O'Donoghue , Konrad Dybcio Cc: Subbaraman Narayanamurthy , David Collins , =?utf-8?q?Gy=C3=B6rgy_Kurucz?= , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@oss.qualcomm.com, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756192715; l=1579; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=+qDRNAGRuy9qBxJBOT77eHOX4R2i3kyoPtbI3yzOFKI=; b=j+3uDWtnN6GirByhE5ARQmiAIBk8ASdKFTYiwe9Kj8mFEoFVVmtXMuqUXMLEjulIK5l00xEY1 F6AIT98DjtkAxdBkeq4Fd64MRjvhvtTsSO2vlZ2KtV+uNXhUXTbsX5e X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Add variant definitions for SM8550 and X1E80100 platforms. Add a compat for SM8550 and update match data for X1E80100 specifically so that they could be handled differently in supporting charge control functionality. Signed-off-by: Fenglin Wu Tested-by: Neil Armstrong # on Thinkpad T14S OL= ED --- drivers/power/supply/qcom_battmgr.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qco= m_battmgr.c index 008e241e3eac3574a78459a2256e006e48c9f508..174d3f83ac2b070bb90c21a4986= 86e91cc629ebe 100644 --- a/drivers/power/supply/qcom_battmgr.c +++ b/drivers/power/supply/qcom_battmgr.c @@ -19,8 +19,10 @@ #define BATTMGR_STRING_LEN 128 =20 enum qcom_battmgr_variant { - QCOM_BATTMGR_SM8350, QCOM_BATTMGR_SC8280XP, + QCOM_BATTMGR_SM8350, + QCOM_BATTMGR_SM8550, + QCOM_BATTMGR_X1E80100, }; =20 #define BATTMGR_BAT_STATUS 0x1 @@ -1333,7 +1335,8 @@ static void qcom_battmgr_pdr_notify(void *priv, int s= tate) static const struct of_device_id qcom_battmgr_of_variants[] =3D { { .compatible =3D "qcom,sc8180x-pmic-glink", .data =3D (void *)QCOM_BATTM= GR_SC8280XP }, { .compatible =3D "qcom,sc8280xp-pmic-glink", .data =3D (void *)QCOM_BATT= MGR_SC8280XP }, - { .compatible =3D "qcom,x1e80100-pmic-glink", .data =3D (void *)QCOM_BATT= MGR_SC8280XP }, + { .compatible =3D "qcom,sm8550-pmic-glink", .data =3D (void *)QCOM_BATTMG= R_SM8550 }, + { .compatible =3D "qcom,x1e80100-pmic-glink", .data =3D (void *)QCOM_BATT= MGR_X1E80100 }, /* Unmatched devices falls back to QCOM_BATTMGR_SM8350 */ {} }; --=20 2.34.1 From nobody Fri Oct 3 20:30:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 062492F657E; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192718; cv=none; b=LLUMnHv9XzShXXQVC6I7tQ09fYNkXxuf2wvRyqNynrXImAZKYBij5/9m2lmsKwj3PM42Iq1uLB8VL/xtnP8OLXrntvPRTdhib4yposiWpTnNO2Wxb8I4ka+tdiyfa4He9bkRx6LWLrj0VUsBf3IZWR9dGZxBs89z3DwMuX/jCdE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192718; c=relaxed/simple; bh=c9FpxhMbO0dHJY+8IwcerSUUGg4XtosdvIRtqr24ytw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=st8zRdlz7Qty4C+2Bqllypbla2Wv1riw0/B4G0UQ+rFVmuPRydOvUXm3+JZpSY3I15AtLiDc0I3kvDbWo2T6iL6SHhinnAdWBelrloEieFtMjQuJ9gK+QPG4dexXmPQjxf6MHJOFMP1pyH/OXe5O+eP45Ma9FoYsUAcclWaHcMk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uNIkFdiH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uNIkFdiH" Received: by smtp.kernel.org (Postfix) with ESMTPS id 80F54C2BCB4; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756192717; bh=c9FpxhMbO0dHJY+8IwcerSUUGg4XtosdvIRtqr24ytw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=uNIkFdiHoF3Dq4lRSIfAawSrqom1FSmEVkQHS6tKlI/rzfQiBEqFSueUQhEaMQf/j eP15kYpgfHtQUA8T72f8n59D9N4cdQH1e421F8KsxJn3YsTn4glKqUx8KXD1uKq80h zoxgjGR64QQJo3ZKQBCx6iPqfkxyq/LRe/pullaq5czU/9b4KhGKNWrKG3aHvgyWWO x85amhZb1IFqsY5qb0stcgms0pJ+heByC606ZAv1iBAX64qLVAS8kGIs4qKRyrtG7G QEWV1M8Nk8jbuoTJr1CpBmk6A6ufxtLnz8fCGmVcFShVN+3Vh+hUlS6ETjiDqmkDTb OYskWxFa+DgPA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75FB1CA0EFA; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 26 Aug 2025 15:18:33 +0800 Subject: [PATCH v3 6/8] dt-bindings: soc: qcom,pmic-glink: Add charge limit nvmem properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-qcom_battmgr_update-v3-6-74ea410ef146@oss.qualcomm.com> References: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> In-Reply-To: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> To: Sebastian Reichel , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , Dmitry Baryshkov , Bryan O'Donoghue , Konrad Dybcio Cc: Subbaraman Narayanamurthy , David Collins , =?utf-8?q?Gy=C3=B6rgy_Kurucz?= , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@oss.qualcomm.com, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756192715; l=1445; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=ORlAVczHQEA0etBKQz2CENwDXUZXd+9EuSntaMi9ZEE=; b=h48ys0f+qEB7+0uoFBLr92/XOO7t0htNP1CHWOiYkdaL5AJMU/ZtZxF0qrfgA+gMUrD7lbn/O p92TpiOpK2QAiirfCQsuKD8nqztmnaapvAua+H64T17OyqHbnXYXVgc X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Add nvmem properties to retrieve charge control configurations from the PMIC SDAM registers. Signed-off-by: Fenglin Wu Acked-by: Rob Herring (Arm) Tested-by: Neil Armstrong # on Thinkpad T14S OL= ED --- .../devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yam= l b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 4c9e78f29523e3d77aacb4299f64ab96f9b1a831..9d6db4825da389aa14d77f653d2= f8a3442e22162 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -55,6 +55,20 @@ properties: The array should contain a gpio entry for each PMIC Glink connector,= in reg order. It is defined that GPIO active level means "CC2" or Reversed/Flipped= orientation. =20 + nvmem-cells: + minItems: 3 + maxItems: 3 + description: + The nvmem cells contain the charge control settings, including the c= harge control + enable status, the battery state of charge (SoC) threshold for stopp= ing charging, + and the battery SoC delta required to restart charging. + + nvmem-cell-names: + items: + - const: charge_limit_en + - const: charge_limit_end + - const: charge_limit_delta + patternProperties: '^connector@\d$': $ref: /schemas/connector/usb-connector.yaml# --=20 2.34.1 From nobody Fri Oct 3 20:30:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32C5B2F7475; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192718; cv=none; b=DZD/qRTj2aA7ww0EQAN18+Dg2crjNkw2qqubxMhHE0JG96z1DMHe8+CnJyvPg4gPXeFcuaz5BW6n9LFJREiQDrXRDIMUpWcGLRDewm6wfNIdk5CzovggE8PgSP9qiaLxz7FVE/UVHuUSOcOa9rV0vczNR/VOh+pB/huBbhnkj/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192718; c=relaxed/simple; bh=/xvWwbXNZdVdd8LbcSqP/I7FgHVp4m5GJ6D0r5nbaTo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Kg59VlHqUNMi22VKSffDqIHsSLUrqerzDCVmNY4bK7UEZNqw9bU01uG1pCRnvvsswnEdTKkzLrcKUt3moROMa8TfRLRoDb/tk9+YAEu91Hcoca7i4Hmjq023k6Wvky7rXLROhcOkx2r3p9RaltCnb6pTcfkWBvRqz0Ss+2bJoXs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E/4ibi8z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E/4ibi8z" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8E5CEC2BCB9; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756192717; bh=/xvWwbXNZdVdd8LbcSqP/I7FgHVp4m5GJ6D0r5nbaTo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=E/4ibi8zL2z74uGhw3+LfDXmVgp6QxhMW5CcUKFGiznOcxwhgJrPfnEWRLppyvU+C ADggs7+IpKAYVocOmEGVweSR020K2KUnnLfP+3N6cMI20XQSom7gUKSFYnMFRP+aDT qjr5Mt91bvxIP9quSNz0rXwm4jeWMAeYYRyNpKUlCbkpf9xcu+cxx72ymMQOyABgpR +HPmBoUZ4PYjHmG57ojs/f9it+2E0UaKdfgjRRWBb/VJ83hJwUIWRbOU/Xlrdw4Tjj gyGSRCG4Utev2Lh2Iv/UI1oYAArS3rHp1RG5+/7ZxvqAw5dT3AbzcAldg6L5gSuHWP F/3QwxbpGV9zA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84C59CA0FF0; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 26 Aug 2025 15:18:34 +0800 Subject: [PATCH v3 7/8] power: supply: qcom_battmgr: Add charge control support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-qcom_battmgr_update-v3-7-74ea410ef146@oss.qualcomm.com> References: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> In-Reply-To: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> To: Sebastian Reichel , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , Dmitry Baryshkov , Bryan O'Donoghue , Konrad Dybcio Cc: Subbaraman Narayanamurthy , David Collins , =?utf-8?q?Gy=C3=B6rgy_Kurucz?= , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@oss.qualcomm.com, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756192715; l=16265; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=XLZOvcmHE6RROkhLWhnjCbOoiqF7//GLRnH4lRYpZYs=; b=ZNlYBz7/oigSGbX9g34JWCAUwfrfpZq7WFs6gdeh+Fqcbpb69hIzPPRaIPtl8N8nhUVuYOzJg 733DkvBS9EHBB5hpMXL2VaFB+cldw7nxZ+VYUGtFYXISIUjjsXoky14 X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Add charge control support for SM8550 and X1E80100. It's supported with below two power supply properties: charge_control_end_threshold: The battery SoC (State of Charge) threshold at which the charging should be terminated. charge_control_start_threshold: The battery SoC threshold at which the charging should be resumed. Signed-off-by: Fenglin Wu Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong # on Thinkpad T14S OL= ED --- drivers/power/supply/qcom_battmgr.c | 290 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 283 insertions(+), 7 deletions(-) diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qco= m_battmgr.c index 174d3f83ac2b070bb90c21a498686e91cc629ebe..23c68eb942f1b213f634e31a454= 20b3e113e2764 100644 --- a/drivers/power/supply/qcom_battmgr.c +++ b/drivers/power/supply/qcom_battmgr.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -68,6 +69,9 @@ enum qcom_battmgr_variant { #define BATT_RESISTANCE 21 #define BATT_POWER_NOW 22 #define BATT_POWER_AVG 23 +#define BATT_CHG_CTRL_EN 24 +#define BATT_CHG_CTRL_START_THR 25 +#define BATT_CHG_CTRL_END_THR 26 =20 #define BATTMGR_USB_PROPERTY_GET 0x32 #define BATTMGR_USB_PROPERTY_SET 0x33 @@ -92,6 +96,13 @@ enum qcom_battmgr_variant { #define WLS_TYPE 5 #define WLS_BOOST_EN 6 =20 +#define BATTMGR_CHG_CTRL_LIMIT_EN 0x48 +#define CHARGE_CTRL_START_THR_MIN 50 +#define CHARGE_CTRL_START_THR_MAX 95 +#define CHARGE_CTRL_END_THR_MIN 55 +#define CHARGE_CTRL_END_THR_MAX 100 +#define CHARGE_CTRL_DELTA_SOC 5 + struct qcom_battmgr_enable_request { struct pmic_glink_hdr hdr; __le32 battery_id; @@ -126,6 +137,13 @@ struct qcom_battmgr_discharge_time_request { __le32 reserved; }; =20 +struct qcom_battmgr_charge_ctrl_request { + struct pmic_glink_hdr hdr; + __le32 enable; + __le32 target_soc; + __le32 delta_soc; +}; + struct qcom_battmgr_message { struct pmic_glink_hdr hdr; union { @@ -238,6 +256,8 @@ struct qcom_battmgr_info { unsigned int capacity_warning; unsigned int cycle_count; unsigned int charge_count; + unsigned int charge_ctrl_start; + unsigned int charge_ctrl_end; char model_number[BATTMGR_STRING_LEN]; char serial_number[BATTMGR_STRING_LEN]; char oem_info[BATTMGR_STRING_LEN]; @@ -426,6 +446,8 @@ static const u8 sm8350_bat_prop_map[] =3D { [POWER_SUPPLY_PROP_INTERNAL_RESISTANCE] =3D BATT_RESISTANCE, [POWER_SUPPLY_PROP_STATE_OF_HEALTH] =3D BATT_SOH, [POWER_SUPPLY_PROP_POWER_NOW] =3D BATT_POWER_NOW, + [POWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD] =3D BATT_CHG_CTRL_STAR= T_THR, + [POWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD] =3D BATT_CHG_CTRL_END_TH= R, }; =20 static int qcom_battmgr_bat_sm8350_update(struct qcom_battmgr *battmgr, @@ -496,7 +518,8 @@ static int qcom_battmgr_bat_get_property(struct power_s= upply *psy, if (!battmgr->service_up) return -EAGAIN; =20 - if (battmgr->variant =3D=3D QCOM_BATTMGR_SC8280XP) + if (battmgr->variant =3D=3D QCOM_BATTMGR_SC8280XP || + battmgr->variant =3D=3D QCOM_BATTMGR_X1E80100) ret =3D qcom_battmgr_bat_sc8280xp_update(battmgr, psp); else ret =3D qcom_battmgr_bat_sm8350_update(battmgr, psp); @@ -601,6 +624,12 @@ static int qcom_battmgr_bat_get_property(struct power_= supply *psy, case POWER_SUPPLY_PROP_TIME_TO_FULL_AVG: val->intval =3D battmgr->status.charge_time; break; + case POWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD: + val->intval =3D battmgr->info.charge_ctrl_start; + break; + case POWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD: + val->intval =3D battmgr->info.charge_ctrl_end; + break; case POWER_SUPPLY_PROP_MANUFACTURE_YEAR: val->intval =3D battmgr->info.year; break; @@ -626,6 +655,149 @@ static int qcom_battmgr_bat_get_property(struct power= _supply *psy, return 0; } =20 +static int qcom_battmgr_set_charge_control(struct qcom_battmgr *battmgr, + u32 target_soc, u32 delta_soc) +{ + struct qcom_battmgr_charge_ctrl_request request =3D { + .hdr.owner =3D cpu_to_le32(PMIC_GLINK_OWNER_BATTMGR), + .hdr.type =3D cpu_to_le32(PMIC_GLINK_REQ_RESP), + .hdr.opcode =3D cpu_to_le32(BATTMGR_CHG_CTRL_LIMIT_EN), + .enable =3D cpu_to_le32(1), + .target_soc =3D cpu_to_le32(target_soc), + .delta_soc =3D cpu_to_le32(delta_soc), + }; + + return qcom_battmgr_request(battmgr, &request, sizeof(request)); +} + +static int qcom_battmgr_set_charge_start_threshold(struct qcom_battmgr *ba= ttmgr, int start_soc) +{ + u32 target_soc, delta_soc; + int ret; + + if (start_soc < CHARGE_CTRL_START_THR_MIN || + start_soc > CHARGE_CTRL_START_THR_MAX) { + dev_err(battmgr->dev, "charge control start threshold exceed range: [%u = - %u]\n", + CHARGE_CTRL_START_THR_MIN, CHARGE_CTRL_START_THR_MAX); + return -EINVAL; + } + + /* + * If the new start threshold is larger than the old end threshold, + * move the end threshold one step (DELTA_SOC) after the new start + * threshold. + */ + if (start_soc > battmgr->info.charge_ctrl_end) { + target_soc =3D start_soc + CHARGE_CTRL_DELTA_SOC; + target_soc =3D min_t(u32, target_soc, CHARGE_CTRL_END_THR_MAX); + delta_soc =3D target_soc - start_soc; + delta_soc =3D min_t(u32, delta_soc, CHARGE_CTRL_DELTA_SOC); + } else { + target_soc =3D battmgr->info.charge_ctrl_end; + delta_soc =3D battmgr->info.charge_ctrl_end - start_soc; + } + + mutex_lock(&battmgr->lock); + ret =3D qcom_battmgr_set_charge_control(battmgr, target_soc, delta_soc); + mutex_unlock(&battmgr->lock); + if (!ret) { + battmgr->info.charge_ctrl_start =3D start_soc; + battmgr->info.charge_ctrl_end =3D target_soc; + } + + return 0; +} + +static int qcom_battmgr_set_charge_end_threshold(struct qcom_battmgr *batt= mgr, int end_soc) +{ + u32 delta_soc =3D CHARGE_CTRL_DELTA_SOC; + int ret; + + if (end_soc < CHARGE_CTRL_END_THR_MIN || + end_soc > CHARGE_CTRL_END_THR_MAX) { + dev_err(battmgr->dev, "charge control end threshold exceed range: [%u - = %u]\n", + CHARGE_CTRL_END_THR_MIN, CHARGE_CTRL_END_THR_MAX); + return -EINVAL; + } + + if (battmgr->info.charge_ctrl_start && end_soc > battmgr->info.charge_ctr= l_start) + delta_soc =3D end_soc - battmgr->info.charge_ctrl_start; + + mutex_lock(&battmgr->lock); + ret =3D qcom_battmgr_set_charge_control(battmgr, end_soc, delta_soc); + mutex_unlock(&battmgr->lock); + if (!ret) { + battmgr->info.charge_ctrl_start =3D end_soc - delta_soc; + battmgr->info.charge_ctrl_end =3D end_soc; + } + + return 0; +} + +static int qcom_battmgr_charge_control_thresholds_init(struct qcom_battmgr= *battmgr) +{ + int ret; + u8 en, end_soc, start_soc, delta_soc; + + ret =3D nvmem_cell_read_u8(battmgr->dev->parent, "charge_limit_en", &en); + if (!ret && en !=3D 0) { + ret =3D nvmem_cell_read_u8(battmgr->dev->parent, "charge_limit_end", &en= d_soc); + if (ret < 0) + return ret; + + ret =3D nvmem_cell_read_u8(battmgr->dev->parent, "charge_limit_delta", &= delta_soc); + if (ret < 0) + return ret; + + if (delta_soc >=3D end_soc) + return -EINVAL; + + start_soc =3D end_soc - delta_soc; + end_soc =3D clamp(end_soc, CHARGE_CTRL_END_THR_MIN, CHARGE_CTRL_END_THR_= MAX); + start_soc =3D clamp(start_soc, CHARGE_CTRL_START_THR_MIN, CHARGE_CTRL_ST= ART_THR_MAX); + + battmgr->info.charge_ctrl_start =3D start_soc; + battmgr->info.charge_ctrl_end =3D end_soc; + } + + return 0; +} + +static int qcom_battmgr_bat_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + switch (psp) { + case POWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD: + case POWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD: + return 1; + default: + return 0; + } + + return 0; +} + +static int qcom_battmgr_bat_set_property(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *pval) +{ + struct qcom_battmgr *battmgr =3D power_supply_get_drvdata(psy); + + if (!battmgr->service_up) + return -EAGAIN; + + switch (psp) { + case POWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD: + return qcom_battmgr_set_charge_start_threshold(battmgr, pval->intval); + case POWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD: + return qcom_battmgr_set_charge_end_threshold(battmgr, pval->intval); + default: + return -EINVAL; + } + + return 0; +} + static const enum power_supply_property sc8280xp_bat_props[] =3D { POWER_SUPPLY_PROP_STATUS, POWER_SUPPLY_PROP_PRESENT, @@ -659,6 +831,43 @@ static const struct power_supply_desc sc8280xp_bat_psy= _desc =3D { .get_property =3D qcom_battmgr_bat_get_property, }; =20 +static const enum power_supply_property x1e80100_bat_props[] =3D { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_CYCLE_COUNT, + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_POWER_NOW, + POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, + POWER_SUPPLY_PROP_CHARGE_FULL, + POWER_SUPPLY_PROP_CHARGE_EMPTY, + POWER_SUPPLY_PROP_CHARGE_NOW, + POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN, + POWER_SUPPLY_PROP_ENERGY_FULL, + POWER_SUPPLY_PROP_ENERGY_EMPTY, + POWER_SUPPLY_PROP_ENERGY_NOW, + POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_MANUFACTURE_YEAR, + POWER_SUPPLY_PROP_MANUFACTURE_MONTH, + POWER_SUPPLY_PROP_MANUFACTURE_DAY, + POWER_SUPPLY_PROP_MODEL_NAME, + POWER_SUPPLY_PROP_MANUFACTURER, + POWER_SUPPLY_PROP_SERIAL_NUMBER, + POWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD, + POWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD, +}; + +static const struct power_supply_desc x1e80100_bat_psy_desc =3D { + .name =3D "qcom-battmgr-bat", + .type =3D POWER_SUPPLY_TYPE_BATTERY, + .properties =3D x1e80100_bat_props, + .num_properties =3D ARRAY_SIZE(x1e80100_bat_props), + .get_property =3D qcom_battmgr_bat_get_property, + .set_property =3D qcom_battmgr_bat_set_property, + .property_is_writeable =3D qcom_battmgr_bat_is_writeable, +}; + static const enum power_supply_property sm8350_bat_props[] =3D { POWER_SUPPLY_PROP_STATUS, POWER_SUPPLY_PROP_HEALTH, @@ -691,6 +900,42 @@ static const struct power_supply_desc sm8350_bat_psy_d= esc =3D { .get_property =3D qcom_battmgr_bat_get_property, }; =20 +static const enum power_supply_property sm8550_bat_props[] =3D { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_CHARGE_TYPE, + POWER_SUPPLY_PROP_CAPACITY, + POWER_SUPPLY_PROP_VOLTAGE_OCV, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_VOLTAGE_MAX, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_CHARGE_COUNTER, + POWER_SUPPLY_PROP_CYCLE_COUNT, + POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, + POWER_SUPPLY_PROP_CHARGE_FULL, + POWER_SUPPLY_PROP_MODEL_NAME, + POWER_SUPPLY_PROP_TIME_TO_FULL_AVG, + POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG, + POWER_SUPPLY_PROP_INTERNAL_RESISTANCE, + POWER_SUPPLY_PROP_STATE_OF_HEALTH, + POWER_SUPPLY_PROP_POWER_NOW, + POWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD, + POWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD, +}; + +static const struct power_supply_desc sm8550_bat_psy_desc =3D { + .name =3D "qcom-battmgr-bat", + .type =3D POWER_SUPPLY_TYPE_BATTERY, + .properties =3D sm8550_bat_props, + .num_properties =3D ARRAY_SIZE(sm8550_bat_props), + .get_property =3D qcom_battmgr_bat_get_property, + .set_property =3D qcom_battmgr_bat_set_property, + .property_is_writeable =3D qcom_battmgr_bat_is_writeable, +}; + static int qcom_battmgr_ac_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) @@ -766,7 +1011,8 @@ static int qcom_battmgr_usb_get_property(struct power_= supply *psy, if (!battmgr->service_up) return -EAGAIN; =20 - if (battmgr->variant =3D=3D QCOM_BATTMGR_SC8280XP) + if (battmgr->variant =3D=3D QCOM_BATTMGR_SC8280XP || + battmgr->variant =3D=3D QCOM_BATTMGR_X1E80100) ret =3D qcom_battmgr_bat_sc8280xp_update(battmgr, psp); else ret =3D qcom_battmgr_usb_sm8350_update(battmgr, psp); @@ -888,7 +1134,8 @@ static int qcom_battmgr_wls_get_property(struct power_= supply *psy, if (!battmgr->service_up) return -EAGAIN; =20 - if (battmgr->variant =3D=3D QCOM_BATTMGR_SC8280XP) + if (battmgr->variant =3D=3D QCOM_BATTMGR_SC8280XP || + battmgr->variant =3D=3D QCOM_BATTMGR_X1E80100) ret =3D qcom_battmgr_bat_sc8280xp_update(battmgr, psp); else ret =3D qcom_battmgr_wls_sm8350_update(battmgr, psp); @@ -1085,6 +1332,9 @@ static void qcom_battmgr_sc8280xp_callback(struct qco= m_battmgr *battmgr, case BATTMGR_BAT_CHARGE_TIME: battmgr->status.charge_time =3D le32_to_cpu(resp->time); break; + case BATTMGR_CHG_CTRL_LIMIT_EN: + battmgr->error =3D 0; + break; default: dev_warn(battmgr->dev, "unknown message %#x\n", opcode); break; @@ -1198,6 +1448,12 @@ static void qcom_battmgr_sm8350_callback(struct qcom= _battmgr *battmgr, case BATT_POWER_NOW: battmgr->status.power_now =3D le32_to_cpu(resp->intval.value); break; + case BATT_CHG_CTRL_START_THR: + battmgr->info.charge_ctrl_start =3D le32_to_cpu(resp->intval.value); + break; + case BATT_CHG_CTRL_END_THR: + battmgr->info.charge_ctrl_end =3D le32_to_cpu(resp->intval.value); + break; default: dev_warn(battmgr->dev, "unknown property %#x\n", property); break; @@ -1280,6 +1536,7 @@ static void qcom_battmgr_sm8350_callback(struct qcom_= battmgr *battmgr, } break; case BATTMGR_REQUEST_NOTIFICATION: + case BATTMGR_CHG_CTRL_LIMIT_EN: battmgr->error =3D 0; break; default: @@ -1299,7 +1556,8 @@ static void qcom_battmgr_callback(const void *data, s= ize_t len, void *priv) =20 if (opcode =3D=3D BATTMGR_NOTIFICATION) qcom_battmgr_notification(battmgr, data, len); - else if (battmgr->variant =3D=3D QCOM_BATTMGR_SC8280XP) + else if (battmgr->variant =3D=3D QCOM_BATTMGR_SC8280XP || + battmgr->variant =3D=3D QCOM_BATTMGR_X1E80100) qcom_battmgr_sc8280xp_callback(battmgr, data, len); else qcom_battmgr_sm8350_callback(battmgr, data, len); @@ -1346,11 +1604,13 @@ static char *qcom_battmgr_battery[] =3D { "battery"= }; static int qcom_battmgr_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id) { + const struct power_supply_desc *psy_desc; struct power_supply_config psy_cfg_supply =3D {}; struct power_supply_config psy_cfg =3D {}; const struct of_device_id *match; struct qcom_battmgr *battmgr; struct device *dev =3D &adev->dev; + int ret; =20 battmgr =3D devm_kzalloc(dev, sizeof(*battmgr), GFP_KERNEL); if (!battmgr) @@ -1376,8 +1636,19 @@ static int qcom_battmgr_probe(struct auxiliary_devic= e *adev, else battmgr->variant =3D QCOM_BATTMGR_SM8350; =20 - if (battmgr->variant =3D=3D QCOM_BATTMGR_SC8280XP) { - battmgr->bat_psy =3D devm_power_supply_register(dev, &sc8280xp_bat_psy_d= esc, &psy_cfg); + ret =3D qcom_battmgr_charge_control_thresholds_init(battmgr); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to init battery charge control thresholds\n"); + + if (battmgr->variant =3D=3D QCOM_BATTMGR_SC8280XP || + battmgr->variant =3D=3D QCOM_BATTMGR_X1E80100) { + if (battmgr->variant =3D=3D QCOM_BATTMGR_X1E80100) + psy_desc =3D &x1e80100_bat_psy_desc; + else + psy_desc =3D &sc8280xp_bat_psy_desc; + + battmgr->bat_psy =3D devm_power_supply_register(dev, psy_desc, &psy_cfg); if (IS_ERR(battmgr->bat_psy)) return dev_err_probe(dev, PTR_ERR(battmgr->bat_psy), "failed to register battery power supply\n"); @@ -1397,7 +1668,12 @@ static int qcom_battmgr_probe(struct auxiliary_devic= e *adev, return dev_err_probe(dev, PTR_ERR(battmgr->wls_psy), "failed to register wireless charing power supply\n"); } else { - battmgr->bat_psy =3D devm_power_supply_register(dev, &sm8350_bat_psy_des= c, &psy_cfg); + if (battmgr->variant =3D=3D QCOM_BATTMGR_SM8550) + psy_desc =3D &sm8550_bat_psy_desc; + else + psy_desc =3D &sm8350_bat_psy_desc; + + battmgr->bat_psy =3D devm_power_supply_register(dev, psy_desc, &psy_cfg); if (IS_ERR(battmgr->bat_psy)) return dev_err_probe(dev, PTR_ERR(battmgr->bat_psy), "failed to register battery power supply\n"); --=20 2.34.1 From nobody Fri Oct 3 20:30:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51E722F83B6; Tue, 26 Aug 2025 07:18:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192718; cv=none; b=KythlgmitbvCnaCzc3bnr4tv8yIS4klkdyqlJQEvo3aPZNdEH6/1vwitL6fm9//jfRThrCIoB0PgqMb+4S6ow/sBgek6OO4LYOUsT1AeBeX7L7xQWGf+/QO/BYy7A2hrfabMStA8kBPfaRynAJ4FFrZLKpCeBXmOEXOQYVrYTD4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756192718; c=relaxed/simple; bh=i0Nfy+9gssKmarkh7J2+cP0xs3hncTO4KeRTAk5qZO8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=huZCbrkCTK5qj8SdSa93deVIwK8fDWjid2kS60gGvJvxOa7BupriDWtdPTLDtMFDIWV0jDu3cRdstjVwVrsalkS2Vi41PwEeRVg3yqUAkcTNVJZi+okgG0mPEuUCLc+vSth/xb8qUOqqOGycYHZYBYb2W6OY4LciSTvalYon+yY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iscT6gSZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iscT6gSZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9BDD2C2BCB7; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756192717; bh=i0Nfy+9gssKmarkh7J2+cP0xs3hncTO4KeRTAk5qZO8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=iscT6gSZf9IrQsmHBTplipM+0F9X9OI8CwAzh0KIFSezDZwQHScS8J/8uoohKSUUs KBWZcz3v4+r7ykZS64xQcl9bUFHXYLBsXsx7VbqzgoU2nHVpR0ur5q5S8iOu+ZyLhr YPQ4mcjX4bCSzTB2hzQIvxOZsUJ1hhTwH7qY70WWRldfwv0Z3CVADnoDY/AL8z2X0w 7MDg8Dw/Vkdc5pK0aXCZDhu7MX3AgpZIlwUT8AeB+ksROrBq0vm8ynlp3veYmCxdkq N1M5S6rI/o4xKWeYuf8omNKus4x6V/hEwRKrAM2UW2pkOqOiiaIf/kVNQ/1XSxYcr8 4rQUrZbMgNM6g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93069CA0FEB; Tue, 26 Aug 2025 07:18:37 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Tue, 26 Aug 2025 15:18:35 +0800 Subject: [PATCH v3 8/8] arm64: dts: qcom: x1e80100-crd: Add charge limit nvmem Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-qcom_battmgr_update-v3-8-74ea410ef146@oss.qualcomm.com> References: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> In-Reply-To: <20250826-qcom_battmgr_update-v3-0-74ea410ef146@oss.qualcomm.com> To: Sebastian Reichel , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , Dmitry Baryshkov , Bryan O'Donoghue , Konrad Dybcio Cc: Subbaraman Narayanamurthy , David Collins , =?utf-8?q?Gy=C3=B6rgy_Kurucz?= , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@oss.qualcomm.com, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756192715; l=1892; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=nz0xqUIFES4rZCFzolpsU95uZVTcAXXyGgr1rWpbGA4=; b=DtfgkJIdv343kcIVoBWGlbvfyvBVocOucPuihWubpjjDuFsrX/vYpzAfcFgXdtNSKANvONaOl 83AnAvPj5lSDPvb5Z24TD+c7MHXCLo7Ic+6QxroMCMFUFp1JzvbD6i1 X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Add nvmem cells for getting charge control thresholds if they have been set previously. Signed-off-by: Fenglin Wu Tested-by: Neil Armstrong # on Thinkpad T14S OL= ED --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 2 ++ arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qco= m/x1-crd.dtsi index c9f0d505267081af66b0973fe6c1e33832a2c86b..8c3d30dd936ef9b12867971f5f2= 37dd12484072d 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -82,6 +82,8 @@ pmic-glink { <&tlmm 123 GPIO_ACTIVE_HIGH>, <&tlmm 125 GPIO_ACTIVE_HIGH>; =20 + nvmem-cells =3D <&charge_limit_en>, <&charge_limit_end>, <&charge_limit_= delta>; + nvmem-cell-names =3D "charge_limit_en", "charge_limit_end", "charge_limi= t_delta"; /* Left-side rear port */ connector@0 { compatible =3D "usb-c-connector"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot= /dts/qcom/x1e80100-pmics.dtsi index c02fd4d15c9649c222caaafa5ed2c777a10fb4f5..abf7afe5127d7b8b572513234e0= 0009ce837837d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -239,6 +239,26 @@ reboot_reason: reboot-reason@48 { }; }; =20 + pmk8550_sdam_15: nvram@7e00 { + compatible =3D "qcom,spmi-sdam"; + reg =3D <0x7e00>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x7e00 0x100>; + + charge_limit_en: charge-limit-en@73 { + reg =3D <0x73 0x1>; + }; + + charge_limit_end: charge-limit-end@75 { + reg =3D <0x75 0x1>; + }; + + charge_limit_delta: charge-limit-delta@75 { + reg =3D <0x76 0x1>; + }; + }; + pmk8550_gpios: gpio@8800 { compatible =3D "qcom,pmk8550-gpio", "qcom,spmi-gpio"; reg =3D <0xb800>; --=20 2.34.1