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To overcome these when needed, add a `from_bytes_copy` with a default implementation in the trait. `from_bytes_copy` returns an owned value that is populated using an unaligned read, removing the lifetime constraint and making it usable even on non-aligned byte slices. Reviewed-by: Alice Ryhl Signed-off-by: Alexandre Courbot Acked-by: Miguel Ojeda Reviewed-by: Benno Lossin Reviewed-by: John Hubbard --- rust/kernel/transmute.rs | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/rust/kernel/transmute.rs b/rust/kernel/transmute.rs index 494bb3b1d059337520efef694fc8952972d44fbf..721dd8254dcedd71ed7c1fc0ee9= 292950c16c89e 100644 --- a/rust/kernel/transmute.rs +++ b/rust/kernel/transmute.rs @@ -78,6 +78,23 @@ fn from_bytes_mut(bytes: &mut [u8]) -> Option<&mut Self> None } } + + /// Creates an owned instance of `Self` by copying `bytes`. + /// + /// As the data is copied into a properly-aligned location, this metho= d can be used even if + /// [`FromBytes::from_bytes`] would return `None` due to incompatible = alignment. + fn from_bytes_copy(bytes: &[u8]) -> Option + where + Self: Sized, + { + if bytes.len() =3D=3D size_of::() { + // SAFETY: `bytes` has the same size as `Self`, and per the in= variants of `FromBytes`, + // any byte sequence is a valid value for `Self`. + Some(unsafe { core::ptr::read_unaligned(bytes.as_ptr().cast::<= Self>()) }) + } else { + None + } + } } =20 macro_rules! impl_frombytes { --=20 2.50.1 From nobody Fri Oct 3 20:25:47 2025 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2055.outbound.protection.outlook.com [40.107.93.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7EFB2D3A60; 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Add basic support for it so subsequent patches can leverage it. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/firmware.rs | 62 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 62 insertions(+) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 2931912ddba0ea1fe6d027ccec70b39cdb40344a..ccb4d19f8fa76b0e844252dede5= f50b37c590571 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -4,11 +4,13 @@ //! to be loaded into a given execution unit. =20 use core::marker::PhantomData; +use core::mem::size_of; =20 use kernel::device; use kernel::firmware; use kernel::prelude::*; use kernel::str::CString; +use kernel::transmute::FromBytes; =20 use crate::dma::DmaObject; use crate::falcon::FalconFirmware; @@ -150,6 +152,66 @@ fn no_patch_signature(self) -> FirmwareDmaObject { } } =20 +/// Header common to most firmware files. +#[repr(C)] +#[derive(Debug, Clone)] +struct BinHdr { + /// Magic number, must be `0x10de`. + bin_magic: u32, + /// Version of the header. + bin_ver: u32, + /// Size in bytes of the binary (to be ignored). + bin_size: u32, + /// Offset of the start of the application-specific header. + header_offset: u32, + /// Offset of the start of the data payload. + data_offset: u32, + /// Size in bytes of the data payload. + data_size: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for BinHdr {} + +// A firmware blob starting with a `BinHdr`. +struct BinFirmware<'a> { + hdr: BinHdr, + fw: &'a [u8], +} + +#[expect(dead_code)] +impl<'a> BinFirmware<'a> { + /// Interpret `fw` as a firmware image starting with a [`BinHdr`], and= returns the + /// corresponding [`BinFirmware`] that can be used to extract its payl= oad. + fn new(fw: &'a firmware::Firmware) -> Result { + const BIN_MAGIC: u32 =3D 0x10de; + let fw =3D fw.data(); + + fw.get(0..size_of::()) + // Extract header. + .and_then(BinHdr::from_bytes_copy) + // Validate header. + .and_then(|hdr| { + if hdr.bin_magic =3D=3D BIN_MAGIC { + Some(hdr) + } else { + None + } + }) + .map(|hdr| Self { hdr, fw }) + .ok_or(EINVAL) + } + + /// Returns the data payload of the firmware, or `None` if the data ra= nge is out of bounds of + /// the firmware image. + fn data(&self) -> Option<&[u8]> { + let fw_start =3D self.hdr.data_offset as usize; + let fw_size =3D self.hdr.data_size as usize; + + self.fw.get(fw_start..fw_start + fw_size) + } +} + pub(crate) struct ModInfoBuilder(firmware::ModInfoBuilder<= N>); =20 impl ModInfoBuilder { --=20 2.50.1 From nobody Fri Oct 3 20:25:47 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2084.outbound.protection.outlook.com [40.107.92.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07B1F2C21D0; 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It is loaded on the sec2 falcon core and is responsible for loading and running the RISC-V GSP bootloader into the GSP core. Add support for parsing the Booter firmware loaded from userspace, patch its signatures, and store it into a form that is ready to be loaded and executed on the sec2 falcon. We do not run it yet, as its own payload (the GSP bootloader and firmware image) still need to be prepared. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 4 +- drivers/gpu/nova-core/firmware.rs | 25 ++- drivers/gpu/nova-core/firmware/booter.rs | 356 +++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/gpu.rs | 11 +- 4 files changed, 386 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 2dbcdf26697beb7e52083675fc9ea62a6167fef8..7bd13481a6a37783309c2d2621a= 6b67b81d55cc5 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -293,7 +293,7 @@ pub(crate) trait FalconEngine: } =20 /// Represents a portion of the firmware to be loaded into a particular me= mory (e.g. IMEM or DMEM). -#[derive(Debug)] +#[derive(Debug, Clone)] pub(crate) struct FalconLoadTarget { /// Offset from the start of the source object to copy from. pub(crate) src_start: u32, @@ -304,7 +304,7 @@ pub(crate) struct FalconLoadTarget { } =20 /// Parameters for the falcon boot ROM. -#[derive(Debug)] +#[derive(Debug, Clone)] pub(crate) struct FalconBromParams { /// Offset in `DMEM`` of the firmware's signature. pub(crate) pkc_data_offset: u32, diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index ccb4d19f8fa76b0e844252dede5f50b37c590571..be190af1e11aec26c18c85324a1= 85d135a16eabe 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -6,6 +6,7 @@ use core::marker::PhantomData; use core::mem::size_of; =20 +use booter::BooterFirmware; use kernel::device; use kernel::firmware; use kernel::prelude::*; @@ -13,10 +14,13 @@ use kernel::transmute::FromBytes; =20 use crate::dma::DmaObject; +use crate::driver::Bar0; use crate::falcon::FalconFirmware; +use crate::falcon::{sec2::Sec2, Falcon}; use crate::gpu; use crate::gpu::Chipset; =20 +pub(crate) mod booter; pub(crate) mod fwsec; =20 pub(crate) const FIRMWARE_VERSION: &str =3D "535.113.01"; @@ -24,14 +28,22 @@ /// Structure encapsulating the firmware blobs required for the GPU to ope= rate. #[expect(dead_code)] pub(crate) struct Firmware { - booter_load: firmware::Firmware, - booter_unload: firmware::Firmware, + /// Runs on the sec2 falcon engine to load and start the GSP bootloade= r. + booter_loader: BooterFirmware, + /// Runs on the sec2 falcon engine to stop and unload a running GSP fi= rmware. + booter_unloader: BooterFirmware, bootloader: firmware::Firmware, gsp: firmware::Firmware, } =20 impl Firmware { - pub(crate) fn new(dev: &device::Device, chipset: Chipset, ver: &str) -= > Result { + pub(crate) fn new( + dev: &device::Device, + sec2: &Falcon, + bar: &Bar0, + chipset: Chipset, + ver: &str, + ) -> Result { let mut chip_name =3D CString::try_from_fmt(fmt!("{chipset}"))?; chip_name.make_ascii_lowercase(); let chip_name =3D &*chip_name; @@ -42,8 +54,10 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset= , ver: &str) -> Result { fw: &'a [u8], } =20 -#[expect(dead_code)] impl<'a> BinFirmware<'a> { /// Interpret `fw` as a firmware image starting with a [`BinHdr`], and= returns the /// corresponding [`BinFirmware`] that can be used to extract its payl= oad. diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs new file mode 100644 index 0000000000000000000000000000000000000000..108649bdf716eeacaae3098b3c2= 9b2de2813c6ee --- /dev/null +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Support for loading and patching the `Booter` firmware. `Booter` is a = Heavy Secured firmware +//! running on [`Sec2`], that is used on Turing/Ampere to load the GSP fir= mware into the GSP falcon +//! (and optionally unload it through a separate firmware image). + +use core::marker::PhantomData; +use core::mem::size_of; +use core::ops::Deref; + +use kernel::device; +use kernel::firmware::Firmware; +use kernel::prelude::*; +use kernel::transmute::FromBytes; + +use crate::dma::DmaObject; +use crate::driver::Bar0; +use crate::falcon::sec2::Sec2; +use crate::falcon::{Falcon, FalconBromParams, FalconFirmware, FalconLoadPa= rams, FalconLoadTarget}; +use crate::firmware::{BinFirmware, FirmwareDmaObject, FirmwareSignature, S= igned, Unsigned}; + +/// Local convenience function to return a copy of `S` by reinterpreting t= he bytes starting at +/// `offset` in `slice`. +fn frombytes_at(slice: &[u8], offset: usize) -> Resu= lt { + slice + .get(offset..offset + size_of::()) + .and_then(S::from_bytes_copy) + .ok_or(EINVAL) +} + +/// Heavy-Secured firmware header. +/// +/// Such firmwares have an application-specific payload that needs to be p= atched with a given +/// signature. +#[repr(C)] +#[derive(Debug, Clone)] +struct HsHeaderV2 { + /// Offset to the start of the signatures. + sig_prod_offset: u32, + /// Size in bytes of the signatures. + sig_prod_size: u32, + /// Offset to a `u32` containing the location at which to patch the si= gnature in the microcode + /// image. + patch_loc: u32, + /// Offset to a `u32` containing the index of the signature to patch. + patch_sig: u32, + /// Start offset to the signature metadata. + meta_data_offset: u32, + /// Size in bytes of the signature metadata. + meta_data_size: u32, + /// Offset to a `u32` containing the number of signatures in the signa= tures section. + num_sig: u32, + /// Offset of the application-specific header. + header_offset: u32, + /// Size in bytes of the application-specific header. + header_size: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for HsHeaderV2 {} + +/// Heavy-Secured Firmware image container. +/// +/// This provides convenient access to the fields of [`HsHeaderV2`] that a= re actually indices to +/// read from in the firmware data. +struct HsFirmwareV2<'a> { + hdr: HsHeaderV2, + fw: &'a [u8], +} + +impl<'a> HsFirmwareV2<'a> { + /// Interprets the header of `bin_fw` as a [`HsHeaderV2`] and returns = an instance of + /// `HsFirmwareV2` for further parsing. + /// + /// Fails if the header pointed at by `bin_fw` is not within the bound= s of the firmware image. + fn new(bin_fw: &BinFirmware<'a>) -> Result { + frombytes_at::(bin_fw.fw, bin_fw.hdr.header_offset as = usize) + .map(|hdr| Self { hdr, fw: bin_fw.fw }) + } + + /// Returns the location at which the signatures should be patched in = the microcode image. + /// + /// Fails if the offset of the patch location is outside the bounds of= the firmware + /// image. + fn patch_location(&self) -> Result { + frombytes_at::(self.fw, self.hdr.patch_loc as usize) + } + + /// Returns an iterator to the signatures of the firmware. The iterato= r can be empty if the + /// firmware is unsigned. + /// + /// Fails if the pointed signatures are outside the bounds of the firm= ware image. + fn signatures_iter(&'a self) -> Result>> { + let num_sig =3D frombytes_at::(self.fw, self.hdr.num_sig as u= size)?; + let iter =3D match self.hdr.sig_prod_size.checked_div(num_sig) { + // If there are no signatures, return an iterator that will yi= eld zero elements. + None =3D> (&[] as &[u8]).chunks_exact(1), + Some(sig_size) =3D> { + let patch_sig =3D frombytes_at::(self.fw, self.hdr.pa= tch_sig as usize)?; + let signatures_start =3D (self.hdr.sig_prod_offset + patch= _sig) as usize; + + self.fw + // Get signatures range. + .get(signatures_start..signatures_start + self.hdr.sig= _prod_size as usize) + .ok_or(EINVAL)? + .chunks_exact(sig_size as usize) + } + }; + + // Map the byte slices into signatures. + Ok(iter.map(BooterSignature)) + } +} + +/// Signature parameters, as defined in the firmware. +#[repr(C)] +struct HsSignatureParams { + // Fuse version to use. + fuse_ver: u32, + // Mask of engine IDs this firmware applies to. + engine_id_mask: u32, + // ID of the microcode. + ucode_id: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for HsSignatureParams {} + +impl HsSignatureParams { + /// Returns the signature parameters contained in `hs_fw`. + /// + /// Fails if the meta data parameter of `hs_fw` is outside the bounds = of the firmware image, or + /// if its size doesn't match that of [`HsSignatureParams`]. + fn new(hs_fw: &HsFirmwareV2<'_>) -> Result { + let start =3D hs_fw.hdr.meta_data_offset as usize; + let end =3D start + .checked_add(hs_fw.hdr.meta_data_size as usize) + .ok_or(EINVAL)?; + + hs_fw + .fw + .get(start..end) + .and_then(Self::from_bytes_copy) + .ok_or(EINVAL) + } +} + +/// Header for code and data load offsets. +#[repr(C)] +#[derive(Debug, Clone)] +struct HsLoadHeaderV2 { + // Offset at which the code starts. + os_code_offset: u32, + // Total size of the code, for all apps. + os_code_size: u32, + // Offset at which the data starts. + os_data_offset: u32, + // Size of the data. + os_data_size: u32, + // Number of apps following this header. Each app is described by a [`= HsLoadHeaderV2App`]. + num_apps: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for HsLoadHeaderV2 {} + +impl HsLoadHeaderV2 { + /// Returns the load header contained in `hs_fw`. + /// + /// Fails if the header pointed at by `hs_fw` is not within the bounds= of the firmware image. + fn new(hs_fw: &HsFirmwareV2<'_>) -> Result { + frombytes_at::(hs_fw.fw, hs_fw.hdr.header_offset as usize) + } +} + +/// Header for app code loader. +#[repr(C)] +#[derive(Debug, Clone)] +struct HsLoadHeaderV2App { + /// Offset at which to load the app code. + offset: u32, + /// Length in bytes of the app code. + len: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for HsLoadHeaderV2App {} + +impl HsLoadHeaderV2App { + /// Returns the [`HsLoadHeaderV2App`] for app `idx` of `hs_fw`. + /// + /// Fails if `idx` is larger than the number of apps declared in `hs_f= w`, or if the header is + /// not within the bounds of the firmware image. + fn new(hs_fw: &HsFirmwareV2<'_>, idx: u32) -> Result { + let load_hdr =3D HsLoadHeaderV2::new(hs_fw)?; + if idx >=3D load_hdr.num_apps { + Err(EINVAL) + } else { + frombytes_at::( + hs_fw.fw, + (hs_fw.hdr.header_offset as usize) + // Skip the load header... + .checked_add(size_of::()) + // ... and jump to app header `idx`. + .and_then(|offset| { + offset.checked_add((idx as usize).checked_mul(size= _of::())?) + }) + .ok_or(EINVAL)?, + ) + } + } +} + +/// Signature for Booter firmware. Their size is encoded into the header a= nd not known a compile +/// time, so we just wrap a byte slices on which we can implement [`Firmwa= reSignature`]. +struct BooterSignature<'a>(&'a [u8]); + +impl<'a> AsRef<[u8]> for BooterSignature<'a> { + fn as_ref(&self) -> &[u8] { + self.0 + } +} + +impl<'a> FirmwareSignature for BooterSignature<'a> {} + +/// The `Booter` loader firmware, responsible for loading the GSP. +pub(crate) struct BooterFirmware { + // Load parameters for `IMEM` falcon memory. + imem_load_target: FalconLoadTarget, + // Load parameters for `DMEM` falcon memory. + dmem_load_target: FalconLoadTarget, + // BROM falcon parameters. + brom_params: FalconBromParams, + // Device-mapped firmware image. + ucode: FirmwareDmaObject, +} + +impl FirmwareDmaObject { + fn new_booter(dev: &device::Device, data: &[u8]) -> Res= ult { + DmaObject::from_data(dev, data).map(|ucode| Self(ucode, PhantomDat= a)) + } +} + +impl BooterFirmware { + /// Parses the Booter firmware contained in `fw`, and patches the corr= ect signature so it is + /// ready to be loaded and run on `falcon`. + pub(crate) fn new( + dev: &device::Device, + fw: &Firmware, + falcon: &Falcon<::Target>, + bar: &Bar0, + ) -> Result { + let bin_fw =3D BinFirmware::new(fw)?; + // The binary firmware embeds a Heavy-Secured firmware. + let hs_fw =3D HsFirmwareV2::new(&bin_fw)?; + // The Heavy-Secured firmware embeds a firmware load descriptor. + let load_hdr =3D HsLoadHeaderV2::new(&hs_fw)?; + // Offset in `ucode` where to patch the signature. + let patch_loc =3D hs_fw.patch_location()?; + let sig_params =3D HsSignatureParams::new(&hs_fw)?; + let brom_params =3D FalconBromParams { + // `load_hdr.os_data_offset` is an absolute index, but `pkc_da= ta_offset` is from the + // signature patch location. + pkc_data_offset: patch_loc + .checked_sub(load_hdr.os_data_offset) + .ok_or(EINVAL)?, + engine_id_mask: u16::try_from(sig_params.engine_id_mask).map_e= rr(|_| EINVAL)?, + ucode_id: u8::try_from(sig_params.ucode_id).map_err(|_| EINVAL= )?, + }; + let app0 =3D HsLoadHeaderV2App::new(&hs_fw, 0)?; + + // Object containing the firmware microcode to be signature-patche= d. + let ucode =3D bin_fw + .data() + .ok_or(EINVAL) + .and_then(|data| FirmwareDmaObject::::new_booter(dev,= data))?; + + let ucode_signed =3D { + let mut signatures =3D hs_fw.signatures_iter()?.peekable(); + + if signatures.peek().is_none() { + // If there are no signatures, then the firmware is unsign= ed. + ucode.no_patch_signature() + } else { + // Obtain the version from the fuse register, and extract = the corresponding + // signature. + let reg_fuse_version =3D falcon.signature_reg_fuse_version( + bar, + brom_params.engine_id_mask, + brom_params.ucode_id, + )?; + + let signature =3D match reg_fuse_version { + // `0` means the last signature should be used. + 0 =3D> signatures.last(), + // Otherwise hardware fuse version needs to be substra= cted to obtain the index. + reg_fuse_version =3D> { + let Some(idx) =3D sig_params.fuse_ver.checked_sub(= reg_fuse_version) else { + dev_err!(dev, "invalid fuse version for Booter= firmware\n"); + return Err(EINVAL); + }; + signatures.nth(idx as usize) + } + } + .ok_or(EINVAL)?; + + ucode.patch_signature(&signature, patch_loc as usize)? + } + }; + + Ok(Self { + imem_load_target: FalconLoadTarget { + src_start: app0.offset, + dst_start: 0, + len: app0.len, + }, + dmem_load_target: FalconLoadTarget { + src_start: load_hdr.os_data_offset, + dst_start: 0, + len: load_hdr.os_data_size, + }, + brom_params, + ucode: ucode_signed, + }) + } +} + +impl FalconLoadParams for BooterFirmware { + fn imem_load_params(&self) -> FalconLoadTarget { + self.imem_load_target.clone() + } + + fn dmem_load_params(&self) -> FalconLoadTarget { + self.dmem_load_target.clone() + } + + fn brom_params(&self) -> FalconBromParams { + self.brom_params.clone() + } + + fn boot_addr(&self) -> u32 { + self.imem_load_target.src_start + } +} + +impl Deref for BooterFirmware { + type Target =3D DmaObject; + + fn deref(&self) -> &Self::Target { + &self.ucode.0 + } +} + +impl FalconFirmware for BooterFirmware { + type Target =3D Sec2; +} diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 8caecaf7dfb4820a96a568a05653dbdf808a3719..54f0e9fd587ae5c4c045096930c= 0548fb1ef1b86 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -269,7 +269,6 @@ pub(crate) fn new( ) -> Result> { let bar =3D devres_bar.access(pdev.as_ref())?; let spec =3D Spec::new(bar)?; - let fw =3D Firmware::new(pdev.as_ref(), spec.chipset, FIRMWARE_VER= SION)?; =20 dev_info!( pdev.as_ref(), @@ -293,7 +292,15 @@ pub(crate) fn new( )?; gsp_falcon.clear_swgen0_intr(bar); =20 - let _sec2_falcon =3D Falcon::::new(pdev.as_ref(), spec.chips= et, bar, true)?; + let sec2_falcon =3D Falcon::::new(pdev.as_ref(), spec.chipse= t, bar, true)?; + + let fw =3D Firmware::new( + pdev.as_ref(), + &sec2_falcon, + bar, + spec.chipset, + FIRMWARE_VERSION, + )?; =20 let fb_layout =3D FbLayout::new(spec.chipset, bar)?; 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It is a regular binary firmware file containing a specific header. Create a type holding the DMA-mapped firmware as well as useful information extracted from the header, and hook it into our firmware structure for later use. Signed-off-by: Alexandre Courbot Reviewed-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 7 ++- drivers/gpu/nova-core/firmware/riscv.rs | 89 +++++++++++++++++++++++++++++= ++++ 2 files changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index be190af1e11aec26c18c85324a185d135a16eabe..9bee0e0a0ab99d10be7e56d3669= 70fdf4c813fc4 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -12,6 +12,7 @@ use kernel::prelude::*; use kernel::str::CString; use kernel::transmute::FromBytes; +use riscv::RiscvFirmware; =20 use crate::dma::DmaObject; use crate::driver::Bar0; @@ -22,6 +23,7 @@ =20 pub(crate) mod booter; pub(crate) mod fwsec; +pub(crate) mod riscv; =20 pub(crate) const FIRMWARE_VERSION: &str =3D "535.113.01"; =20 @@ -32,7 +34,8 @@ pub(crate) struct Firmware { booter_loader: BooterFirmware, /// Runs on the sec2 falcon engine to stop and unload a running GSP fi= rmware. booter_unloader: BooterFirmware, - bootloader: firmware::Firmware, + /// GSP bootloader, verifies the GSP firmware before loading and runni= ng it. + gsp_bootloader: RiscvFirmware, gsp: firmware::Firmware, } =20 @@ -58,7 +61,7 @@ pub(crate) fn new( .and_then(|fw| BooterFirmware::new(dev, &fw, sec2, bar))?, booter_unloader: request("booter_unload") .and_then(|fw| BooterFirmware::new(dev, &fw, sec2, bar))?, - bootloader: request("bootloader")?, + gsp_bootloader: request("bootloader").and_then(|fw| RiscvFirmw= are::new(dev, &fw))?, gsp: request("gsp")?, }) } diff --git a/drivers/gpu/nova-core/firmware/riscv.rs b/drivers/gpu/nova-cor= e/firmware/riscv.rs new file mode 100644 index 0000000000000000000000000000000000000000..926883230f2fe4e3327713e28b7= fae31ebee60bb --- /dev/null +++ b/drivers/gpu/nova-core/firmware/riscv.rs @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Support for firmware binaries designed to run on a RISC-V cores. Such = firmwares have a +//! dedicated header. + +use kernel::device; +use kernel::firmware::Firmware; +use kernel::prelude::*; +use kernel::transmute::FromBytes; + +use crate::dma::DmaObject; +use crate::firmware::BinFirmware; + +/// Descriptor for microcode running on a RISC-V core. +#[repr(C)] +#[derive(Debug)] +struct RmRiscvUCodeDesc { + version: u32, + bootloader_offset: u32, + bootloader_size: u32, + bootloader_param_offset: u32, + bootloader_param_size: u32, + riscv_elf_offset: u32, + riscv_elf_size: u32, + app_version: u32, + manifest_offset: u32, + manifest_size: u32, + monitor_data_offset: u32, + monitor_data_size: u32, + monitor_code_offset: u32, + monitor_code_size: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for RmRiscvUCodeDesc {} + +impl RmRiscvUCodeDesc { + /// Interprets the header of `bin_fw` as a [`RmRiscvUCodeDesc`] and re= turns it. + /// + /// Fails if the header pointed at by `bin_fw` is not within the bound= s of the firmware image. + fn new(bin_fw: &BinFirmware<'_>) -> Result { + let offset =3D bin_fw.hdr.header_offset as usize; + + bin_fw + .fw + .get(offset..offset + size_of::()) + .and_then(Self::from_bytes_copy) + .ok_or(EINVAL) + } +} + +/// A parsed firmware for a RISC-V core, ready to be loaded and run. +#[expect(unused)] +pub(crate) struct RiscvFirmware { + /// Offset at which the code starts in the firmware image. + code_offset: u32, + /// Offset at which the data starts in the firmware image. + data_offset: u32, + /// Offset at which the manifest starts in the firmware image. + manifest_offset: u32, + /// Application version. + app_version: u32, + /// Device-mapped firmware image. + ucode: DmaObject, +} + +impl RiscvFirmware { + // Parses the RISC-V firmware image contained in `fw`. + pub(crate) fn new(dev: &device::Device, fw: &Firmware) = -> Result { + let bin_fw =3D BinFirmware::new(fw)?; + + let riscv_desc =3D RmRiscvUCodeDesc::new(&bin_fw)?; + + let ucode =3D { + let start =3D bin_fw.hdr.data_offset as usize; + let len =3D bin_fw.hdr.data_size as usize; + + DmaObject::from_data(dev, fw.data().get(start..start + len).ok= _or(EINVAL)?)? + }; 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Its presentation is a bit peculiar as the GSP bootloader expects to be given a DMA address to a 3-levels page table mapping the GSP firmware at address 0 of its own address space. Prepare such a structure containing the DMA-mapped firmware as well as the DMA-mapped page tables, and a way to obtain the DMA handle of the level 0 page table. As we are performing the required ELF section parsing and radix3 page table building, remove these items from the TODO file. Signed-off-by: Alexandre Courbot --- Documentation/gpu/nova/core/todo.rst | 17 ----- drivers/gpu/nova-core/firmware.rs | 110 ++++++++++++++++++++++++++++++= +- drivers/gpu/nova-core/firmware/gsp.rs | 117 ++++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/gsp.rs | 4 ++ drivers/gpu/nova-core/nova_core.rs | 1 + 5 files changed, 229 insertions(+), 20 deletions(-) diff --git a/Documentation/gpu/nova/core/todo.rst b/Documentation/gpu/nova/= core/todo.rst index 89431fec9041b1f35cc55799c91f48dc6bc918eb..0972cb905f7ae64dfbaef480827= 6757319009e9c 100644 --- a/Documentation/gpu/nova/core/todo.rst +++ b/Documentation/gpu/nova/core/todo.rst @@ -229,23 +229,6 @@ Rust abstraction for debugfs APIs. GPU (general) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -Parse firmware headers ----------------------- - -Parse ELF headers from the firmware files loaded from the filesystem. - -| Reference: ELF utils -| Complexity: Beginner -| Contact: Abdiel Janulgue - -Build radix3 page table ------------------------ - -Build the radix3 page table to map the firmware. - -| Complexity: Intermediate -| Contact: Abdiel Janulgue - Initial Devinit support ----------------------- =20 diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 9bee0e0a0ab99d10be7e56d366970fdf4c813fc4..fb751287e938e6a323db185ff8c= 4ba2781d25285 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -7,6 +7,7 @@ use core::mem::size_of; =20 use booter::BooterFirmware; +use gsp::GspFirmware; use kernel::device; use kernel::firmware; use kernel::prelude::*; @@ -19,14 +20,100 @@ use crate::falcon::FalconFirmware; use crate::falcon::{sec2::Sec2, Falcon}; use crate::gpu; -use crate::gpu::Chipset; +use crate::gpu::{Architecture, Chipset}; =20 pub(crate) mod booter; pub(crate) mod fwsec; +pub(crate) mod gsp; pub(crate) mod riscv; =20 pub(crate) const FIRMWARE_VERSION: &str =3D "535.113.01"; =20 +/// Ad-hoc and temporary module to extract sections from ELF images. +/// +/// Some firmware images are currently packaged as ELF files, where sectio= ns names are used as keys +/// to specific and related bits of data. Future firmware versions are sch= eduled to move away from +/// that scheme before nova-core becomes stable, which means this module w= ill eventually be +/// removed. +mod elf { + use kernel::bindings; + use kernel::str::CStr; + use kernel::transmute::FromBytes; + + /// Newtype to provide a [`FromBytes`] implementation. + #[repr(transparent)] + struct Elf64Hdr(bindings::elf64_hdr); + + // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. + unsafe impl FromBytes for Elf64Hdr {} + + /// Tries to extract section with name `name` from the ELF64 image `el= f`, and returns it. + pub(super) fn elf64_section<'a, 'b>(elf: &'a [u8], name: &'b str) -> O= ption<&'a [u8]> { + let hdr =3D &elf + .get(0..size_of::()) + .and_then(Elf64Hdr::from_bytes)? + .0; + + // Get all the section headers. + let shdr =3D { + let shdr_num =3D usize::from(hdr.e_shnum); + let shdr_start =3D usize::try_from(hdr.e_shoff).ok()?; + let shdr_end =3D shdr_num + .checked_mul(size_of::()) + .and_then(|v| v.checked_add(shdr_start))?; + + elf.get(shdr_start..shdr_end) + .map(|slice| slice.as_ptr()) + .filter(|ptr| ptr.align_offset(align_of::()) =3D=3D 0) + // `FromBytes::from_bytes` does not support slices yet, so= build it manually. + // + // SAFETY: + // * `get` guarantees that the slice is within the bounds = of `elf` and of size + // `elf64_shdr * shdr_num`. + // * We checked that `ptr` had the correct alignment for `= elf64_shdr`. + .map(|ptr| unsafe { + core::slice::from_raw_parts(ptr.cast::(), shdr_num) + })? + }; + + // Get the strings table. + let strhdr =3D shdr.get(usize::from(hdr.e_shstrndx))?; + + // Find the section which name matches `name` and return it. + shdr.iter() + .find(|sh| { + let Some(name_idx) =3D strhdr + .sh_offset + .checked_add(u64::from(sh.sh_name)) + .and_then(|idx| usize::try_from(idx).ok()) + else { + return false; + }; + + // Get the start of the name. + elf.get(name_idx..) + // Stop at the first `0`. + .and_then(|nstr| nstr.get(0..=3Dnstr.iter().position(|= b| *b =3D=3D 0)?)) + // Convert into CStr. This should never fail because o= f the line above. + .and_then(|nstr| CStr::from_bytes_with_nul(nstr).ok()) + // Convert into str. + .and_then(|c_str| c_str.to_str().ok()) + // Check that the name matches. + .map(|str| str =3D=3D name) + .unwrap_or(false) + }) + // Return the slice containing the section. + .and_then(|sh| { + let start =3D usize::try_from(sh.sh_offset).ok()?; + let end =3D usize::try_from(sh.sh_size) + .ok() + .and_then(|sh_size| start.checked_add(sh_size))?; + + elf.get(start..end) + }) + } +} + /// Structure encapsulating the firmware blobs required for the GPU to ope= rate. #[expect(dead_code)] pub(crate) struct Firmware { @@ -36,7 +123,10 @@ pub(crate) struct Firmware { booter_unloader: BooterFirmware, /// GSP bootloader, verifies the GSP firmware before loading and runni= ng it. gsp_bootloader: RiscvFirmware, - gsp: firmware::Firmware, + /// GSP firmware. + gsp: Pin>, + /// GSP signatures, to be passed as parameter to the bootloader for va= lidation. + gsp_sigs: DmaObject, } =20 impl Firmware { @@ -56,13 +146,27 @@ pub(crate) fn new( .and_then(|path| firmware::Firmware::request(&path, dev)) }; =20 + let gsp_fw =3D request("gsp")?; + let gsp =3D elf::elf64_section(gsp_fw.data(), ".fwimage") + .ok_or(EINVAL) + .map(|data| GspFirmware::new(dev, data))?; + + let gsp_sigs_section =3D match chipset.arch() { + Architecture::Ampere =3D> ".fwsignature_ga10x", + _ =3D> return Err(ENOTSUPP), + }; + let gsp_sigs =3D elf::elf64_section(gsp_fw.data(), gsp_sigs_sectio= n) + .ok_or(EINVAL) + .and_then(|data| DmaObject::from_data(dev, data))?; + Ok(Firmware { booter_loader: request("booter_load") .and_then(|fw| BooterFirmware::new(dev, &fw, sec2, bar))?, booter_unloader: request("booter_unload") .and_then(|fw| BooterFirmware::new(dev, &fw, sec2, bar))?, gsp_bootloader: request("bootloader").and_then(|fw| RiscvFirmw= are::new(dev, &fw))?, - gsp: request("gsp")?, + gsp: KBox::pin_init(gsp, GFP_KERNEL)?, + gsp_sigs, }) } } diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/= firmware/gsp.rs new file mode 100644 index 0000000000000000000000000000000000000000..f37bd619bfb71629ed86ee8b782= 8971bbe4c5916 --- /dev/null +++ b/drivers/gpu/nova-core/firmware/gsp.rs @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::device; +use kernel::dma::DataDirection; +use kernel::dma::DmaAddress; +use kernel::prelude::*; +use kernel::scatterlist::Owned; +use kernel::scatterlist::SGTable; + +use crate::dma::DmaObject; +use crate::gsp::GSP_PAGE_SIZE; + +/// A device-mapped firmware with a set of (also device-mapped) pages tabl= es mapping the firmware +/// to the start of their own address space, also known as a `Radix3` firm= ware. +#[pin_data] +pub(crate) struct GspFirmware { + /// The GSP firmware inside a [`VVec`], device-mapped via a SG table. + #[pin] + fw: SGTable>>, + /// The level 2 page table, mapping [`Self::fw`] at its beginning. + #[pin] + lvl2: SGTable>>, + /// The level 1 page table, mapping [`Self::lvl2`] at its beginning. + #[pin] + lvl1: SGTable>>, + /// The level 0 page table, mapping [`Self::lvl1`] at its beginning. + lvl0: DmaObject, + /// Size in bytes of the firmware contained in [`Self::fw`]. + pub size: usize, +} + +impl GspFirmware { + /// Maps the GSP firmware image `fw` into `dev`'s address-space, and c= reates the page tables + /// expected by the GSP bootloader to load it. + pub(crate) fn new<'a>( + dev: &'a device::Device, + fw: &'a [u8], + ) -> impl PinInit + 'a { + try_pin_init!(&this in Self { + fw <- { + // Move the firmware into a vmalloc'd vector and map it in= to the device address + // space. + VVec::with_capacity(fw.len(), GFP_KERNEL) + .and_then(|mut v| { + v.extend_from_slice(fw, GFP_KERNEL)?; + Ok(v) + }) + .map_err(|_| ENOMEM) + .map(|v| SGTable::new(dev, v, DataDirection::ToDevice, GFP= _KERNEL))? + }, + lvl2 <- { + // Allocate the level 2 page table, map the firmware onto = it, and map it into the + // device address space. + // SAFETY: `this` is a valid pointer, and `fw` has been in= itialized. + let fw_sg_table =3D unsafe { &(*this.as_ptr()).fw }; + VVec::::with_capacity( + fw_sg_table.iter().count() * core::mem::size_of::= (), + GFP_KERNEL, + ) + .map_err(|_| ENOMEM) + .and_then(|lvl2| map_into_lvl(fw_sg_table, lvl2)) + .map(|lvl2| SGTable::new(dev, lvl2, DataDirection::ToDevic= e, GFP_KERNEL))? + }, + lvl1 <- { + // Allocate the level 1 page table, map the level 2 page t= able onto it, and map it + // into the device address space. + // SAFETY: `this` is a valid pointer, and `lvl2` has been = initialized. + let lvl2_sg_table =3D unsafe { &(*this.as_ptr()).lvl2 }; + VVec::::with_capacity( + lvl2_sg_table.iter().count() * core::mem::size_of::(), + GFP_KERNEL, + ) + .map_err(|_| ENOMEM) + .and_then(|lvl1| map_into_lvl(lvl2_sg_table, lvl1)) + .map(|lvl1| SGTable::new(dev, lvl1, DataDirection::ToDevic= e, GFP_KERNEL))? + }, + lvl0: { + // Allocate the level 0 page table as a device-visible DMA= object, and map the + // level 1 page table onto it. + // SAFETY: `this` is a valid pointer, and `lvl1` has been = initialized. + let lvl1_sg_table =3D unsafe { &(*this.as_ptr()).lvl1 }; + let mut lvl0 =3D DmaObject::new(dev, GSP_PAGE_SIZE)?; + // SAFETY: we are the only owner of this newly-created obj= ect, making races + // impossible. + let lvl0_slice =3D unsafe { lvl0.as_slice_mut(0, GSP_PAGE_= SIZE) }?; + lvl0_slice[0..core::mem::size_of::()].copy_from_slice( + #[allow(clippy::useless_conversion)] + &(u64::from(lvl1_sg_table.iter().next().unwrap().dma_a= ddress())).to_le_bytes(), + ); + + lvl0 + }, + size: fw.len(), + }) + } + + #[expect(unused)] + /// Returns the DMA handle of the level 0 page table. + pub(crate) fn lvl0_dma_handle(&self) -> DmaAddress { + self.lvl0.dma_handle() + } +} + +/// Create a linear mapping the device mapping of the buffer described by = `sg_table` into `dst`. +fn map_into_lvl(sg_table: &SGTable>>, mut dst: VVec) ->= Result> { + for sg_entry in sg_table.iter() { + // Number of pages we need to map. + let num_pages =3D (sg_entry.dma_len() as usize).div_ceil(GSP_PAGE_= SIZE); + + for i in 0..num_pages { + let entry =3D sg_entry.dma_address() + (i as u64 * GSP_PAGE_SI= ZE as u64); + dst.extend_from_slice(&entry.to_le_bytes(), GFP_KERNEL)?; + } + } + + Ok(dst) +} diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs new file mode 100644 index 0000000000000000000000000000000000000000..a0e7ec5f6c9c959d57540b3ebf4= b782f2e002b08 --- /dev/null +++ b/drivers/gpu/nova-core/gsp.rs @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 + +pub(crate) const GSP_PAGE_SHIFT: usize =3D 12; +pub(crate) const GSP_PAGE_SIZE: usize =3D 1 << GSP_PAGE_SHIFT; diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index cb2bbb30cba142265b354c9acf70349a6e40759e..fffcaee2249fe6cd7f55a7291c1= e44be42e791d9 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -9,6 +9,7 @@ mod firmware; mod gfw; mod gpu; +mod gsp; mod regs; mod util; mod vbios; --=20 2.50.1 From nobody Fri Oct 3 20:25:47 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2068.outbound.protection.outlook.com [40.107.92.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2756A2D738B; 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It should eventually be dropped for a newer version before the driver becomes able to do anything useful. The newer firmware is expected to iron out some of the inelegances of 570.144, notably related to packaging. Signed-off-by: Alexandre Courbot Reviewed-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index fb751287e938e6a323db185ff8c4ba2781d25285..f296dee224e48b2a4e20d06f8b3= 6d8d1e5f08c53 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -27,7 +27,7 @@ pub(crate) mod gsp; pub(crate) mod riscv; =20 -pub(crate) const FIRMWARE_VERSION: &str =3D "535.113.01"; +pub(crate) const FIRMWARE_VERSION: &str =3D "570.144"; =20 /// Ad-hoc and temporary module to extract sections from ELF images. /// --=20 2.50.1 From nobody Fri Oct 3 20:25:47 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2064.outbound.protection.outlook.com [40.107.92.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 270842D7D35; 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Rust definitions for the types needed for Nova core will be generated using the Rust bindgen tool. This patch adds the base module to allow inclusion of the generated bindings. The generated bindings themselves are added by subsequent patches when they are first used. Currently we only intend to support a single firmware version, 570.144, with these bindings. Longer term we intend to move to a more stable GSP interface that isn't tied to specific firmware versions. [acourbot@nvidia.com: adapt the bindings module comment a bit.] Signed-off-by: Alistair Popple Signed-off-by: Alexandre Courbot Reviewed-by: John Hubbard --- drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/nvfw.rs | 3 +++ drivers/gpu/nova-core/nvfw/r570_144.rs | 29 +++++++++++++++++++++= ++++ drivers/gpu/nova-core/nvfw/r570_144_bindings.rs | 1 + 4 files changed, 34 insertions(+) diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index fffcaee2249fe6cd7f55a7291c1e44be42e791d9..db197498b0b7b1ff9234ef6645a= 4ea5ff44bd285 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -10,6 +10,7 @@ mod gfw; mod gpu; mod gsp; +mod nvfw; mod regs; mod util; mod vbios; diff --git a/drivers/gpu/nova-core/nvfw.rs b/drivers/gpu/nova-core/nvfw.rs new file mode 100644 index 0000000000000000000000000000000000000000..7c5baccc34a2387c30e51f93d3a= e039b14b6b83a --- /dev/null +++ b/drivers/gpu/nova-core/nvfw.rs @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0 + +mod r570_144; diff --git a/drivers/gpu/nova-core/nvfw/r570_144.rs b/drivers/gpu/nova-core= /nvfw/r570_144.rs new file mode 100644 index 0000000000000000000000000000000000000000..2e7bba80fa8b9c5fcb4e2688782= 5d2cca3f7b6b7 --- /dev/null +++ b/drivers/gpu/nova-core/nvfw/r570_144.rs @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Firmware bindings. +//! +//! Imports the generated bindings by `bindgen`. +//! +//! This module may not be directly used. Please abstract or re-export the= needed symbols in the +//! parent module instead. + +#![cfg_attr(test, allow(deref_nullptr))] +#![cfg_attr(test, allow(unaligned_references))] +#![cfg_attr(test, allow(unsafe_op_in_unsafe_fn))] +#![allow( + dead_code, + unused_imports, + clippy::all, + clippy::undocumented_unsafe_blocks, + clippy::ptr_as_ptr, + clippy::ref_as_ptr, + missing_docs, + non_camel_case_types, + non_upper_case_globals, + non_snake_case, + improper_ctypes, + unreachable_pub, + unsafe_op_in_unsafe_fn +)] +use kernel::ffi; +include!("r570_144_bindings.rs"); diff --git a/drivers/gpu/nova-core/nvfw/r570_144_bindings.rs b/drivers/gpu/= nova-core/nvfw/r570_144_bindings.rs new file mode 100644 index 0000000000000000000000000000000000000000..cec5940325151e407aa90128a35= cb683afd436d7 --- /dev/null +++ b/drivers/gpu/nova-core/nvfw/r570_144_bindings.rs @@ -0,0 +1 @@ +// SPDX-License-Identifier: GPL-2.0 --=20 2.50.1 From nobody Fri Oct 3 20:25:47 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2057.outbound.protection.outlook.com [40.107.92.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C1902D4B71; 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This information is dependent on the firmware itself, so first we need to import and abstract the required firmware bindings in the `nvfw` module. Then, a new FB HAL method is introduced in `fb::hal` that uses these bindings and hardware information to compute the correct layout information. This information is then used in `fb` and the result made visible in `FbLayout`. These 3 things are grouped into the same patch to avoid lots of unused warnings that would be tedious to work around. As they happen in different files, they should not be too difficult to track separately. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/fb.rs | 112 ++++++++++++++++++++- drivers/gpu/nova-core/fb/hal.rs | 4 + drivers/gpu/nova-core/fb/hal/ga100.rs | 6 +- drivers/gpu/nova-core/fb/hal/ga102.rs | 14 ++- drivers/gpu/nova-core/fb/hal/tu102.rs | 14 +++ drivers/gpu/nova-core/firmware.rs | 4 +- drivers/gpu/nova-core/firmware/riscv.rs | 2 +- drivers/gpu/nova-core/gpu.rs | 2 +- drivers/gpu/nova-core/gsp.rs | 3 + drivers/gpu/nova-core/nvfw.rs | 39 ++++++++ drivers/gpu/nova-core/nvfw/r570_144.rs | 1 - drivers/gpu/nova-core/nvfw/r570_144_bindings.rs | 125 ++++++++++++++++++++= ++++ 12 files changed, 317 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index b0e860498b883815b3861b8717f8ee1832d25440..a3eb063f86b3a06a7ad01e68491= 9115abf5e28da 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -10,7 +10,11 @@ =20 use crate::dma::DmaObject; use crate::driver::Bar0; +use crate::firmware::gsp::GspFirmware; +use crate::firmware::riscv::RiscvFirmware; use crate::gpu::Chipset; +use crate::gsp::GSP_HEAP_ALIGNMENT; +use crate::nvfw::{self, LibosParams}; use crate::regs; =20 mod hal; @@ -81,20 +85,80 @@ pub(crate) fn unregister(&self, bar: &Bar0) { } } =20 +/// Heap memory requirements for the GSP firmware. +pub(crate) struct GspFwHeapParams { + /// Libos parameters in effect. + pub libos: &'static LibosParams, + /// The amount of heap memory used by GSP-RM boot and initialization, = up and including the + /// first client subdevice allocation, in bytes. + pub base_rm_size: u64, +} + +impl GspFwHeapParams { + /// Returns the amount of memory (in bytes) to allocate for the WPR he= ap for a framebuffer size + /// of `fb_size` (in bytes). + /// + /// Returns `EOVERFLOW` if the computation overflows. + pub(crate) fn wpr_heap_size(&self, fb_size: u64) -> Result { + let fb_size_gb =3D fb_size.div_ceil(SZ_1G as u64); + + // The WPR heap will contain the following: + let size =3D + // LIBOS carveout, + self.libos.carveout_size + // RM boot working memory, + + self.base_rm_size + // One RM client, + + u64::from(nvfw::GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE) + .align_up(GSP_HEAP_ALIGNMENT) + .ok_or(EOVERFLOW)? + // Overhead for memory management. + + u64::from(nvfw::GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB) + .checked_mul(fb_size_gb) + .and_then(|heap_size| heap_size.align_up(GSP_HEAP_ALIGNMEN= T)) + .ok_or(EOVERFLOW)?; + + // Clamp to the supported heap sizes. + Ok(size.clamp( + self.libos.allowed_heap_size.start, + self.libos.allowed_heap_size.end - 1, + )) + } +} + /// Layout of the GPU framebuffer memory. /// /// Contains ranges of GPU memory reserved for a given purpose during the = GSP boot process. #[derive(Debug)] #[expect(dead_code)] pub(crate) struct FbLayout { + /// Range of the framebuffer. Starts at `0`. pub(crate) fb: Range, + /// VGA workspace, small area of reserved memory at the end of the fra= mebuffer. pub(crate) vga_workspace: Range, + /// FRTS range. pub(crate) frts: Range, + /// Memory area containing the GSP bootloader image. + pub(crate) boot: Range, + /// Memory area containing the GSP firmware image. + pub(crate) elf: Range, + /// WPR2 heap. + pub(crate) wpr2_heap: Range, + // WPR2 region range, starting with an instance of `GspFwWprMeta`. + pub(crate) wpr2: Range, + pub(crate) heap: Range, + pub(crate) vf_partition_count: u8, } =20 impl FbLayout { - /// Computes the FB layout. - pub(crate) fn new(chipset: Chipset, bar: &Bar0) -> Result { + /// Computes the FB layout for `chipset`, for running the `bl` GSP boo= tloader and `gsp` GSP + /// firmware. + pub(crate) fn new( + chipset: Chipset, + bar: &Bar0, + bl: &RiscvFirmware, + gsp: &GspFirmware, + ) -> Result { let hal =3D hal::fb_hal(chipset); =20 let fb =3D { @@ -138,10 +202,54 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0) -> Re= sult { frts_base..frts_base + FRTS_SIZE }; =20 + let boot =3D { + const BOOTLOADER_DOWN_ALIGN: Alignment =3D Alignment::new(SZ_4= K); + let bootloader_size =3D bl.ucode.size() as u64; + let bootloader_base =3D (frts.start - bootloader_size).align_d= own(BOOTLOADER_DOWN_ALIGN); + + bootloader_base..bootloader_base + bootloader_size + }; + + let elf =3D { + const ELF_DOWN_ALIGN: Alignment =3D Alignment::new(SZ_64K); + let elf_size =3D gsp.size as u64; + let elf_addr =3D (boot.start - elf_size).align_down(ELF_DOWN_A= LIGN); + + elf_addr..elf_addr + elf_size + }; + + let wpr2_heap =3D { + const WPR2_HEAP_DOWN_ALIGN: Alignment =3D Alignment::new(SZ_1M= ); + let wpr2_heap_size =3D hal.heap_params().wpr_heap_size(fb.end)= ?; + let wpr2_heap_addr =3D (elf.start - wpr2_heap_size).align_down= (WPR2_HEAP_DOWN_ALIGN); + + wpr2_heap_addr..(elf.start).align_down(WPR2_HEAP_DOWN_ALIGN) + }; + + let wpr2 =3D { + const WPR2_DOWN_ALIGN: Alignment =3D Alignment::new(SZ_1M); + let wpr2_addr =3D (wpr2_heap.start - size_of::() as u64) + .align_down(WPR2_DOWN_ALIGN); + + wpr2_addr..frts.end + }; + + let heap =3D { + const HEAP_SIZE: u64 =3D SZ_1M as u64; + + wpr2.start - HEAP_SIZE..wpr2.start + }; + Ok(Self { fb, vga_workspace, frts, + boot, + elf, + wpr2_heap, + wpr2, + heap, + vf_partition_count: 0, }) } } diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index 2f914948bb9a9842fd00a4c6381420b74de81c3f..2bfde29dd3602dd150fb6bdb110= 72d000a32fec8 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -3,6 +3,7 @@ use kernel::prelude::*; =20 use crate::driver::Bar0; +use crate::fb::GspFwHeapParams; use crate::gpu::Chipset; =20 mod ga100; @@ -23,6 +24,9 @@ pub(crate) trait FbHal { =20 /// Returns the VRAM size, in bytes. fn vidmem_size(&self, bar: &Bar0) -> u64; + + /// Returns the heap memory requirements to start the GSP firmware. + fn heap_params(&self) -> GspFwHeapParams; } =20 /// Returns the HAL corresponding to `chipset`. diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/= fb/hal/ga100.rs index 871c42bf033acd0b9c5735c43d408503075099af..19fc4862f3d88c91d741aa951fa= a24703aa1d1e9 100644 --- a/drivers/gpu/nova-core/fb/hal/ga100.rs +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs @@ -5,7 +5,7 @@ use kernel::prelude::*; =20 use crate::driver::Bar0; -use crate::fb::hal::FbHal; +use crate::fb::hal::{FbHal, GspFwHeapParams}; use crate::regs; =20 use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT; @@ -51,6 +51,10 @@ fn supports_display(&self, bar: &Bar0) -> bool { fn vidmem_size(&self, bar: &Bar0) -> u64 { super::tu102::vidmem_size_gp102(bar) } + + fn heap_params(&self) -> GspFwHeapParams { + super::tu102::heap_params_tu102() + } } =20 const GA100: Ga100 =3D Ga100; diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-core/= fb/hal/ga102.rs index a73b77e3971513d088211a97ad8e50b00a9131f7..4b93fde8357d81c636eb6352875= 0ec600fa77443 100644 --- a/drivers/gpu/nova-core/fb/hal/ga102.rs +++ b/drivers/gpu/nova-core/fb/hal/ga102.rs @@ -3,13 +3,21 @@ use kernel::prelude::*; =20 use crate::driver::Bar0; -use crate::fb::hal::FbHal; +use crate::fb::hal::{FbHal, GspFwHeapParams}; +use crate::nvfw; use crate::regs; =20 fn vidmem_size_ga102(bar: &Bar0) -> u64 { regs::NV_USABLE_FB_SIZE_IN_MB::read(bar).usable_fb_size() } =20 +fn heap_params_ga102() -> GspFwHeapParams { + GspFwHeapParams { + libos: &nvfw::LIBOS3_PARAMS, + ..super::tu102::heap_params_tu102() + } +} + struct Ga102; =20 impl FbHal for Ga102 { @@ -30,6 +38,10 @@ fn supports_display(&self, bar: &Bar0) -> bool { fn vidmem_size(&self, bar: &Bar0) -> u64 { vidmem_size_ga102(bar) } + + fn heap_params(&self) -> GspFwHeapParams { + heap_params_ga102() + } } =20 const GA102: Ga102 =3D Ga102; diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/= fb/hal/tu102.rs index b022c781caf4514b4060fa2083cdc0ca12573c5b..441f1dc0e5163ea7612b7b95092= 4918cdb6cb5c0 100644 --- a/drivers/gpu/nova-core/fb/hal/tu102.rs +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs @@ -2,7 +2,10 @@ =20 use crate::driver::Bar0; use crate::fb::hal::FbHal; +use crate::fb::hal::GspFwHeapParams; +use crate::nvfw; use crate::regs; + use kernel::prelude::*; =20 /// Shift applied to the sysmem address before it is written into `NV_PFB_= NISO_FLUSH_SYSMEM_ADDR`, @@ -34,6 +37,13 @@ pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 { regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE::read(bar).usable_fb_size() } =20 +pub(super) fn heap_params_tu102() -> GspFwHeapParams { + GspFwHeapParams { + libos: &nvfw::LIBOS2_PARAMS, + base_rm_size: u64::from(nvfw::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X= ), + } +} + struct Tu102; =20 impl FbHal for Tu102 { @@ -52,6 +62,10 @@ fn supports_display(&self, bar: &Bar0) -> bool { fn vidmem_size(&self, bar: &Bar0) -> u64 { vidmem_size_gp102(bar) } + + fn heap_params(&self) -> GspFwHeapParams { + heap_params_tu102() + } } =20 const TU102: Tu102 =3D Tu102; diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index f296dee224e48b2a4e20d06f8b36d8d1e5f08c53..05e57730a3c6fa3d3415c6073de= 55d1ff1b3b40a 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -122,9 +122,9 @@ pub(crate) struct Firmware { /// Runs on the sec2 falcon engine to stop and unload a running GSP fi= rmware. booter_unloader: BooterFirmware, /// GSP bootloader, verifies the GSP firmware before loading and runni= ng it. - gsp_bootloader: RiscvFirmware, + pub gsp_bootloader: RiscvFirmware, /// GSP firmware. - gsp: Pin>, + pub gsp: Pin>, /// GSP signatures, to be passed as parameter to the bootloader for va= lidation. gsp_sigs: DmaObject, } diff --git a/drivers/gpu/nova-core/firmware/riscv.rs b/drivers/gpu/nova-cor= e/firmware/riscv.rs index 926883230f2fe4e3327713e28b7fae31ebee60bb..b2f646c1f02c6d1c5a28e688c6d= 2d0684b3f31be 100644 --- a/drivers/gpu/nova-core/firmware/riscv.rs +++ b/drivers/gpu/nova-core/firmware/riscv.rs @@ -61,7 +61,7 @@ pub(crate) struct RiscvFirmware { /// Application version. app_version: u32, /// Device-mapped firmware image. - ucode: DmaObject, + pub ucode: DmaObject, } =20 impl RiscvFirmware { diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 54f0e9fd587ae5c4c045096930c0548fb1ef1b86..5c1c88086cb0dae3ae3547aeb0e= 15332f1d854df 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -302,7 +302,7 @@ pub(crate) fn new( FIRMWARE_VERSION, )?; =20 - let fb_layout =3D FbLayout::new(spec.chipset, bar)?; + let fb_layout =3D FbLayout::new(spec.chipset, bar, &fw.gsp_bootloa= der, &fw.gsp)?; dev_dbg!(pdev.as_ref(), "{:#x?}\n", fb_layout); =20 let bios =3D Vbios::new(pdev, bar)?; diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index a0e7ec5f6c9c959d57540b3ebf4b782f2e002b08..ead471746ccad02f1e0d6ec114a= b2aa67b1ed733 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 +use kernel::ptr::Alignment; + pub(crate) const GSP_PAGE_SHIFT: usize =3D 12; pub(crate) const GSP_PAGE_SIZE: usize =3D 1 << GSP_PAGE_SHIFT; +pub(crate) const GSP_HEAP_ALIGNMENT: Alignment =3D Alignment::new(1 << 20); diff --git a/drivers/gpu/nova-core/nvfw.rs b/drivers/gpu/nova-core/nvfw.rs index 7c5baccc34a2387c30e51f93d3ae039b14b6b83a..11a63c3710b1aa1eec78359c15c= 101bdf2ad99c8 100644 --- a/drivers/gpu/nova-core/nvfw.rs +++ b/drivers/gpu/nova-core/nvfw.rs @@ -1,3 +1,42 @@ // SPDX-License-Identifier: GPL-2.0 =20 mod r570_144; + +use core::ops::Range; + +use kernel::sizes::SZ_1M; + +/// Heap memory requirements and constraints for a given version of the GS= P LIBOS. +pub(crate) struct LibosParams { + /// The base amount of heap required by the GSP operating system, in b= ytes. + pub(crate) carveout_size: u64, + /// The minimum and maximum sizes allowed for the GSP FW heap, in byte= s. + pub(crate) allowed_heap_size: Range, +} + +/// Version 2 of the GSP LIBOS (Turing and GA100) +pub(crate) const LIBOS2_PARAMS: LibosParams =3D LibosParams { + carveout_size: r570_144::GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2 as u64, + allowed_heap_size: r570_144::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB a= s u64 * SZ_1M as u64 + ..r570_144::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB as u64 * SZ_1M= as u64, +}; + +/// Version 3 of the GSP LIBOS (GA102+) +pub(crate) const LIBOS3_PARAMS: LibosParams =3D LibosParams { + carveout_size: r570_144::GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL as= u64, + allowed_heap_size: r570_144::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETA= L_MIN_MB as u64 + * SZ_1M as u64 + ..r570_144::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB as u= 64 * SZ_1M as u64, +}; + +/// Amount of GSP-RM heap memory used during GSP-RM boot and initializatio= n (up to and including +/// the first client subdevice allocation) on Turing/Ampere/Ada. +pub(crate) use r570_144::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X; +/// WPR heap usage of a single client channel allocation. +pub(crate) use r570_144::GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE; +/// Amount of extra WPR heap to reserve per GB of framebuffer memory, in b= ytes. +pub(crate) use r570_144::GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB; + +/// Structure passed to the GSP bootloader, containing the framebuffer lay= out as well as the DMA +/// addresses of the GSP bootloader and firmware. +pub(crate) use r570_144::GspFwWprMeta; diff --git a/drivers/gpu/nova-core/nvfw/r570_144.rs b/drivers/gpu/nova-core= /nvfw/r570_144.rs index 2e7bba80fa8b9c5fcb4e26887825d2cca3f7b6b7..bb8074797b550c7976a7432b418= 41c6bf61bf5f8 100644 --- a/drivers/gpu/nova-core/nvfw/r570_144.rs +++ b/drivers/gpu/nova-core/nvfw/r570_144.rs @@ -12,7 +12,6 @@ #![cfg_attr(test, allow(unsafe_op_in_unsafe_fn))] #![allow( dead_code, - unused_imports, clippy::all, clippy::undocumented_unsafe_blocks, clippy::ptr_as_ptr, diff --git a/drivers/gpu/nova-core/nvfw/r570_144_bindings.rs b/drivers/gpu/= nova-core/nvfw/r570_144_bindings.rs index cec5940325151e407aa90128a35cb683afd436d7..0407000cca2296e713cc4701b63= 5718fe51488cb 100644 --- a/drivers/gpu/nova-core/nvfw/r570_144_bindings.rs +++ b/drivers/gpu/nova-core/nvfw/r570_144_bindings.rs @@ -1 +1,126 @@ // SPDX-License-Identifier: GPL-2.0 + +pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2: u32 =3D 0; +pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL: u32 =3D 23068672; +pub const GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X: u32 =3D 8388608; +pub const GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB: u32 =3D 98304; +pub const GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE: u32 =3D 100663296; +pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB: u32 =3D 64; +pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB: u32 =3D 256; +pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB: u32 =3D 88; +pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB: u32 =3D 280; +pub type __u8 =3D ffi::c_uchar; +pub type __u16 =3D ffi::c_ushort; +pub type __u32 =3D ffi::c_uint; +pub type __u64 =3D ffi::c_ulonglong; +pub type u8_ =3D __u8; +pub type u16_ =3D __u16; +pub type u32_ =3D __u32; +pub type u64_ =3D __u64; +#[repr(C)] +#[derive(Copy, Clone)] +pub struct GspFwWprMeta { + pub magic: u64_, + pub revision: u64_, + pub sysmemAddrOfRadix3Elf: u64_, + pub sizeOfRadix3Elf: u64_, + pub sysmemAddrOfBootloader: u64_, + pub sizeOfBootloader: u64_, + pub bootloaderCodeOffset: u64_, + pub bootloaderDataOffset: u64_, + pub bootloaderManifestOffset: u64_, + pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_1, + pub gspFwRsvdStart: u64_, + pub nonWprHeapOffset: u64_, + pub nonWprHeapSize: u64_, + pub gspFwWprStart: u64_, + pub gspFwHeapOffset: u64_, + pub gspFwHeapSize: u64_, + pub gspFwOffset: u64_, + pub bootBinOffset: u64_, + pub frtsOffset: u64_, + pub frtsSize: u64_, + pub gspFwWprEnd: u64_, + pub fbSize: u64_, + pub vgaWorkspaceOffset: u64_, + pub vgaWorkspaceSize: u64_, + pub bootCount: u64_, + pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_2, + pub gspFwHeapVfPartitionCount: u8_, + pub flags: u8_, + pub padding: [u8_; 2usize], + pub pmuReservedSize: u32_, + pub verified: u64_, +} +#[repr(C)] +#[derive(Copy, Clone)] +pub union GspFwWprMeta__bindgen_ty_1 { + pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_1__bindgen_ty_1, + pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_1__bindgen_ty_2, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GspFwWprMeta__bindgen_ty_1__bindgen_ty_1 { + pub sysmemAddrOfSignature: u64_, + pub sizeOfSignature: u64_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GspFwWprMeta__bindgen_ty_1__bindgen_ty_2 { + pub gspFwHeapFreeListWprOffset: u32_, + pub unused0: u32_, + pub unused1: u64_, +} +impl Default for GspFwWprMeta__bindgen_ty_1 { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +#[repr(C)] +#[derive(Copy, Clone)] +pub union GspFwWprMeta__bindgen_ty_2 { + pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_2__bindgen_ty_1, + pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_2__bindgen_ty_2, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GspFwWprMeta__bindgen_ty_2__bindgen_ty_1 { + pub partitionRpcAddr: u64_, + pub partitionRpcRequestOffset: u16_, + pub partitionRpcReplyOffset: u16_, + pub elfCodeOffset: u32_, + pub elfDataOffset: u32_, + pub elfCodeSize: u32_, + pub elfDataSize: u32_, + pub lsUcodeVersion: u32_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GspFwWprMeta__bindgen_ty_2__bindgen_ty_2 { + pub partitionRpcPadding: [u32_; 4usize], + pub sysmemAddrOfCrashReportQueue: u64_, + pub sizeOfCrashReportQueue: u32_, + pub lsUcodeVersionPadding: [u32_; 1usize], +} +impl Default for GspFwWprMeta__bindgen_ty_2 { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +impl Default for GspFwWprMeta { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} --=20 2.50.1