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Tue, 26 Aug 2025 11:21:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGqTO7Pu0wOsLUCAduferZquK+24b2fZ5cpErQjBpKf3mge15QU2OPVpb0Li9cR7UXqWFEfvg== X-Received: by 2002:a05:6a20:938e:b0:243:15b9:7662 with SMTP id adf61e73a8af0-24340d6e2d0mr23095093637.60.1756232498783; Tue, 26 Aug 2025 11:21:38 -0700 (PDT) Received: from hu-wasimn-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77048989fe6sm9881803b3a.51.2025.08.26.11.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 11:21:38 -0700 (PDT) From: Wasim Nazir Date: Tue, 26 Aug 2025 23:51:02 +0530 Subject: [PATCH 3/5] arm64: dts: qcom: lemans-evk: Extend peripheral and subsystem support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-lemans-evk-bu-v1-3-08016e0d3ce5@oss.qualcomm.com> References: <20250826-lemans-evk-bu-v1-0-08016e0d3ce5@oss.qualcomm.com> In-Reply-To: <20250826-lemans-evk-bu-v1-0-08016e0d3ce5@oss.qualcomm.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Richard Cochran Cc: kernel@oss.qualcomm.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, Viken Dadhaniya , Sushrut Shree Trivedi , Nirmesh Kumar Singh , Krishna Kurapati , Mohd Ayaan Anwar , Dikshita Agarwal , Monish Chunara , Vishal Kumar Pal , Wasim Nazir X-Mailer: b4 0.15-dev-e44bb X-Developer-Signature: v=1; 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It depends on CONFIG_QCA808X_PHY to use QCA8081 PHY. - Add support for the Iris video decoder, including the required firmware, to enable video decoding capabilities. - Enable SD-card slot on SDHC. Co-developed-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya Co-developed-by: Sushrut Shree Trivedi Signed-off-by: Sushrut Shree Trivedi Co-developed-by: Nirmesh Kumar Singh Signed-off-by: Nirmesh Kumar Singh Co-developed-by: Krishna Kurapati Signed-off-by: Krishna Kurapati Co-developed-by: Mohd Ayaan Anwar Signed-off-by: Mohd Ayaan Anwar Co-developed-by: Dikshita Agarwal Signed-off-by: Dikshita Agarwal Co-developed-by: Monish Chunara Signed-off-by: Monish Chunara Co-developed-by: Vishal Kumar Pal Signed-off-by: Vishal Kumar Pal Signed-off-by: Wasim Nazir --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 387 ++++++++++++++++++++++++++++= ++++ 1 file changed, 387 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/= qcom/lemans-evk.dts index 9e415012140b..642b66c4ad1e 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -16,7 +16,10 @@ / { compatible =3D "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p"; =20 aliases { + ethernet0 =3D ðernet0; + mmc1 =3D &sdhc; serial0 =3D &uart10; + serial1 =3D &uart17; }; =20 chosen { @@ -46,6 +49,30 @@ edp1_connector_in: endpoint { }; }; }; + + vmmc_sdc: regulator-vmmc-sdc { + compatible =3D "regulator-fixed"; + regulator-name =3D "vmmc_sdc"; + + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <2950000>; + }; + + vreg_sdc: regulator-vreg-sdc { + compatible =3D "regulator-gpio"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + regulator-name =3D "vreg_sdc"; + regulator-type =3D "voltage"; + + startup-delay-us =3D <100>; + + gpios =3D <&expander1 7 GPIO_ACTIVE_HIGH>; + + states =3D <1800000 0x1 + 2950000 0x0>; + }; }; =20 &apps_rsc { @@ -277,6 +304,161 @@ vreg_l8e: ldo8 { }; }; =20 +ðernet0 { + phy-handle =3D <&hsgmii_phy0>; + phy-mode =3D "2500base-x"; + + pinctrl-0 =3D <ðernet0_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,ps-speed =3D <1000>; + + nvmem-cells =3D <&mac_addr0>; + nvmem-cell-names =3D "mac-address"; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible =3D "ethernet-phy-id004d.d101"; + reg =3D <0x1c>; + reset-gpios =3D <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpi_dma2 { + status =3D "okay"; +}; + +&i2c18 { + status =3D "okay"; + + expander0: pca953x@38 { + compatible =3D "ti,tca9538"; + #gpio-cells =3D <2>; + gpio-controller; + reg =3D <0x38>; + }; + + expander1: pca953x@39 { + compatible =3D "ti,tca9538"; + #gpio-cells =3D <2>; + gpio-controller; + reg =3D <0x39>; + }; + + expander2: pca953x@3a { + compatible =3D "ti,tca9538"; + #gpio-cells =3D <2>; + gpio-controller; + reg =3D <0x3a>; + }; + + expander3: pca953x@3b { + compatible =3D "ti,tca9538"; + #gpio-cells =3D <2>; + gpio-controller; + reg =3D <0x3b>; + }; + + eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + pagesize =3D <64>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mac_addr0: mac-addr@0 { + reg =3D <0x0 0x6>; + }; + }; + }; +}; + +&iris { + firmware-name =3D "qcom/vpu/vpu30_p4_s6.mbn"; + + status =3D "okay"; +}; + &mdss0 { status =3D "okay"; }; @@ -323,14 +505,196 @@ &mdss0_dp1_phy { status =3D "okay"; }; =20 +&pcie0 { + perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_default_state>; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l1c>; + + status =3D "okay"; +}; + +&pcie1 { + perst-gpios =3D <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_default_state>; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l1c>; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + &qupv3_id_1 { status =3D "okay"; }; =20 +&qupv3_id_2 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sa8775p/adsp.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp0 { + firmware-name =3D "qcom/sa8775p/cdsp0.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp1 { + firmware-name =3D "qcom/sa8775p/cdsp1.mbn"; + + status =3D "okay"; +}; + +&remoteproc_gpdsp0 { + firmware-name =3D "qcom/sa8775p/gpdsp0.mbn"; + + status =3D "okay"; +}; + +&remoteproc_gpdsp1 { + firmware-name =3D "qcom/sa8775p/gpdsp1.mbn"; + + status =3D "okay"; +}; + +&sdhc { + vmmc-supply =3D <&vmmc_sdc>; + vqmmc-supply =3D <&vreg_sdc>; + + pinctrl-0 =3D <&sdc_default>, <&sd_cd>; + pinctrl-1 =3D <&sdc_sleep>, <&sd_cd>; + pinctrl-names =3D "default", "sleep"; + + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&sdhc_opp_table>; + + cd-gpios =3D <&tlmm 36 GPIO_ACTIVE_LOW>; + + status =3D "okay"; + + sdhc_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1800000 400000>; + opp-avg-kBps =3D <100000 0>; + }; + + opp-384000000 { + opp-hz =3D /bits/ 64 <384000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <5400000 1600000>; + opp-avg-kBps =3D <390000 0>; + }; + }; +}; + +&serdes0 { + phy-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + &sleep_clk { clock-frequency =3D <32768>; }; =20 +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins =3D "gpio8"; + function =3D "emac0_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins =3D "gpio9"; + function =3D "emac0_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + + pcie0_default_state: pcie0-default-state { + clkreq-pins { + pins =3D "gpio1"; + function =3D "pcie0_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + wake-pins { + pins =3D "gpio0"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + clkreq-pins { + pins =3D "gpio3"; + function =3D "pcie1_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio4"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + wake-pins { + pins =3D "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + sd_cd: sd-cd-state { + pins =3D "gpio36"; + function =3D "gpio"; + bias-pull-up; + }; +}; + &uart10 { compatible =3D "qcom,geni-debug-uart"; pinctrl-0 =3D <&qup_uart10_default>; @@ -356,6 +720,29 @@ &ufs_mem_phy { status =3D "okay"; }; =20 +&usb_0 { + status =3D "okay"; +}; + +&usb_0_dwc3 { + dr_mode =3D "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply =3D <&vreg_l7a>; + vdda18-supply =3D <&vreg_l6c>; + vdda33-supply =3D <&vreg_l9a>; + + status =3D "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply =3D <&vreg_l1c>; + vdda-pll-supply =3D <&vreg_l7a>; + + status =3D "okay"; +}; + &xo_board_clk { clock-frequency =3D <38400000>; }; --=20 2.51.0