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Tue, 26 Aug 2025 02:35:16 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 26 Aug 2025 11:35:06 +0200 Subject: [PATCH 05/12] gpio: mlxbf2: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250826-gpio-mmio-gpio-conv-part2-v1-5-f67603e4b27e@linaro.org> References: <20250826-gpio-mmio-gpio-conv-part2-v1-0-f67603e4b27e@linaro.org> In-Reply-To: <20250826-gpio-mmio-gpio-conv-part2-v1-0-f67603e4b27e@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Ray Jui , Scott Branden , Broadcom internal kernel review list , Yang Shen , Nobuhiro Iwamatsu Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-mlxbf2.c | 59 +++++++++++++++++++++++-------------------= ---- 1 file changed, 30 insertions(+), 29 deletions(-) diff --git a/drivers/gpio/gpio-mlxbf2.c b/drivers/gpio/gpio-mlxbf2.c index bc4bba8b567c2605a77d4f9d4d7d916e8b096569..f99f66cd189ca71c9d188dff0a0= b42ef2223abb3 100644 --- a/drivers/gpio/gpio-mlxbf2.c +++ b/drivers/gpio/gpio-mlxbf2.c @@ -6,8 +6,10 @@ =20 #include #include +#include #include #include +#include #include #include #include @@ -65,7 +67,7 @@ struct mlxbf2_gpio_context_save_regs { =20 /* BlueField-2 gpio block context structure. */ struct mlxbf2_gpio_context { - struct gpio_chip gc; + struct gpio_generic_chip chip; =20 /* YU GPIO blocks address */ void __iomem *gpio_io; @@ -132,7 +134,7 @@ static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_= context *gs) u32 arm_gpio_lock_val; =20 mutex_lock(yu_arm_gpio_lock_param.lock); - raw_spin_lock(&gs->gc.bgpio_lock); + gpio_generic_chip_lock(&gs->chip); =20 arm_gpio_lock_val =3D readl(yu_arm_gpio_lock_param.io); =20 @@ -140,7 +142,7 @@ static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_= context *gs) * When lock active bit[31] is set, ModeX is write enabled */ if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) { - raw_spin_unlock(&gs->gc.bgpio_lock); + gpio_generic_chip_unlock(&gs->chip); mutex_unlock(yu_arm_gpio_lock_param.lock); return -EINVAL; } @@ -154,11 +156,11 @@ static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpi= o_context *gs) * Release the YU arm_gpio_lock after changing the direction mode. */ static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs) - __releases(&gs->gc.bgpio_lock) + __releases(&gs->chip.gc.bgpio_lock) __releases(yu_arm_gpio_lock_param.lock) { writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io); - raw_spin_unlock(&gs->gc.bgpio_lock); + gpio_generic_chip_unlock(&gs->chip); mutex_unlock(yu_arm_gpio_lock_param.lock); } =20 @@ -235,11 +237,10 @@ static void mlxbf2_gpio_irq_enable(struct irq_data *i= rqd) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); struct mlxbf2_gpio_context *gs =3D gpiochip_get_data(gc); int offset =3D irqd_to_hwirq(irqd); - unsigned long flags; u32 val; =20 gpiochip_enable_irq(gc, irqd_to_hwirq(irqd)); - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&gs->chip); val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE); val |=3D BIT(offset); writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE); @@ -247,7 +248,6 @@ static void mlxbf2_gpio_irq_enable(struct irq_data *irq= d) val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); val |=3D BIT(offset); writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); } =20 static void mlxbf2_gpio_irq_disable(struct irq_data *irqd) @@ -255,21 +255,21 @@ static void mlxbf2_gpio_irq_disable(struct irq_data *= irqd) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); struct mlxbf2_gpio_context *gs =3D gpiochip_get_data(gc); int offset =3D irqd_to_hwirq(irqd); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); - val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); - val &=3D ~BIT(offset); - writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &gs->chip) { + val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); + val &=3D ~BIT(offset); + writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); + } + gpiochip_disable_irq(gc, irqd_to_hwirq(irqd)); } =20 static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr) { struct mlxbf2_gpio_context *gs =3D ptr; - struct gpio_chip *gc =3D &gs->gc; + struct gpio_chip *gc =3D &gs->chip.gc; unsigned long pending; u32 level; =20 @@ -288,7 +288,6 @@ mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigne= d int type) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); struct mlxbf2_gpio_context *gs =3D gpiochip_get_data(gc); int offset =3D irqd_to_hwirq(irqd); - unsigned long flags; bool fall =3D false; bool rise =3D false; u32 val; @@ -308,7 +307,8 @@ mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigne= d int type) return -EINVAL; } =20 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&gs->chip); + if (fall) { val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN); val |=3D BIT(offset); @@ -320,7 +320,6 @@ mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigne= d int type) val |=3D BIT(offset); writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN); } - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); =20 return 0; } @@ -347,6 +346,7 @@ static const struct irq_chip mlxbf2_gpio_irq_chip =3D { static int mlxbf2_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct mlxbf2_gpio_context *gs; struct device *dev =3D &pdev->dev; struct gpio_irq_chip *girq; @@ -375,18 +375,19 @@ mlxbf2_gpio_probe(struct platform_device *pdev) if (device_property_read_u32(dev, "npins", &npins)) npins =3D MLXBF2_GPIO_MAX_PINS_PER_BLOCK; =20 - gc =3D &gs->gc; + gc =3D &gs->chip.gc; =20 - ret =3D bgpio_init(gc, dev, 4, - gs->gpio_io + YU_GPIO_DATAIN, - gs->gpio_io + YU_GPIO_DATASET, - gs->gpio_io + YU_GPIO_DATACLEAR, - NULL, - NULL, - 0); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D gs->gpio_io + YU_GPIO_DATAIN, + .set =3D gs->gpio_io + YU_GPIO_DATASET, + .clr =3D gs->gpio_io + YU_GPIO_DATACLEAR, + }; =20 + ret =3D gpio_generic_chip_init(&gs->chip, &config); if (ret) - return dev_err_probe(dev, ret, "bgpio_init failed\n"); + return dev_err_probe(dev, ret, "failed to initialize the generic GPIO ch= ip\n"); =20 gc->direction_input =3D mlxbf2_gpio_direction_input; gc->direction_output =3D mlxbf2_gpio_direction_output; @@ -395,7 +396,7 @@ mlxbf2_gpio_probe(struct platform_device *pdev) =20 irq =3D platform_get_irq_optional(pdev, 0); if (irq >=3D 0) { - girq =3D &gs->gc.irq; + girq =3D &gs->chip.gc.irq; gpio_irq_chip_set_chip(girq, &mlxbf2_gpio_irq_chip); girq->handler =3D handle_simple_irq; girq->default_type =3D IRQ_TYPE_NONE; @@ -416,7 +417,7 @@ mlxbf2_gpio_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, gs); =20 - ret =3D devm_gpiochip_add_data(dev, &gs->gc, gs); + ret =3D devm_gpiochip_add_data(dev, &gs->chip.gc, gs); if (ret) return dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n"); =20 --=20 2.48.1