From nobody Fri Oct 3 21:02:27 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 649E92FC877; Mon, 25 Aug 2025 14:26:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756131972; cv=none; b=FlyeEHEcQTpJsVcC99Gyab/+DEOAge44NEagsYJ0vtPr4KHm8mnX76tfAXRG/ba3Y7gEHUyAl1dfoyW2q2BRA3cCqSxTpPLQZxvL67EPo0/QBnpqtfwzBwcGz4aPEwPziFdPO1euIuItbhhWPqbPnEi1yAOWg8ORhsf6juMdAfY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756131972; c=relaxed/simple; bh=IFYF9RIT73FLeFUegxVg+86DeUuSSQ5b97Whd6RNQpE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LM5tGQXYvb+jeOXX0mZASfYemlNKvteiJs0xRVm4I0w5Q9bWSc6hL5yIE/ujP2tjRarw90rToNP35Q6TiyjZOwbHdV1nH0b0nFXa7m9sWmx7eYwaDMapV74JjvK7h/UlpbPIZe9VyBIj3kBSWva8X/fcQbYVtHjSEsC2c9n2nwQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=AArkkKVn; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="AArkkKVn" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57PEPgvE831117; Mon, 25 Aug 2025 09:25:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756131942; bh=Lt6X5vJMypPF2ntqXJz2jWfNePmR/AQc1XaefjsIRj0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AArkkKVnCTRyGKjzMB7drhISF2k6g8debsl36wXsKjQIqN67zxhL9oDLu1mXGVTIf ZQVOB1+5KlZyaJkWZXIKRsn1VZUFLBz4oRnLqyqJvpAZz9lDtMYeRT25C8UbKwq94b n8Tra7W5ctejdk0yIegOMe2itK75RWePRSqpB6W8= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57PEPgZm669004 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 25 Aug 2025 09:25:42 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 25 Aug 2025 09:25:41 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 25 Aug 2025 09:25:41 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3p3747540; Mon, 25 Aug 2025 09:25:36 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 02/14] dt-bindings: media: ti,j721e-csi2rx-shim: Support 32 dma chans Date: Mon, 25 Aug 2025 19:55:10 +0530 Message-ID: <20250825142522.1826188-3-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra The CSI2RX SHIM IP can support 32x DMA channels. These can be used to split incoming "streams" of data on the CSI-RX port, distinguished by MIPI Virtual Channel (or Data Type), into different locations in memory. Actual number of DMA channels allocated to CSI-RX is dependent on the usecase, and can be modified using the K3 Resource Partitioning tool [1]. So set the minimum channels as 1 and maximum as 32. Link: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/10_00_07_04/= exports/docs/linux/How_to_Guides/Host/K3_Resource_Partitioning_Tool.html [1] Link: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Jai Luthra Reviewed-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Rob Herring (Arm) Reviewed-by: Yemike Abhilash Chandra Signed-off-by: Rishikesh Donadkar --- .../bindings/media/ti,j721e-csi2rx-shim.yaml | 39 +++++++++++++++++-- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.y= aml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml index b9f033f2f3ce..bf62998b0445 100644 --- a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml +++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml @@ -20,11 +20,44 @@ properties: const: ti,j721e-csi2rx-shim =20 dmas: - maxItems: 1 + minItems: 1 + maxItems: 32 =20 dma-names: + minItems: 1 items: - const: rx0 + - const: rx1 + - const: rx2 + - const: rx3 + - const: rx4 + - const: rx5 + - const: rx6 + - const: rx7 + - const: rx8 + - const: rx9 + - const: rx10 + - const: rx11 + - const: rx12 + - const: rx13 + - const: rx14 + - const: rx15 + - const: rx16 + - const: rx17 + - const: rx18 + - const: rx19 + - const: rx20 + - const: rx21 + - const: rx22 + - const: rx23 + - const: rx24 + - const: rx25 + - const: rx26 + - const: rx27 + - const: rx28 + - const: rx29 + - const: rx30 + - const: rx31 =20 reg: maxItems: 1 @@ -62,8 +95,8 @@ examples: =20 ti_csi2rx0: ticsi2rx@4500000 { compatible =3D "ti,j721e-csi2rx-shim"; - dmas =3D <&main_udmap 0x4940>; - dma-names =3D "rx0"; + dmas =3D <&main_udmap 0x4940>, <&main_udmap 0x4941>; + dma-names =3D "rx0", "rx1"; reg =3D <0x4500000 0x1000>; power-domains =3D <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; --=20 2.34.1