From nobody Fri Oct 3 20:26:50 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C3E32FD7A0; Mon, 25 Aug 2025 14:26:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756131970; cv=none; b=E8CV8XlrDHbixu3FMgGr7t8uuM+vU7VXj/d2VnnvPGkMg2YOmij8Ctr9++T+MCYtsfp1xu/SaGxYSSw8yE8L5Pys3vH25ADlIPiSml5jg4YBT7Z2000d8xRUPunGxDe1iaHwb0pS1lmwfX0PyWRL2ImGrSCpFubBffdLXZOoRy8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756131970; c=relaxed/simple; bh=Mld5ISGPALxOyvJoKBqf92b21BuUd63ks+esurEOXDM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=plS2yLzhIvkhVdIbxYvocj5IoDWX9IoTqahvm5QzeoY06jQ36mRXQi6ojG/exqLR0kyx7WO8Xpsl7DBXt1usNLhk+MiVAzfQpj+pjOPS9NEIxYqA1AsRRLnoX/cSBkyxVrjQzBxj48gLkdcMScDyHcW25o5DgtlRSe6YrF2MxlU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=PJ5bwJVm; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="PJ5bwJVm" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57PEPaaw1294844; Mon, 25 Aug 2025 09:25:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756131936; bh=/361XwHSvb122WZ867+lIgKqVCIqjCFUgdsiMSQZtRU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PJ5bwJVm94QOpXdzcUBV8NUgHM7d91iabhEYHIGNWmreM/Rb5VotSclIr0lx8rjN4 yaeqkHVn10BMk29Zv4uwDjTQ0o2pWO6qT8AFHmVjxOmqyhwCQYDeenXu4stqZWzGJQ /3zCnnA06nMPCQlkH9SvULAZlQOSH+wmKDLIm+QU= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57PEPahP668976 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 25 Aug 2025 09:25:36 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 25 Aug 2025 09:25:35 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 25 Aug 2025 09:25:35 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3o3747540; Mon, 25 Aug 2025 09:25:30 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 01/14] media: ti: j721e-csi2rx: Remove word size alignment on frame width Date: Mon, 25 Aug 2025 19:55:09 +0530 Message-ID: <20250825142522.1826188-2-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" j721e-csi2rx driver has a limitation of frame width being a multiple word size. However, there is no such limitation imposed by the hardware [1]. Remove this limitation from the driver. Link: https://www.ti.com/lit/pdf/spruj16 Signed-off-by: Rishikesh Donadkar Reviewed-by: Yemike Abhilash Chandra --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 3992f8b754b7..b3a27f4c3210 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -260,9 +260,6 @@ static void ti_csi2rx_fill_fmt(const struct ti_csi2rx_f= mt *csi_fmt, MAX_WIDTH_BYTES * 8 / csi_fmt->bpp); pix->height =3D clamp_t(unsigned int, pix->height, 1, MAX_HEIGHT_LINES); =20 - /* Width should be a multiple of transfer word-size */ - pix->width =3D rounddown(pix->width, pixels_in_word); - v4l2_fmt->type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE; pix->pixelformat =3D csi_fmt->fourcc; pix->bytesperline =3D pix->width * (csi_fmt->bpp / 8); @@ -360,23 +357,15 @@ static int ti_csi2rx_enum_framesizes(struct file *fil= e, void *fh, struct v4l2_frmsizeenum *fsize) { const struct ti_csi2rx_fmt *fmt; - unsigned int pixels_in_word; =20 fmt =3D find_format_by_fourcc(fsize->pixel_format); if (!fmt || fsize->index !=3D 0) return -EINVAL; =20 - /* - * Number of pixels in one PSI-L word. The transfer happens in multiples - * of PSI-L word sizes. - */ - pixels_in_word =3D PSIL_WORD_SIZE_BYTES * 8 / fmt->bpp; - fsize->type =3D V4L2_FRMSIZE_TYPE_STEPWISE; - fsize->stepwise.min_width =3D pixels_in_word; - fsize->stepwise.max_width =3D rounddown(MAX_WIDTH_BYTES * 8 / fmt->bpp, - pixels_in_word); - fsize->stepwise.step_width =3D pixels_in_word; + fsize->stepwise.min_width =3D 1; + fsize->stepwise.max_width =3D MAX_WIDTH_BYTES * 8 / fmt->bpp; + fsize->stepwise.step_width =3D 1; fsize->stepwise.min_height =3D 1; fsize->stepwise.max_height =3D MAX_HEIGHT_LINES; fsize->stepwise.step_height =3D 1; --=20 2.34.1 From nobody Fri Oct 3 20:26:50 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 649E92FC877; Mon, 25 Aug 2025 14:26:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756131972; cv=none; b=FlyeEHEcQTpJsVcC99Gyab/+DEOAge44NEagsYJ0vtPr4KHm8mnX76tfAXRG/ba3Y7gEHUyAl1dfoyW2q2BRA3cCqSxTpPLQZxvL67EPo0/QBnpqtfwzBwcGz4aPEwPziFdPO1euIuItbhhWPqbPnEi1yAOWg8ORhsf6juMdAfY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756131972; c=relaxed/simple; bh=IFYF9RIT73FLeFUegxVg+86DeUuSSQ5b97Whd6RNQpE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LM5tGQXYvb+jeOXX0mZASfYemlNKvteiJs0xRVm4I0w5Q9bWSc6hL5yIE/ujP2tjRarw90rToNP35Q6TiyjZOwbHdV1nH0b0nFXa7m9sWmx7eYwaDMapV74JjvK7h/UlpbPIZe9VyBIj3kBSWva8X/fcQbYVtHjSEsC2c9n2nwQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=AArkkKVn; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="AArkkKVn" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57PEPgvE831117; Mon, 25 Aug 2025 09:25:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756131942; bh=Lt6X5vJMypPF2ntqXJz2jWfNePmR/AQc1XaefjsIRj0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AArkkKVnCTRyGKjzMB7drhISF2k6g8debsl36wXsKjQIqN67zxhL9oDLu1mXGVTIf ZQVOB1+5KlZyaJkWZXIKRsn1VZUFLBz4oRnLqyqJvpAZz9lDtMYeRT25C8UbKwq94b n8Tra7W5ctejdk0yIegOMe2itK75RWePRSqpB6W8= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57PEPgZm669004 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 25 Aug 2025 09:25:42 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 25 Aug 2025 09:25:41 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 25 Aug 2025 09:25:41 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3p3747540; Mon, 25 Aug 2025 09:25:36 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 02/14] dt-bindings: media: ti,j721e-csi2rx-shim: Support 32 dma chans Date: Mon, 25 Aug 2025 19:55:10 +0530 Message-ID: <20250825142522.1826188-3-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra The CSI2RX SHIM IP can support 32x DMA channels. These can be used to split incoming "streams" of data on the CSI-RX port, distinguished by MIPI Virtual Channel (or Data Type), into different locations in memory. Actual number of DMA channels allocated to CSI-RX is dependent on the usecase, and can be modified using the K3 Resource Partitioning tool [1]. So set the minimum channels as 1 and maximum as 32. Link: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/10_00_07_04/= exports/docs/linux/How_to_Guides/Host/K3_Resource_Partitioning_Tool.html [1] Link: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Jai Luthra Reviewed-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Rob Herring (Arm) Reviewed-by: Yemike Abhilash Chandra Signed-off-by: Rishikesh Donadkar --- .../bindings/media/ti,j721e-csi2rx-shim.yaml | 39 +++++++++++++++++-- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.y= aml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml index b9f033f2f3ce..bf62998b0445 100644 --- a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml +++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml @@ -20,11 +20,44 @@ properties: const: ti,j721e-csi2rx-shim =20 dmas: - maxItems: 1 + minItems: 1 + maxItems: 32 =20 dma-names: + minItems: 1 items: - const: rx0 + - const: rx1 + - const: rx2 + - const: rx3 + - const: rx4 + - const: rx5 + - const: rx6 + - const: rx7 + - const: rx8 + - const: rx9 + - const: rx10 + - const: rx11 + - const: rx12 + - const: rx13 + - const: rx14 + - const: rx15 + - const: rx16 + - const: rx17 + - const: rx18 + - const: rx19 + - const: rx20 + - const: rx21 + - const: rx22 + - const: rx23 + - const: rx24 + - const: rx25 + - const: rx26 + - const: rx27 + - const: rx28 + - const: rx29 + - const: rx30 + - const: rx31 =20 reg: maxItems: 1 @@ -62,8 +95,8 @@ examples: =20 ti_csi2rx0: ticsi2rx@4500000 { compatible =3D "ti,j721e-csi2rx-shim"; - dmas =3D <&main_udmap 0x4940>; - dma-names =3D "rx0"; + dmas =3D <&main_udmap 0x4940>, <&main_udmap 0x4941>; + dma-names =3D "rx0", "rx1"; reg =3D <0x4500000 0x1000>; power-domains =3D <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; --=20 2.34.1 From nobody Fri Oct 3 20:26:50 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B67792FD7B4; Mon, 25 Aug 2025 14:26:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756131971; cv=none; b=qCfm+1JhJMJKHa1FCC55euO+eBgMb0j+AnoPcjnXfGRgWgQQuL5zvnar06ivse6hvd6qsYT95tfwtTFOHRyR+8id5YSheMyBc/HWFl5yLgwq7i3ae1aKLuhykV2pxtkSbFc4C1JqYer1yyCIeIkG2saZ6sgyr/ZDpmp9Gr464gY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 25 Aug 2025 09:25:48 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3q3747540; Mon, 25 Aug 2025 09:25:42 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 03/14] media: ti: j721e-csi2rx: separate out device and context Date: Mon, 25 Aug 2025 19:55:11 +0530 Message-ID: <20250825142522.1826188-4-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra The TI CSI2RX wrapper has two parts: the main device and the DMA contexts. The driver was originally written with single camera capture in mind, so only one DMA context was needed. For the sake of simplicity, the context specific stuff was not modeled different to the main device. To enable multiplexed stream capture, the contexts need to be separated out from the main device. Create a struct ti_csi2rx_ctx that holds the DMA context specific things. Separate out functions handling the device and context related functionality. Reviewed-by: Yemike Abhilash Chandra Co-developed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav Signed-off-by: Jai Luthra Signed-off-by: Rishikesh Donadkar --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 420 ++++++++++-------- 1 file changed, 232 insertions(+), 188 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index b3a27f4c3210..cb52bc7afd1f 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -44,6 +44,8 @@ =20 #define TI_CSI2RX_MAX_PIX_PER_CLK 4 #define PSIL_WORD_SIZE_BYTES 16 +#define TI_CSI2RX_NUM_CTX 1 + /* * There are no hard limits on the width or height. The DMA engine can han= dle * all sizes. The max width and height are arbitrary numbers for this driv= er. @@ -70,7 +72,7 @@ struct ti_csi2rx_buffer { /* Common v4l2 buffer. Must be first. */ struct vb2_v4l2_buffer vb; struct list_head list; - struct ti_csi2rx_dev *csi; + struct ti_csi2rx_ctx *ctx; }; =20 enum ti_csi2rx_dma_state { @@ -90,30 +92,38 @@ struct ti_csi2rx_dma { * Queue of buffers submitted to DMA engine. */ struct list_head submitted; - /* Buffer to drain stale data from PSI-L endpoint */ - struct { - void *vaddr; - dma_addr_t paddr; - size_t len; - } drain; +}; + +struct ti_csi2rx_dev; + +struct ti_csi2rx_ctx { + struct ti_csi2rx_dev *csi; + struct video_device vdev; + struct vb2_queue vidq; + struct mutex mutex; /* To serialize ioctls. */ + struct v4l2_format v_fmt; + struct ti_csi2rx_dma dma; + u32 sequence; + u32 idx; }; =20 struct ti_csi2rx_dev { struct device *dev; void __iomem *shim; struct v4l2_device v4l2_dev; - struct video_device vdev; struct media_device mdev; struct media_pipeline pipe; struct media_pad pad; struct v4l2_async_notifier notifier; struct v4l2_subdev *source; - struct vb2_queue vidq; - struct mutex mutex; /* To serialize ioctls. */ - struct v4l2_format v_fmt; - struct ti_csi2rx_dma dma; - u32 sequence; + struct ti_csi2rx_ctx ctx[TI_CSI2RX_NUM_CTX]; u8 pix_per_clk; + /* Buffer to drain stale data from PSI-L endpoint */ + struct { + void *vaddr; + dma_addr_t paddr; + size_t len; + } drain; }; =20 static const struct ti_csi2rx_fmt ti_csi2rx_formats[] =3D { @@ -219,7 +229,7 @@ static const struct ti_csi2rx_fmt ti_csi2rx_formats[] = =3D { }; =20 /* Forward declaration needed by ti_csi2rx_dma_callback. */ -static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi, +static int ti_csi2rx_start_dma(struct ti_csi2rx_ctx *ctx, struct ti_csi2rx_buffer *buf); =20 static const struct ti_csi2rx_fmt *find_format_by_fourcc(u32 pixelformat) @@ -306,7 +316,7 @@ static int ti_csi2rx_enum_fmt_vid_cap(struct file *file= , void *priv, static int ti_csi2rx_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) { - struct ti_csi2rx_dev *csi =3D video_drvdata(file); + struct ti_csi2rx_ctx *csi =3D video_drvdata(file); =20 *f =3D csi->v_fmt; =20 @@ -337,7 +347,7 @@ static int ti_csi2rx_try_fmt_vid_cap(struct file *file,= void *priv, static int ti_csi2rx_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) { - struct ti_csi2rx_dev *csi =3D video_drvdata(file); + struct ti_csi2rx_ctx *csi =3D video_drvdata(file); struct vb2_queue *q =3D &csi->vidq; int ret; =20 @@ -415,26 +425,35 @@ static int csi_async_notifier_bound(struct v4l2_async= _notifier *notifier, static int csi_async_notifier_complete(struct v4l2_async_notifier *notifie= r) { struct ti_csi2rx_dev *csi =3D dev_get_drvdata(notifier->v4l2_dev->dev); - struct video_device *vdev =3D &csi->vdev; - int ret; + int ret, i; =20 - ret =3D video_register_device(vdev, VFL_TYPE_VIDEO, -1); - if (ret) - return ret; - - ret =3D media_create_pad_link(&csi->source->entity, CSI2RX_BRIDGE_SOURCE_= PAD, - &vdev->entity, csi->pad.index, - MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED); + for (i =3D 0; i < TI_CSI2RX_NUM_CTX; i++) { + struct ti_csi2rx_ctx *ctx =3D &csi->ctx[i]; + struct video_device *vdev =3D &ctx->vdev; =20 - if (ret) { - video_unregister_device(vdev); - return ret; + ret =3D video_register_device(vdev, VFL_TYPE_VIDEO, -1); + if (ret) + goto unregister_dev; } =20 + ret =3D media_create_pad_link(&csi->source->entity, + CSI2RX_BRIDGE_SOURCE_PAD, + &vdev->entity, csi->pad.index, + MEDIA_LNK_FL_IMMUTABLE | + MEDIA_LNK_FL_ENABLED); + if (ret) + goto unregister_dev; + ret =3D v4l2_device_register_subdev_nodes(&csi->v4l2_dev); if (ret) - video_unregister_device(vdev); + goto unregister_dev; =20 + return 0; + +unregister_dev: + i--; + for (; i >=3D 0; i--) + video_unregister_device(&csi->ctx[i].vdev); return ret; } =20 @@ -479,13 +498,14 @@ static int ti_csi2rx_notifier_register(struct ti_csi2= rx_dev *csi) } =20 /* Request maximum possible pixels per clock from the bridge */ -static void ti_csi2rx_request_max_ppc(struct ti_csi2rx_dev *csi) +static void ti_csi2rx_request_max_ppc(struct ti_csi2rx_ctx *ctx) { + struct ti_csi2rx_dev *csi =3D ctx->csi; u8 ppc =3D TI_CSI2RX_MAX_PIX_PER_CLK; struct media_pad *pad; int ret; =20 - pad =3D media_entity_remote_source_pad_unique(&csi->vdev.entity); + pad =3D media_entity_remote_source_pad_unique(&ctx->vdev.entity); if (!pad) return; =20 @@ -498,19 +518,20 @@ static void ti_csi2rx_request_max_ppc(struct ti_csi2r= x_dev *csi) } } =20 -static void ti_csi2rx_setup_shim(struct ti_csi2rx_dev *csi) +static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx *ctx) { + struct ti_csi2rx_dev *csi =3D ctx->csi; const struct ti_csi2rx_fmt *fmt; unsigned int reg; =20 - fmt =3D find_format_by_fourcc(csi->v_fmt.fmt.pix.pixelformat); + fmt =3D find_format_by_fourcc(ctx->v_fmt.fmt.pix.pixelformat); =20 /* De-assert the pixel interface reset. */ reg =3D SHIM_CNTL_PIX_RST; writel(reg, csi->shim + SHIM_CNTL); =20 /* Negotiate pixel count from the source */ - ti_csi2rx_request_max_ppc(csi); + ti_csi2rx_request_max_ppc(ctx); =20 reg =3D SHIM_DMACNTX_EN; reg |=3D FIELD_PREP(SHIM_DMACNTX_FMT, fmt->csi_dt); @@ -577,8 +598,9 @@ static void ti_csi2rx_drain_callback(void *param) * To prevent that stale data corrupting the subsequent transactions, it is * required to issue DMA requests to drain it out. */ -static int ti_csi2rx_drain_dma(struct ti_csi2rx_dev *csi) +static int ti_csi2rx_drain_dma(struct ti_csi2rx_ctx *ctx) { + struct ti_csi2rx_dev *csi =3D ctx->csi; struct dma_async_tx_descriptor *desc; struct completion drain_complete; dma_cookie_t cookie; @@ -586,8 +608,8 @@ static int ti_csi2rx_drain_dma(struct ti_csi2rx_dev *cs= i) =20 init_completion(&drain_complete); =20 - desc =3D dmaengine_prep_slave_single(csi->dma.chan, csi->dma.drain.paddr, - csi->dma.drain.len, DMA_DEV_TO_MEM, + desc =3D dmaengine_prep_slave_single(ctx->dma.chan, csi->drain.paddr, + csi->drain.len, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); if (!desc) { ret =3D -EIO; @@ -602,11 +624,11 @@ static int ti_csi2rx_drain_dma(struct ti_csi2rx_dev *= csi) if (ret) goto out; =20 - dma_async_issue_pending(csi->dma.chan); + dma_async_issue_pending(ctx->dma.chan); =20 if (!wait_for_completion_timeout(&drain_complete, msecs_to_jiffies(DRAIN_TIMEOUT_MS))) { - dmaengine_terminate_sync(csi->dma.chan); + dmaengine_terminate_sync(ctx->dma.chan); dev_dbg(csi->dev, "DMA transfer timed out for drain buffer\n"); ret =3D -ETIMEDOUT; goto out; @@ -618,8 +640,8 @@ static int ti_csi2rx_drain_dma(struct ti_csi2rx_dev *cs= i) static void ti_csi2rx_dma_callback(void *param) { struct ti_csi2rx_buffer *buf =3D param; - struct ti_csi2rx_dev *csi =3D buf->csi; - struct ti_csi2rx_dma *dma =3D &csi->dma; + struct ti_csi2rx_ctx *ctx =3D buf->ctx; + struct ti_csi2rx_dma *dma =3D &ctx->dma; unsigned long flags; =20 /* @@ -627,7 +649,7 @@ static void ti_csi2rx_dma_callback(void *param) * hardware monitor registers. */ buf->vb.vb2_buf.timestamp =3D ktime_get_ns(); - buf->vb.sequence =3D csi->sequence++; + buf->vb.sequence =3D ctx->sequence++; =20 spin_lock_irqsave(&dma->lock, flags); =20 @@ -654,17 +676,17 @@ static void ti_csi2rx_dma_callback(void *param) spin_unlock_irqrestore(&dma->lock, flags); } =20 -static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi, +static int ti_csi2rx_start_dma(struct ti_csi2rx_ctx *ctx, struct ti_csi2rx_buffer *buf) { unsigned long addr; struct dma_async_tx_descriptor *desc; - size_t len =3D csi->v_fmt.fmt.pix.sizeimage; + size_t len =3D ctx->v_fmt.fmt.pix.sizeimage; dma_cookie_t cookie; int ret =3D 0; =20 addr =3D vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); - desc =3D dmaengine_prep_slave_single(csi->dma.chan, addr, len, + desc =3D dmaengine_prep_slave_single(ctx->dma.chan, addr, len, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); if (!desc) @@ -678,20 +700,20 @@ static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *= csi, if (ret) return ret; =20 - dma_async_issue_pending(csi->dma.chan); + dma_async_issue_pending(ctx->dma.chan); =20 return 0; } =20 -static void ti_csi2rx_stop_dma(struct ti_csi2rx_dev *csi) +static void ti_csi2rx_stop_dma(struct ti_csi2rx_ctx *ctx) { - struct ti_csi2rx_dma *dma =3D &csi->dma; + struct ti_csi2rx_dma *dma =3D &ctx->dma; enum ti_csi2rx_dma_state state; unsigned long flags; int ret; =20 spin_lock_irqsave(&dma->lock, flags); - state =3D csi->dma.state; + state =3D ctx->dma.state; dma->state =3D TI_CSI2RX_DMA_STOPPED; spin_unlock_irqrestore(&dma->lock, flags); =20 @@ -702,30 +724,30 @@ static void ti_csi2rx_stop_dma(struct ti_csi2rx_dev *= csi) * is stopped, as the module-level pixel reset cannot be * enforced before terminating DMA. */ - ret =3D ti_csi2rx_drain_dma(csi); + ret =3D ti_csi2rx_drain_dma(ctx); if (ret && ret !=3D -ETIMEDOUT) - dev_warn(csi->dev, + dev_warn(ctx->csi->dev, "Failed to drain DMA. Next frame might be bogus\n"); } =20 - ret =3D dmaengine_terminate_sync(csi->dma.chan); + ret =3D dmaengine_terminate_sync(ctx->dma.chan); if (ret) - dev_err(csi->dev, "Failed to stop DMA: %d\n", ret); + dev_err(ctx->csi->dev, "Failed to stop DMA: %d\n", ret); } =20 -static void ti_csi2rx_cleanup_buffers(struct ti_csi2rx_dev *csi, +static void ti_csi2rx_cleanup_buffers(struct ti_csi2rx_ctx *ctx, enum vb2_buffer_state state) { - struct ti_csi2rx_dma *dma =3D &csi->dma; + struct ti_csi2rx_dma *dma =3D &ctx->dma; struct ti_csi2rx_buffer *buf, *tmp; unsigned long flags; =20 spin_lock_irqsave(&dma->lock, flags); - list_for_each_entry_safe(buf, tmp, &csi->dma.queue, list) { + list_for_each_entry_safe(buf, tmp, &ctx->dma.queue, list) { list_del(&buf->list); vb2_buffer_done(&buf->vb.vb2_buf, state); } - list_for_each_entry_safe(buf, tmp, &csi->dma.submitted, list) { + list_for_each_entry_safe(buf, tmp, &ctx->dma.submitted, list) { list_del(&buf->list); vb2_buffer_done(&buf->vb.vb2_buf, state); } @@ -736,8 +758,8 @@ static int ti_csi2rx_queue_setup(struct vb2_queue *q, u= nsigned int *nbuffers, unsigned int *nplanes, unsigned int sizes[], struct device *alloc_devs[]) { - struct ti_csi2rx_dev *csi =3D vb2_get_drv_priv(q); - unsigned int size =3D csi->v_fmt.fmt.pix.sizeimage; + struct ti_csi2rx_ctx *ctx =3D vb2_get_drv_priv(q); + unsigned int size =3D ctx->v_fmt.fmt.pix.sizeimage; =20 if (*nplanes) { if (sizes[0] < size) @@ -753,11 +775,11 @@ static int ti_csi2rx_queue_setup(struct vb2_queue *q,= unsigned int *nbuffers, =20 static int ti_csi2rx_buffer_prepare(struct vb2_buffer *vb) { - struct ti_csi2rx_dev *csi =3D vb2_get_drv_priv(vb->vb2_queue); - unsigned long size =3D csi->v_fmt.fmt.pix.sizeimage; + struct ti_csi2rx_ctx *ctx =3D vb2_get_drv_priv(vb->vb2_queue); + unsigned long size =3D ctx->v_fmt.fmt.pix.sizeimage; =20 if (vb2_plane_size(vb, 0) < size) { - dev_err(csi->dev, "Data will not fit into plane\n"); + dev_err(ctx->csi->dev, "Data will not fit into plane\n"); return -EINVAL; } =20 @@ -767,15 +789,15 @@ static int ti_csi2rx_buffer_prepare(struct vb2_buffer= *vb) =20 static void ti_csi2rx_buffer_queue(struct vb2_buffer *vb) { - struct ti_csi2rx_dev *csi =3D vb2_get_drv_priv(vb->vb2_queue); + struct ti_csi2rx_ctx *ctx =3D vb2_get_drv_priv(vb->vb2_queue); struct ti_csi2rx_buffer *buf; - struct ti_csi2rx_dma *dma =3D &csi->dma; + struct ti_csi2rx_dma *dma =3D &ctx->dma; bool restart_dma =3D false; unsigned long flags =3D 0; int ret; =20 buf =3D container_of(vb, struct ti_csi2rx_buffer, vb.vb2_buf); - buf->csi =3D csi; + buf->ctx =3D ctx; =20 spin_lock_irqsave(&dma->lock, flags); /* @@ -804,18 +826,18 @@ static void ti_csi2rx_buffer_queue(struct vb2_buffer = *vb) * the application and will only confuse it. Issue a DMA * transaction to drain that up. */ - ret =3D ti_csi2rx_drain_dma(csi); + ret =3D ti_csi2rx_drain_dma(ctx); if (ret && ret !=3D -ETIMEDOUT) - dev_warn(csi->dev, + dev_warn(ctx->csi->dev, "Failed to drain DMA. Next frame might be bogus\n"); =20 spin_lock_irqsave(&dma->lock, flags); - ret =3D ti_csi2rx_start_dma(csi, buf); + ret =3D ti_csi2rx_start_dma(ctx, buf); if (ret) { vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); dma->state =3D TI_CSI2RX_DMA_IDLE; spin_unlock_irqrestore(&dma->lock, flags); - dev_err(csi->dev, "Failed to start DMA: %d\n", ret); + dev_err(ctx->csi->dev, "Failed to start DMA: %d\n", ret); } else { list_add_tail(&buf->list, &dma->submitted); spin_unlock_irqrestore(&dma->lock, flags); @@ -825,8 +847,9 @@ static void ti_csi2rx_buffer_queue(struct vb2_buffer *v= b) =20 static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int co= unt) { - struct ti_csi2rx_dev *csi =3D vb2_get_drv_priv(vq); - struct ti_csi2rx_dma *dma =3D &csi->dma; + struct ti_csi2rx_ctx *ctx =3D vb2_get_drv_priv(vq); + struct ti_csi2rx_dev *csi =3D ctx->csi; + struct ti_csi2rx_dma *dma =3D &ctx->dma; struct ti_csi2rx_buffer *buf; unsigned long flags; int ret =3D 0; @@ -838,18 +861,18 @@ static int ti_csi2rx_start_streaming(struct vb2_queue= *vq, unsigned int count) if (ret) return ret; =20 - ret =3D video_device_pipeline_start(&csi->vdev, &csi->pipe); + ret =3D video_device_pipeline_start(&ctx->vdev, &csi->pipe); if (ret) goto err; =20 - ti_csi2rx_setup_shim(csi); + ti_csi2rx_setup_shim(ctx); =20 - csi->sequence =3D 0; + ctx->sequence =3D 0; =20 spin_lock_irqsave(&dma->lock, flags); buf =3D list_entry(dma->queue.next, struct ti_csi2rx_buffer, list); =20 - ret =3D ti_csi2rx_start_dma(csi, buf); + ret =3D ti_csi2rx_start_dma(ctx, buf); if (ret) { dev_err(csi->dev, "Failed to start DMA: %d\n", ret); spin_unlock_irqrestore(&dma->lock, flags); @@ -867,22 +890,23 @@ static int ti_csi2rx_start_streaming(struct vb2_queue= *vq, unsigned int count) return 0; =20 err_dma: - ti_csi2rx_stop_dma(csi); + ti_csi2rx_stop_dma(ctx); err_pipeline: - video_device_pipeline_stop(&csi->vdev); + video_device_pipeline_stop(&ctx->vdev); writel(0, csi->shim + SHIM_CNTL); writel(0, csi->shim + SHIM_DMACNTX); err: - ti_csi2rx_cleanup_buffers(csi, VB2_BUF_STATE_QUEUED); + ti_csi2rx_cleanup_buffers(ctx, VB2_BUF_STATE_QUEUED); return ret; } =20 static void ti_csi2rx_stop_streaming(struct vb2_queue *vq) { - struct ti_csi2rx_dev *csi =3D vb2_get_drv_priv(vq); + struct ti_csi2rx_ctx *ctx =3D vb2_get_drv_priv(vq); + struct ti_csi2rx_dev *csi =3D ctx->csi; int ret; =20 - video_device_pipeline_stop(&csi->vdev); + video_device_pipeline_stop(&ctx->vdev); =20 writel(0, csi->shim + SHIM_CNTL); writel(0, csi->shim + SHIM_DMACNTX); @@ -891,8 +915,8 @@ static void ti_csi2rx_stop_streaming(struct vb2_queue *= vq) if (ret) dev_err(csi->dev, "Failed to stop subdev stream\n"); =20 - ti_csi2rx_stop_dma(csi); - ti_csi2rx_cleanup_buffers(csi, VB2_BUF_STATE_ERROR); + ti_csi2rx_stop_dma(ctx); + ti_csi2rx_cleanup_buffers(ctx, VB2_BUF_STATE_ERROR); } =20 static const struct vb2_ops csi_vb2_qops =3D { @@ -903,20 +927,43 @@ static const struct vb2_ops csi_vb2_qops =3D { .stop_streaming =3D ti_csi2rx_stop_streaming, }; =20 -static int ti_csi2rx_init_vb2q(struct ti_csi2rx_dev *csi) +static void ti_csi2rx_cleanup_v4l2(struct ti_csi2rx_dev *csi) { - struct vb2_queue *q =3D &csi->vidq; + media_device_unregister(&csi->mdev); + v4l2_device_unregister(&csi->v4l2_dev); + media_device_cleanup(&csi->mdev); +} + +static void ti_csi2rx_cleanup_notifier(struct ti_csi2rx_dev *csi) +{ + v4l2_async_nf_unregister(&csi->notifier); + v4l2_async_nf_cleanup(&csi->notifier); +} + +static void ti_csi2rx_cleanup_ctx(struct ti_csi2rx_ctx *ctx) +{ + dma_release_channel(ctx->dma.chan); + vb2_queue_release(&ctx->vidq); + + video_unregister_device(&ctx->vdev); + + mutex_destroy(&ctx->mutex); +} + +static int ti_csi2rx_init_vb2q(struct ti_csi2rx_ctx *ctx) +{ + struct vb2_queue *q =3D &ctx->vidq; int ret; =20 q->type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE; q->io_modes =3D VB2_MMAP | VB2_DMABUF; - q->drv_priv =3D csi; + q->drv_priv =3D ctx; q->buf_struct_size =3D sizeof(struct ti_csi2rx_buffer); q->ops =3D &csi_vb2_qops; q->mem_ops =3D &vb2_dma_contig_memops; q->timestamp_flags =3D V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; - q->dev =3D dmaengine_get_dma_device(csi->dma.chan); - q->lock =3D &csi->mutex; + q->dev =3D dmaengine_get_dma_device(ctx->dma.chan); + q->lock =3D &ctx->mutex; q->min_queued_buffers =3D 1; q->allow_cache_hints =3D 1; =20 @@ -924,7 +971,7 @@ static int ti_csi2rx_init_vb2q(struct ti_csi2rx_dev *cs= i) if (ret) return ret; =20 - csi->vdev.queue =3D q; + ctx->vdev.queue =3D q; =20 return 0; } @@ -933,8 +980,9 @@ static int ti_csi2rx_link_validate(struct media_link *l= ink) { struct media_entity *entity =3D link->sink->entity; struct video_device *vdev =3D media_entity_to_video_device(entity); - struct ti_csi2rx_dev *csi =3D container_of(vdev, struct ti_csi2rx_dev, vd= ev); - struct v4l2_pix_format *csi_fmt =3D &csi->v_fmt.fmt.pix; + struct ti_csi2rx_ctx *ctx =3D container_of(vdev, struct ti_csi2rx_ctx, vd= ev); + struct ti_csi2rx_dev *csi =3D ctx->csi; + struct v4l2_pix_format *csi_fmt =3D &ctx->v_fmt.fmt.pix; struct v4l2_subdev_format source_fmt =3D { .which =3D V4L2_SUBDEV_FORMAT_ACTIVE, .pad =3D link->source->index, @@ -987,47 +1035,63 @@ static const struct media_entity_operations ti_csi2r= x_video_entity_ops =3D { .link_validate =3D ti_csi2rx_link_validate, }; =20 -static int ti_csi2rx_init_dma(struct ti_csi2rx_dev *csi) +static int ti_csi2rx_init_dma(struct ti_csi2rx_ctx *ctx) { struct dma_slave_config cfg =3D { .src_addr_width =3D DMA_SLAVE_BUSWIDTH_16_BYTES, }; int ret; =20 - INIT_LIST_HEAD(&csi->dma.queue); - INIT_LIST_HEAD(&csi->dma.submitted); - spin_lock_init(&csi->dma.lock); - - csi->dma.state =3D TI_CSI2RX_DMA_STOPPED; + ctx->dma.chan =3D dma_request_chan(ctx->csi->dev, "rx0"); + if (IS_ERR(ctx->dma.chan)) + return PTR_ERR(ctx->dma.chan); =20 - csi->dma.chan =3D dma_request_chan(csi->dev, "rx0"); - if (IS_ERR(csi->dma.chan)) - return PTR_ERR(csi->dma.chan); - - ret =3D dmaengine_slave_config(csi->dma.chan, &cfg); + ret =3D dmaengine_slave_config(ctx->dma.chan, &cfg); if (ret) { - dma_release_channel(csi->dma.chan); + dma_release_channel(ctx->dma.chan); return ret; } =20 - csi->dma.drain.len =3D DRAIN_BUFFER_SIZE; - csi->dma.drain.vaddr =3D dma_alloc_coherent(csi->dev, csi->dma.drain.len, - &csi->dma.drain.paddr, - GFP_KERNEL); - if (!csi->dma.drain.vaddr) - return -ENOMEM; - return 0; } =20 static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev *csi) { struct media_device *mdev =3D &csi->mdev; - struct video_device *vdev =3D &csi->vdev; + int ret; + + mdev->dev =3D csi->dev; + mdev->hw_revision =3D 1; + strscpy(mdev->model, "TI-CSI2RX", sizeof(mdev->model)); + + media_device_init(mdev); + + csi->v4l2_dev.mdev =3D mdev; + + ret =3D v4l2_device_register(csi->dev, &csi->v4l2_dev); + if (ret) + return ret; + + ret =3D media_device_register(mdev); + if (ret) { + v4l2_device_unregister(&csi->v4l2_dev); + media_device_cleanup(mdev); + return ret; + } + + return 0; +} + +static int ti_csi2rx_init_ctx(struct ti_csi2rx_ctx *ctx) +{ + struct ti_csi2rx_dev *csi =3D ctx->csi; + struct video_device *vdev =3D &ctx->vdev; const struct ti_csi2rx_fmt *fmt; - struct v4l2_pix_format *pix_fmt =3D &csi->v_fmt.fmt.pix; + struct v4l2_pix_format *pix_fmt =3D &ctx->v_fmt.fmt.pix; int ret; =20 + mutex_init(&ctx->mutex); + fmt =3D find_format_by_fourcc(V4L2_PIX_FMT_UYVY); if (!fmt) return -EINVAL; @@ -1036,19 +1100,20 @@ static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev= *csi) pix_fmt->height =3D 480; pix_fmt->field =3D V4L2_FIELD_NONE; pix_fmt->colorspace =3D V4L2_COLORSPACE_SRGB; - pix_fmt->ycbcr_enc =3D V4L2_YCBCR_ENC_601; - pix_fmt->quantization =3D V4L2_QUANTIZATION_LIM_RANGE; - pix_fmt->xfer_func =3D V4L2_XFER_FUNC_SRGB; + pix_fmt->ycbcr_enc =3D V4L2_YCBCR_ENC_601, + pix_fmt->quantization =3D V4L2_QUANTIZATION_LIM_RANGE, + pix_fmt->xfer_func =3D V4L2_XFER_FUNC_SRGB, =20 - ti_csi2rx_fill_fmt(fmt, &csi->v_fmt); + ti_csi2rx_fill_fmt(fmt, &ctx->v_fmt); =20 - mdev->dev =3D csi->dev; - mdev->hw_revision =3D 1; - strscpy(mdev->model, "TI-CSI2RX", sizeof(mdev->model)); - - media_device_init(mdev); + csi->pad.flags =3D MEDIA_PAD_FL_SINK; + vdev->entity.ops =3D &ti_csi2rx_video_entity_ops; + ret =3D media_entity_pads_init(&ctx->vdev.entity, 1, &csi->pad); + if (ret) + return ret; =20 - strscpy(vdev->name, TI_CSI2RX_MODULE_NAME, sizeof(vdev->name)); + snprintf(vdev->name, sizeof(vdev->name), "%s context %u", + dev_name(csi->dev), ctx->idx); vdev->v4l2_dev =3D &csi->v4l2_dev; vdev->vfl_dir =3D VFL_DIR_RX; vdev->fops =3D &csi_fops; @@ -1056,61 +1121,33 @@ static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev= *csi) vdev->release =3D video_device_release_empty; vdev->device_caps =3D V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | V4L2_CAP_IO_MC; - vdev->lock =3D &csi->mutex; - video_set_drvdata(vdev, csi); + vdev->lock =3D &ctx->mutex; + video_set_drvdata(vdev, ctx); =20 - csi->pad.flags =3D MEDIA_PAD_FL_SINK; - vdev->entity.ops =3D &ti_csi2rx_video_entity_ops; - ret =3D media_entity_pads_init(&csi->vdev.entity, 1, &csi->pad); - if (ret) - return ret; + INIT_LIST_HEAD(&ctx->dma.queue); + INIT_LIST_HEAD(&ctx->dma.submitted); + spin_lock_init(&ctx->dma.lock); + ctx->dma.state =3D TI_CSI2RX_DMA_STOPPED; =20 - csi->v4l2_dev.mdev =3D mdev; - - ret =3D v4l2_device_register(csi->dev, &csi->v4l2_dev); + ret =3D ti_csi2rx_init_dma(ctx); if (ret) return ret; =20 - ret =3D media_device_register(mdev); - if (ret) { - v4l2_device_unregister(&csi->v4l2_dev); - media_device_cleanup(mdev); - return ret; - } + ret =3D ti_csi2rx_init_vb2q(ctx); + if (ret) + goto cleanup_dma; =20 return 0; -} - -static void ti_csi2rx_cleanup_dma(struct ti_csi2rx_dev *csi) -{ - dma_free_coherent(csi->dev, csi->dma.drain.len, - csi->dma.drain.vaddr, csi->dma.drain.paddr); - csi->dma.drain.vaddr =3D NULL; - dma_release_channel(csi->dma.chan); -} - -static void ti_csi2rx_cleanup_v4l2(struct ti_csi2rx_dev *csi) -{ - media_device_unregister(&csi->mdev); - v4l2_device_unregister(&csi->v4l2_dev); - media_device_cleanup(&csi->mdev); -} - -static void ti_csi2rx_cleanup_subdev(struct ti_csi2rx_dev *csi) -{ - v4l2_async_nf_unregister(&csi->notifier); - v4l2_async_nf_cleanup(&csi->notifier); -} =20 -static void ti_csi2rx_cleanup_vb2q(struct ti_csi2rx_dev *csi) -{ - vb2_queue_release(&csi->vidq); +cleanup_dma: + dma_release_channel(ctx->dma.chan); + return ret; } =20 static int ti_csi2rx_probe(struct platform_device *pdev) { struct ti_csi2rx_dev *csi; - int ret; + int ret, i; =20 csi =3D devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); if (!csi) @@ -1119,62 +1156,69 @@ static int ti_csi2rx_probe(struct platform_device *= pdev) csi->dev =3D &pdev->dev; platform_set_drvdata(pdev, csi); =20 - mutex_init(&csi->mutex); csi->shim =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(csi->shim)) { ret =3D PTR_ERR(csi->shim); - goto err_mutex; + return ret; } =20 - ret =3D ti_csi2rx_init_dma(csi); - if (ret) - goto err_mutex; + csi->drain.len =3D DRAIN_BUFFER_SIZE; + csi->drain.vaddr =3D dma_alloc_coherent(csi->dev, csi->drain.len, + &csi->drain.paddr, + GFP_KERNEL); + if (!csi->drain.vaddr) + return -ENOMEM; =20 ret =3D ti_csi2rx_v4l2_init(csi); - if (ret) - goto err_dma; - - ret =3D ti_csi2rx_init_vb2q(csi); if (ret) goto err_v4l2; =20 + for (i =3D 0; i < TI_CSI2RX_NUM_CTX; i++) { + csi->ctx[i].idx =3D i; + csi->ctx[i].csi =3D csi; + ret =3D ti_csi2rx_init_ctx(&csi->ctx[i]); + if (ret) + goto err_ctx; + } + ret =3D ti_csi2rx_notifier_register(csi); if (ret) - goto err_vb2q; + goto err_ctx; =20 ret =3D devm_of_platform_populate(csi->dev); if (ret) { dev_err(csi->dev, "Failed to create children: %d\n", ret); - goto err_subdev; + goto err_notifier; } =20 return 0; =20 -err_subdev: - ti_csi2rx_cleanup_subdev(csi); -err_vb2q: - ti_csi2rx_cleanup_vb2q(csi); -err_v4l2: +err_notifier: + ti_csi2rx_cleanup_notifier(csi); +err_ctx: + i--; + for (; i >=3D 0; i--) + ti_csi2rx_cleanup_ctx(&csi->ctx[i]); ti_csi2rx_cleanup_v4l2(csi); -err_dma: - ti_csi2rx_cleanup_dma(csi); -err_mutex: - mutex_destroy(&csi->mutex); +err_v4l2: + dma_free_coherent(csi->dev, csi->drain.len, csi->drain.vaddr, + csi->drain.paddr); return ret; } =20 static void ti_csi2rx_remove(struct platform_device *pdev) { struct ti_csi2rx_dev *csi =3D platform_get_drvdata(pdev); + unsigned int i; =20 - video_unregister_device(&csi->vdev); + for (i =3D 0; i < TI_CSI2RX_NUM_CTX; i++) + ti_csi2rx_cleanup_ctx(&csi->ctx[i]); =20 - ti_csi2rx_cleanup_vb2q(csi); - ti_csi2rx_cleanup_subdev(csi); + ti_csi2rx_cleanup_notifier(csi); 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Mon, 25 Aug 2025 09:25:54 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3r3747540; Mon, 25 Aug 2025 09:25:48 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 04/14] media: ti: j721e-csi2rx: prepare SHIM code for multiple contexts Date: Mon, 25 Aug 2025 19:55:12 +0530 Message-ID: <20250825142522.1826188-5-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav Currently the SHIM code to configure the context only touches the first context. Add support for writing to the context's registers based on the context index. Signed-off-by: Pratyush Yadav Signed-off-by: Jai Luthra Reviewed-by: Jacopo Mondi Reviewed-by: Laurent Pinchart Reviewed-by: Yemike Abhilash Chandra Signed-off-by: Rishikesh Donadkar --- .../media/platform/ti/j721e-csi2rx/j721e-csi2rx.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index cb52bc7afd1f..50a935494e43 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -27,7 +27,7 @@ #define SHIM_CNTL 0x10 #define SHIM_CNTL_PIX_RST BIT(0) =20 -#define SHIM_DMACNTX 0x20 +#define SHIM_DMACNTX(i) (0x20 + ((i) * 0x20)) #define SHIM_DMACNTX_EN BIT(31) #define SHIM_DMACNTX_YUV422 GENMASK(27, 26) #define SHIM_DMACNTX_DUAL_PCK_CFG BIT(24) @@ -38,7 +38,7 @@ #define SHIM_DMACNTX_SIZE_16 1 #define SHIM_DMACNTX_SIZE_32 2 =20 -#define SHIM_PSI_CFG0 0x24 +#define SHIM_PSI_CFG0(i) (0x24 + ((i) * 0x20)) #define SHIM_PSI_CFG0_SRC_TAG GENMASK(15, 0) #define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 16) =20 @@ -573,11 +573,13 @@ static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx= *ctx) break; } =20 - writel(reg, csi->shim + SHIM_DMACNTX); + reg |=3D FIELD_PREP(SHIM_DMACNTX_SIZE, fmt->size); + + writel(reg, csi->shim + SHIM_DMACNTX(ctx->idx)); =20 reg =3D FIELD_PREP(SHIM_PSI_CFG0_SRC_TAG, 0) | FIELD_PREP(SHIM_PSI_CFG0_DST_TAG, 0); - writel(reg, csi->shim + SHIM_PSI_CFG0); + writel(reg, csi->shim + SHIM_PSI_CFG0(ctx->idx)); } =20 static void ti_csi2rx_drain_callback(void *param) @@ -894,7 +896,7 @@ static int ti_csi2rx_start_streaming(struct vb2_queue *= vq, unsigned int count) err_pipeline: video_device_pipeline_stop(&ctx->vdev); writel(0, csi->shim + SHIM_CNTL); - writel(0, csi->shim + SHIM_DMACNTX); + writel(0, csi->shim + SHIM_DMACNTX(ctx->idx)); err: ti_csi2rx_cleanup_buffers(ctx, VB2_BUF_STATE_QUEUED); return ret; @@ -909,7 +911,7 @@ static void ti_csi2rx_stop_streaming(struct vb2_queue *= vq) video_device_pipeline_stop(&ctx->vdev); =20 writel(0, csi->shim + SHIM_CNTL); - writel(0, csi->shim + SHIM_DMACNTX); + writel(0, csi->shim + SHIM_DMACNTX(ctx->idx)); =20 ret =3D v4l2_subdev_call(csi->source, video, s_stream, 0); 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Mon, 25 Aug 2025 09:26:00 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 25 Aug 2025 09:26:00 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 25 Aug 2025 09:26:00 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3s3747540; Mon, 25 Aug 2025 09:25:54 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 05/14] media: ti: j721e-csi2rx: allocate DMA channel based on context index Date: Mon, 25 Aug 2025 19:55:13 +0530 Message-ID: <20250825142522.1826188-6-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav With multiple contexts, there needs to be a different DMA channel for each context. Earlier, the DMA channel name was hard coded to "rx0" for the sake of simplicity. Generate the DMA channel name based on its index and get the channel corresponding to the context. Signed-off-by: Pratyush Yadav Signed-off-by: Jai Luthra Reviewed-by: Jacopo Mondi Reviewed-by: Laurent Pinchart Reviewed-by: Yemike Abhilash Chandra Signed-off-by: Rishikesh Donadkar --- drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 50a935494e43..4b5e49c2244e 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -1042,9 +1042,11 @@ static int ti_csi2rx_init_dma(struct ti_csi2rx_ctx *= ctx) struct dma_slave_config cfg =3D { .src_addr_width =3D DMA_SLAVE_BUSWIDTH_16_BYTES, }; + char name[5]; int ret; =20 - ctx->dma.chan =3D dma_request_chan(ctx->csi->dev, "rx0"); + snprintf(name, sizeof(name), "rx%u", ctx->idx); + ctx->dma.chan =3D dma_request_chan(ctx->csi->dev, name); if (IS_ERR(ctx->dma.chan)) return PTR_ERR(ctx->dma.chan); =20 --=20 2.34.1 From nobody Fri Oct 3 20:26:50 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81D982FF669; Mon, 25 Aug 2025 14:26:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756131982; cv=none; b=AHxVcvQiSNXmGN3lYwQeKBrUtQ6c/AeMthOGuXjvYnzW+UCaYmj5JjzynzuQVOrRKsWWAt681y3b4gJmZrMxxrTjAw7klwudg8vrerNMLPLeBje7bxc1Y9HrS/2dK/roVOe11D7B15i8QL9GbVlY8bsNsSkiEVOfS9uUA/tu4m4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756131982; c=relaxed/simple; bh=y5c7ZNZi3L7/reZkaeePMtjgdTn7C1EldmJFKN4CuyM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sh2zPKl+dufAAMmvfuSZ62p5HOC/X1IHbrHIr7C7GpJ5gbMmch775M4RTZqzyJkpGdHhG0lT5ThCvhkDdNdOaCjabO43T8bK7vnbCtu7Cupl85O8bv+jukaEMgu4c5UHbwHAT6DqlaILsSQJafP+UsylBbkUlMv6ohCntpI07fs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=OTHcLK6P; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="OTHcLK6P" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57PEQ7VI826676; Mon, 25 Aug 2025 09:26:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756131967; bh=oiVZ7IC48GKfvfJx7HJNmkYC/6w7HvA9zxZFF1Zjlmg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OTHcLK6P2wPmYH9MCc01GAMqDIHRx55db9Y9E3UWNMV+s1C34o55yap+CSd6gxHXB sLVsXFMkkQFEQG8yok4fp6ibVxiDZthpuF2T8aASidJeL3STCsKLUqIhX748i6nRIj dSE56QTBsPDv6Xi4vnRktYExfvGlzKrzLJd9GDjY= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57PEQ7HX1235807 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 25 Aug 2025 09:26:07 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 25 Aug 2025 09:26:06 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 25 Aug 2025 09:26:06 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3t3747540; Mon, 25 Aug 2025 09:26:00 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 06/14] media: ti: j721e-csi2rx: add a subdev for the core device Date: Mon, 25 Aug 2025 19:55:14 +0530 Message-ID: <20250825142522.1826188-7-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra With single stream capture, it was simpler to use the video device as the media entity representing the main TI CSI2RX device. Now with multi stream capture coming into the picture, the model has shifted to each video device having a link to the main device's subdev. The routing would then be set on this subdev. Add this subdev, link each context to this subdev's entity and link the subdev's entity to the source. Also add an array of media pads. It will have one sink pad and source pads equal to the number of contexts. Reviewed-by: Yemike Abhilash Chandra Co-developed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav Signed-off-by: Jai Luthra Signed-off-by: Rishikesh Donadkar --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 259 +++++++++++++++--- 1 file changed, 228 insertions(+), 31 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 4b5e49c2244e..4e1c9db0dcf5 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -55,6 +55,11 @@ #define MAX_WIDTH_BYTES SZ_16K #define MAX_HEIGHT_LINES SZ_16K =20 +#define TI_CSI2RX_PAD_SINK 0 +#define TI_CSI2RX_PAD_FIRST_SOURCE 1 +#define TI_CSI2RX_NUM_SOURCE_PADS 1 +#define TI_CSI2RX_NUM_PADS (1 + TI_CSI2RX_NUM_SOURCE_PADS) + #define DRAIN_TIMEOUT_MS 50 #define DRAIN_BUFFER_SIZE SZ_32K =20 @@ -103,6 +108,7 @@ struct ti_csi2rx_ctx { struct mutex mutex; /* To serialize ioctls. */ struct v4l2_format v_fmt; struct ti_csi2rx_dma dma; + struct media_pad pad; u32 sequence; u32 idx; }; @@ -110,12 +116,15 @@ struct ti_csi2rx_ctx { struct ti_csi2rx_dev { struct device *dev; void __iomem *shim; + struct mutex mutex; /* To serialize ioctls. */ + unsigned int enable_count; struct v4l2_device v4l2_dev; struct media_device mdev; struct media_pipeline pipe; - struct media_pad pad; + struct media_pad pads[TI_CSI2RX_NUM_PADS]; struct v4l2_async_notifier notifier; struct v4l2_subdev *source; + struct v4l2_subdev subdev; struct ti_csi2rx_ctx ctx[TI_CSI2RX_NUM_CTX]; u8 pix_per_clk; /* Buffer to drain stale data from PSI-L endpoint */ @@ -126,6 +135,22 @@ struct ti_csi2rx_dev { } drain; }; =20 +static inline struct ti_csi2rx_dev *to_csi2rx_dev(struct v4l2_subdev *sd) +{ + return container_of(sd, struct ti_csi2rx_dev, subdev); +} + +static const struct v4l2_mbus_framefmt ti_csi2rx_default_fmt =3D { + .width =3D 640, + .height =3D 480, + .code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_SRGB, + .ycbcr_enc =3D V4L2_YCBCR_ENC_601, + .quantization =3D V4L2_QUANTIZATION_LIM_RANGE, + .xfer_func =3D V4L2_XFER_FUNC_SRGB, +}; + static const struct ti_csi2rx_fmt ti_csi2rx_formats[] =3D { { .fourcc =3D V4L2_PIX_FMT_YUYV, @@ -427,6 +452,17 @@ static int csi_async_notifier_complete(struct v4l2_asy= nc_notifier *notifier) struct ti_csi2rx_dev *csi =3D dev_get_drvdata(notifier->v4l2_dev->dev); int ret, i; =20 + /* Create link from source to subdev */ + ret =3D media_create_pad_link(&csi->source->entity, + CSI2RX_BRIDGE_SOURCE_PAD, + &csi->subdev.entity, + TI_CSI2RX_PAD_SINK, + MEDIA_LNK_FL_IMMUTABLE | + MEDIA_LNK_FL_ENABLED); + if (ret) + return ret; + + /* Create and link video nodes for all DMA contexts */ for (i =3D 0; i < TI_CSI2RX_NUM_CTX; i++) { struct ti_csi2rx_ctx *ctx =3D &csi->ctx[i]; struct video_device *vdev =3D &ctx->vdev; @@ -434,15 +470,17 @@ static int csi_async_notifier_complete(struct v4l2_as= ync_notifier *notifier) ret =3D video_register_device(vdev, VFL_TYPE_VIDEO, -1); if (ret) goto unregister_dev; - } =20 - ret =3D media_create_pad_link(&csi->source->entity, - CSI2RX_BRIDGE_SOURCE_PAD, - &vdev->entity, csi->pad.index, - MEDIA_LNK_FL_IMMUTABLE | - MEDIA_LNK_FL_ENABLED); - if (ret) - goto unregister_dev; + ret =3D media_create_pad_link(&csi->subdev.entity, + TI_CSI2RX_PAD_FIRST_SOURCE + ctx->idx, + &vdev->entity, 0, + MEDIA_LNK_FL_IMMUTABLE | + MEDIA_LNK_FL_ENABLED); + if (ret) { + video_unregister_device(vdev); + goto unregister_dev; + } + } =20 ret =3D v4l2_device_register_subdev_nodes(&csi->v4l2_dev); if (ret) @@ -452,8 +490,10 @@ static int csi_async_notifier_complete(struct v4l2_asy= nc_notifier *notifier) =20 unregister_dev: i--; - for (; i >=3D 0; i--) + for (; i >=3D 0; i--) { + media_entity_remove_links(&csi->ctx[i].vdev.entity); video_unregister_device(&csi->ctx[i].vdev); + } return ret; } =20 @@ -498,14 +538,13 @@ static int ti_csi2rx_notifier_register(struct ti_csi2= rx_dev *csi) } =20 /* Request maximum possible pixels per clock from the bridge */ -static void ti_csi2rx_request_max_ppc(struct ti_csi2rx_ctx *ctx) +static void ti_csi2rx_request_max_ppc(struct ti_csi2rx_dev *csi) { - struct ti_csi2rx_dev *csi =3D ctx->csi; u8 ppc =3D TI_CSI2RX_MAX_PIX_PER_CLK; struct media_pad *pad; int ret; =20 - pad =3D media_entity_remote_source_pad_unique(&ctx->vdev.entity); + pad =3D media_entity_remote_source_pad_unique(&csi->subdev.entity); if (!pad) return; =20 @@ -531,7 +570,7 @@ static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx *= ctx) writel(reg, csi->shim + SHIM_CNTL); =20 /* Negotiate pixel count from the source */ - ti_csi2rx_request_max_ppc(ctx); + ti_csi2rx_request_max_ppc(csi); =20 reg =3D SHIM_DMACNTX_EN; reg |=3D FIELD_PREP(SHIM_DMACNTX_FMT, fmt->csi_dt); @@ -885,7 +924,7 @@ static int ti_csi2rx_start_streaming(struct vb2_queue *= vq, unsigned int count) dma->state =3D TI_CSI2RX_DMA_ACTIVE; spin_unlock_irqrestore(&dma->lock, flags); =20 - ret =3D v4l2_subdev_call(csi->source, video, s_stream, 1); + ret =3D v4l2_subdev_call(&csi->subdev, video, s_stream, 1); if (ret) goto err_dma; =20 @@ -913,7 +952,7 @@ static void ti_csi2rx_stop_streaming(struct vb2_queue *= vq) writel(0, csi->shim + SHIM_CNTL); writel(0, csi->shim + SHIM_DMACNTX(ctx->idx)); =20 - ret =3D v4l2_subdev_call(csi->source, video, s_stream, 0); + ret =3D v4l2_subdev_call(&csi->subdev, video, s_stream, 0); if (ret) dev_err(csi->dev, "Failed to stop subdev stream\n"); =20 @@ -929,8 +968,114 @@ static const struct vb2_ops csi_vb2_qops =3D { .stop_streaming =3D ti_csi2rx_stop_streaming, }; =20 +static int ti_csi2rx_enum_mbus_code(struct v4l2_subdev *subdev, + struct v4l2_subdev_state *state, + struct v4l2_subdev_mbus_code_enum *code_enum) +{ + if (code_enum->index >=3D ARRAY_SIZE(ti_csi2rx_formats)) + return -EINVAL; + + code_enum->code =3D ti_csi2rx_formats[code_enum->index].code; + + return 0; +} + +static int ti_csi2rx_sd_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt; + + /* No transcoding, don't allow setting source fmt */ + if (format->pad > TI_CSI2RX_PAD_SINK) + return v4l2_subdev_get_fmt(sd, state, format); + + if (!find_format_by_code(format->format.code)) + format->format.code =3D ti_csi2rx_formats[0].code; + + format->format.field =3D V4L2_FIELD_NONE; + + fmt =3D v4l2_subdev_state_get_format(state, format->pad, format->stream); + *fmt =3D format->format; + + fmt =3D v4l2_subdev_state_get_format(state, TI_CSI2RX_PAD_FIRST_SOURCE, + format->stream); + *fmt =3D format->format; + + return 0; +} + +static int ti_csi2rx_sd_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct v4l2_mbus_framefmt *fmt; + + fmt =3D v4l2_subdev_state_get_format(state, TI_CSI2RX_PAD_SINK); + *fmt =3D ti_csi2rx_default_fmt; + + fmt =3D v4l2_subdev_state_get_format(state, TI_CSI2RX_PAD_FIRST_SOURCE); + *fmt =3D ti_csi2rx_default_fmt; + + return 0; +} + +static int ti_csi2rx_sd_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ti_csi2rx_dev *csi =3D to_csi2rx_dev(sd); + int ret =3D 0; + + mutex_lock(&csi->mutex); + + if (enable) { + if (csi->enable_count > 0) { + csi->enable_count++; + goto out; + } + + ret =3D v4l2_subdev_call(csi->source, video, s_stream, 1); + if (ret) + goto out; + + csi->enable_count++; + } else { + if (csi->enable_count =3D=3D 0) { + ret =3D -EINVAL; + goto out; + } + + if (--csi->enable_count > 0) + goto out; + + ret =3D v4l2_subdev_call(csi->source, video, s_stream, 0); + } + +out: + mutex_unlock(&csi->mutex); + return ret; +} + +static const struct v4l2_subdev_pad_ops ti_csi2rx_subdev_pad_ops =3D { + .enum_mbus_code =3D ti_csi2rx_enum_mbus_code, + .get_fmt =3D v4l2_subdev_get_fmt, + .set_fmt =3D ti_csi2rx_sd_set_fmt, +}; + +static const struct v4l2_subdev_video_ops ti_csi2rx_subdev_video_ops =3D { + .s_stream =3D ti_csi2rx_sd_s_stream, +}; + +static const struct v4l2_subdev_ops ti_csi2rx_subdev_ops =3D { + .video =3D &ti_csi2rx_subdev_video_ops, + .pad =3D &ti_csi2rx_subdev_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops ti_csi2rx_internal_ops =3D { + .init_state =3D ti_csi2rx_sd_init_state, +}; + static void ti_csi2rx_cleanup_v4l2(struct ti_csi2rx_dev *csi) { + v4l2_subdev_cleanup(&csi->subdev); media_device_unregister(&csi->mdev); v4l2_device_unregister(&csi->v4l2_dev); media_device_cleanup(&csi->mdev); @@ -988,14 +1133,22 @@ static int ti_csi2rx_link_validate(struct media_link= *link) struct v4l2_subdev_format source_fmt =3D { .which =3D V4L2_SUBDEV_FORMAT_ACTIVE, .pad =3D link->source->index, + .stream =3D 0, }; + struct v4l2_subdev_state *state; const struct ti_csi2rx_fmt *ti_fmt; int ret; =20 - ret =3D v4l2_subdev_call_state_active(csi->source, pad, - get_fmt, &source_fmt); - if (ret) - return ret; + state =3D v4l2_subdev_lock_and_get_active_state(&csi->subdev); + ret =3D v4l2_subdev_call(&csi->subdev, pad, get_fmt, state, &source_fmt); + v4l2_subdev_unlock_state(state); + + if (ret) { + dev_dbg(csi->dev, + "Skipping validation as no format present on \"%s\":%u:0\n", + link->source->entity->name, link->source->index); + return 0; + } =20 if (source_fmt.format.width !=3D csi_fmt->width) { dev_dbg(csi->dev, "Width does not match (source %u, sink %u)\n", @@ -1025,8 +1178,9 @@ static int ti_csi2rx_link_validate(struct media_link = *link) =20 if (ti_fmt->fourcc !=3D csi_fmt->pixelformat) { dev_dbg(csi->dev, - "Cannot transform source fmt 0x%x to sink fmt 0x%x\n", - ti_fmt->fourcc, csi_fmt->pixelformat); + "Cannot transform \"%s\":%u format %p4cc to %p4cc\n", + link->source->entity->name, link->source->index, + &ti_fmt->fourcc, &csi_fmt->pixelformat); return -EPIPE; } =20 @@ -1037,6 +1191,10 @@ static const struct media_entity_operations ti_csi2r= x_video_entity_ops =3D { .link_validate =3D ti_csi2rx_link_validate, }; =20 +static const struct media_entity_operations ti_csi2rx_subdev_entity_ops = =3D { + .link_validate =3D v4l2_subdev_link_validate, +}; + static int ti_csi2rx_init_dma(struct ti_csi2rx_ctx *ctx) { struct dma_slave_config cfg =3D { @@ -1062,6 +1220,7 @@ static int ti_csi2rx_init_dma(struct ti_csi2rx_ctx *c= tx) static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev *csi) { struct media_device *mdev =3D &csi->mdev; + struct v4l2_subdev *sd =3D &csi->subdev; int ret; =20 mdev->dev =3D csi->dev; @@ -1074,16 +1233,51 @@ static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev= *csi) =20 ret =3D v4l2_device_register(csi->dev, &csi->v4l2_dev); if (ret) - return ret; + goto cleanup_media; =20 ret =3D media_device_register(mdev); - if (ret) { - v4l2_device_unregister(&csi->v4l2_dev); - media_device_cleanup(mdev); - return ret; - } + if (ret) + goto unregister_v4l2; + + v4l2_subdev_init(sd, &ti_csi2rx_subdev_ops); + sd->internal_ops =3D &ti_csi2rx_internal_ops; + sd->entity.function =3D MEDIA_ENT_F_VID_IF_BRIDGE; + sd->flags =3D V4L2_SUBDEV_FL_HAS_DEVNODE; + strscpy(sd->name, dev_name(csi->dev), sizeof(sd->name)); + sd->dev =3D csi->dev; + sd->entity.ops =3D &ti_csi2rx_subdev_entity_ops; + + csi->pads[TI_CSI2RX_PAD_SINK].flags =3D MEDIA_PAD_FL_SINK; + + for (unsigned int i =3D TI_CSI2RX_PAD_FIRST_SOURCE; + i < TI_CSI2RX_NUM_PADS; i++) + csi->pads[i].flags =3D MEDIA_PAD_FL_SOURCE; + + ret =3D media_entity_pads_init(&sd->entity, ARRAY_SIZE(csi->pads), + csi->pads); + if (ret) + goto unregister_media; + + ret =3D v4l2_subdev_init_finalize(sd); + if (ret) + goto unregister_media; + + ret =3D v4l2_device_register_subdev(&csi->v4l2_dev, sd); + if (ret) + goto cleanup_subdev; =20 return 0; + +cleanup_subdev: + v4l2_subdev_cleanup(sd); +unregister_media: + media_device_unregister(mdev); +unregister_v4l2: + v4l2_device_unregister(&csi->v4l2_dev); +cleanup_media: + media_device_cleanup(mdev); + + return ret; } =20 static int ti_csi2rx_init_ctx(struct ti_csi2rx_ctx *ctx) @@ -1110,9 +1304,9 @@ static int ti_csi2rx_init_ctx(struct ti_csi2rx_ctx *c= tx) =20 ti_csi2rx_fill_fmt(fmt, &ctx->v_fmt); =20 - csi->pad.flags =3D MEDIA_PAD_FL_SINK; + ctx->pad.flags =3D MEDIA_PAD_FL_SINK; vdev->entity.ops =3D &ti_csi2rx_video_entity_ops; - ret =3D media_entity_pads_init(&ctx->vdev.entity, 1, &csi->pad); + ret =3D media_entity_pads_init(&ctx->vdev.entity, 1, &ctx->pad); if (ret) return ret; =20 @@ -1173,6 +1367,8 @@ static int ti_csi2rx_probe(struct platform_device *pd= ev) if (!csi->drain.vaddr) return -ENOMEM; =20 + mutex_init(&csi->mutex); + ret =3D ti_csi2rx_v4l2_init(csi); if (ret) goto err_v4l2; @@ -1205,6 +1401,7 @@ static int ti_csi2rx_probe(struct platform_device *pd= ev) ti_csi2rx_cleanup_ctx(&csi->ctx[i]); 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Mon, 25 Aug 2025 09:26:12 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3u3747540; Mon, 25 Aug 2025 09:26:07 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 07/14] media: ti: j721e-csi2rx: get number of contexts from device tree Date: Mon, 25 Aug 2025 19:55:15 +0530 Message-ID: <20250825142522.1826188-8-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav Different platforms that use this driver might have different number of DMA channels allocated for CSI. So only as many DMA contexts can be used as the number of DMA channels available. Get the number of channels provided via device tree and only configure that many contexts, and hence only that many pads. Reviewed-by: Yemike Abhilash Chandra Signed-off-by: Pratyush Yadav Co-developed-by: Jai Luthra Signed-off-by: Jai Luthra Signed-off-by: Rishikesh Donadkar --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 42 ++++++++++++++----- 1 file changed, 31 insertions(+), 11 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 4e1c9db0dcf5..6cab7642aa10 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -44,7 +44,7 @@ =20 #define TI_CSI2RX_MAX_PIX_PER_CLK 4 #define PSIL_WORD_SIZE_BYTES 16 -#define TI_CSI2RX_NUM_CTX 1 +#define TI_CSI2RX_MAX_CTX 32 =20 /* * There are no hard limits on the width or height. The DMA engine can han= dle @@ -57,8 +57,8 @@ =20 #define TI_CSI2RX_PAD_SINK 0 #define TI_CSI2RX_PAD_FIRST_SOURCE 1 -#define TI_CSI2RX_NUM_SOURCE_PADS 1 -#define TI_CSI2RX_NUM_PADS (1 + TI_CSI2RX_NUM_SOURCE_PADS) +#define TI_CSI2RX_MAX_SOURCE_PADS TI_CSI2RX_MAX_CTX +#define TI_CSI2RX_MAX_PADS (1 + TI_CSI2RX_MAX_SOURCE_PADS) =20 #define DRAIN_TIMEOUT_MS 50 #define DRAIN_BUFFER_SIZE SZ_32K @@ -118,14 +118,15 @@ struct ti_csi2rx_dev { void __iomem *shim; struct mutex mutex; /* To serialize ioctls. */ unsigned int enable_count; + unsigned int num_ctx; struct v4l2_device v4l2_dev; struct media_device mdev; struct media_pipeline pipe; - struct media_pad pads[TI_CSI2RX_NUM_PADS]; + struct media_pad pads[TI_CSI2RX_MAX_PADS]; struct v4l2_async_notifier notifier; struct v4l2_subdev *source; struct v4l2_subdev subdev; - struct ti_csi2rx_ctx ctx[TI_CSI2RX_NUM_CTX]; + struct ti_csi2rx_ctx ctx[TI_CSI2RX_MAX_CTX]; u8 pix_per_clk; /* Buffer to drain stale data from PSI-L endpoint */ struct { @@ -463,7 +464,7 @@ static int csi_async_notifier_complete(struct v4l2_asyn= c_notifier *notifier) return ret; =20 /* Create and link video nodes for all DMA contexts */ - for (i =3D 0; i < TI_CSI2RX_NUM_CTX; i++) { + for (i =3D 0; i < csi->num_ctx; i++) { struct ti_csi2rx_ctx *ctx =3D &csi->ctx[i]; struct video_device *vdev =3D &ctx->vdev; =20 @@ -1250,10 +1251,11 @@ static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev= *csi) csi->pads[TI_CSI2RX_PAD_SINK].flags =3D MEDIA_PAD_FL_SINK; =20 for (unsigned int i =3D TI_CSI2RX_PAD_FIRST_SOURCE; - i < TI_CSI2RX_NUM_PADS; i++) + i < TI_CSI2RX_PAD_FIRST_SOURCE + csi->num_ctx; i++) csi->pads[i].flags =3D MEDIA_PAD_FL_SOURCE; =20 - ret =3D media_entity_pads_init(&sd->entity, ARRAY_SIZE(csi->pads), + ret =3D media_entity_pads_init(&sd->entity, + TI_CSI2RX_PAD_FIRST_SOURCE + csi->num_ctx, csi->pads); if (ret) goto unregister_media; @@ -1344,8 +1346,9 @@ static int ti_csi2rx_init_ctx(struct ti_csi2rx_ctx *c= tx) =20 static int ti_csi2rx_probe(struct platform_device *pdev) { + struct device_node *np =3D pdev->dev.of_node; struct ti_csi2rx_dev *csi; - int ret, i; + int ret, i, count; =20 csi =3D devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); if (!csi) @@ -1367,13 +1370,29 @@ static int ti_csi2rx_probe(struct platform_device *= pdev) if (!csi->drain.vaddr) return -ENOMEM; =20 + /* Only use as many contexts as the number of DMA channels allocated. */ + count =3D of_property_count_strings(np, "dma-names"); + if (count < 0) { + dev_err(csi->dev, "Failed to get DMA channel count: %d\n", count); + ret =3D count; + goto err_dma_chan; + } + + csi->num_ctx =3D count; + if (csi->num_ctx > TI_CSI2RX_MAX_CTX) { + dev_err(csi->dev, + "%u DMA channels passed. Maximum is %u.\n", + csi->num_ctx, TI_CSI2RX_MAX_CTX); + goto err_dma_chan; + } + mutex_init(&csi->mutex); =20 ret =3D ti_csi2rx_v4l2_init(csi); if (ret) goto err_v4l2; =20 - for (i =3D 0; i < TI_CSI2RX_NUM_CTX; i++) { + for (i =3D 0; i < csi->num_ctx; i++) { csi->ctx[i].idx =3D i; csi->ctx[i].csi =3D csi; ret =3D ti_csi2rx_init_ctx(&csi->ctx[i]); @@ -1402,6 +1421,7 @@ static int ti_csi2rx_probe(struct platform_device *pd= ev) ti_csi2rx_cleanup_v4l2(csi); err_v4l2: mutex_destroy(&csi->mutex); +err_dma_chan: dma_free_coherent(csi->dev, csi->drain.len, csi->drain.vaddr, csi->drain.paddr); return ret; @@ -1412,7 +1432,7 @@ static void ti_csi2rx_remove(struct platform_device *= pdev) struct ti_csi2rx_dev *csi =3D platform_get_drvdata(pdev); unsigned int i; =20 - for (i =3D 0; i < TI_CSI2RX_NUM_CTX; i++) + for (i =3D 0; i < csi->num_ctx; i++) ti_csi2rx_cleanup_ctx(&csi->ctx[i]); =20 ti_csi2rx_cleanup_notifier(csi); --=20 2.34.1 From nobody Fri Oct 3 20:26:50 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 516582FFDD3; Mon, 25 Aug 2025 14:26:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132000; cv=none; b=PTCy1N61cdDN29mDI8m11bqInoPTR+NnpRd9ITJJGBa2JZ+BPb1yvnVEGhZ4WL0wXu19uzocgVzkze9yDqmrPffGHHUhNYZ+HhRc5GyOJoAvkdaH9AQV6kMCorao7zoD4AiJqqupcUpASHKfIEQz6Pbt98IR7T0EsUof+dI2QOg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132000; c=relaxed/simple; bh=+ATgwERUjCMk+mbyg0rUpYLOyGZJJnUWX/wmnPZ9hlY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CU/26h5zshXHBD+cEQvVoZNPlxYcjGZud3awKuQOuD6UZv4hyos4ZKzhYM5Fhd7QEyP0rJbsVAZFLZa//H2W0fs/Jzk6Qx8a476CffGKlaz8v9Qv83EgkYA9SGeM6YLlmeK7OYpJXOXCoDUc77JYx98AR4Kud8S9rd108VKG8es= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=gFg7BsLo; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="gFg7BsLo" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57PEQJMu1294928; Mon, 25 Aug 2025 09:26:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756131979; bh=H+ovSwcuIBBodDc5Y/doW/VxN5p2BDHHt12bqipJ0o8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gFg7BsLofrHB3OxFKQu2cNulnBGQj90hQdHojjB+p/h4i/xKTzHQVI+lJIEXmY7lJ 2OwmTHqOYSBMoV7R7Nx7/Op7TshWCHRvaixgLE1sHhC2mOQ0YDDO64viQpIAGNsoTx VA6Oc4/t2qG+jhFKIXSTm6sG4ICKl8kHnFjg58Go= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57PEQJE71235883 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 25 Aug 2025 09:26:19 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 25 Aug 2025 09:26:18 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 25 Aug 2025 09:26:18 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3v3747540; Mon, 25 Aug 2025 09:26:13 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 08/14] media: cadence: csi2rx: add get_frame_desc wrapper Date: Mon, 25 Aug 2025 19:55:16 +0530 Message-ID: <20250825142522.1826188-9-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav J721E wrapper CSI2RX driver needs to get the frame descriptor from the source to find out info about virtual channel. This driver itself does not touch the routing or virtual channels in any way. So simply pass the descriptor through from the source. Signed-off-by: Pratyush Yadav Signed-off-by: Jai Luthra Reviewed-by: Jacopo Mondi Reviewed-by: Changhuang Liang Reviewed-by: Laurent Pinchart Reviewed-by: Yemike Abhilash Chandra Signed-off-by: Rishikesh Donadkar --- drivers/media/platform/cadence/cdns-csi2rx.c | 24 ++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/p= latform/cadence/cdns-csi2rx.c index 828b4ba4301d..3c99de56c095 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -235,6 +235,21 @@ static const struct csi2rx_fmt *csi2rx_get_fmt_by_code= (u32 code) return NULL; } =20 +static int csi2rx_get_frame_desc_from_source(struct csi2rx_priv *csi2rx, + struct v4l2_mbus_frame_desc *fd) +{ + struct media_pad *remote_pad; + + remote_pad =3D media_entity_remote_source_pad_unique(&csi2rx->subdev.enti= ty); + if (!remote_pad) { + dev_err(csi2rx->dev, "No remote pad found for sink\n"); + return -ENODEV; + } + + return v4l2_subdev_call(csi2rx->source_subdev, pad, get_frame_desc, + remote_pad->index, fd); +} + static inline struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) { @@ -607,10 +622,19 @@ int cdns_csi2rx_negotiate_ppc(struct v4l2_subdev *sub= dev, unsigned int pad, } EXPORT_SYMBOL_GPL_FOR_MODULES(cdns_csi2rx_negotiate_ppc, "j721e-csi2rx"); =20 +static int csi2rx_get_frame_desc(struct v4l2_subdev *subdev, unsigned int = pad, + struct v4l2_mbus_frame_desc *fd) +{ + struct csi2rx_priv *csi2rx =3D v4l2_subdev_to_csi2rx(subdev); + + return csi2rx_get_frame_desc_from_source(csi2rx, fd); +} + static const struct v4l2_subdev_pad_ops csi2rx_pad_ops =3D { .enum_mbus_code =3D csi2rx_enum_mbus_code, .get_fmt =3D v4l2_subdev_get_fmt, .set_fmt =3D csi2rx_set_fmt, + .get_frame_desc =3D csi2rx_get_frame_desc, }; =20 static const struct v4l2_subdev_video_ops csi2rx_video_ops =3D { --=20 2.34.1 From nobody Fri Oct 3 20:26:50 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B707301038; 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Mon, 25 Aug 2025 09:26:25 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 25 Aug 2025 09:26:24 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 25 Aug 2025 09:26:25 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3w3747540; Mon, 25 Aug 2025 09:26:19 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 09/14] media: ti: j721e-csi2rx: add support for processing virtual channels Date: Mon, 25 Aug 2025 19:55:17 +0530 Message-ID: <20250825142522.1826188-10-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra Use get_frame_desc() to get the frame desc from the connected source, and use the provided virtual channel instead of hardcoded one. get_frame_desc() returns the same information when called on each stream start, so instead get the VCs for all the routed stream at first stream start and cache this information in the driver. get_frame_desc() works per stream, but as we don't support multiple streams yet, we will just always use stream 0. If the source doesn't support get_frame_desc(), fall back to the previous method of always capturing virtual channel 0. Reviewed-by: Yemike Abhilash Chandra Co-developed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav Signed-off-by: Jai Luthra Signed-off-by: Rishikesh Donadkar --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 6cab7642aa10..45e9001fa35b 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -32,6 +32,7 @@ #define SHIM_DMACNTX_YUV422 GENMASK(27, 26) #define SHIM_DMACNTX_DUAL_PCK_CFG BIT(24) #define SHIM_DMACNTX_SIZE GENMASK(21, 20) +#define SHIM_DMACNTX_VC GENMASK(9, 6) #define SHIM_DMACNTX_FMT GENMASK(5, 0) #define SHIM_DMACNTX_YUV422_MODE_11 3 #define SHIM_DMACNTX_SIZE_8 0 @@ -103,6 +104,7 @@ struct ti_csi2rx_dev; =20 struct ti_csi2rx_ctx { struct ti_csi2rx_dev *csi; + struct v4l2_subdev_route *route; struct video_device vdev; struct vb2_queue vidq; struct mutex mutex; /* To serialize ioctls. */ @@ -111,6 +113,8 @@ struct ti_csi2rx_ctx { struct media_pad pad; u32 sequence; u32 idx; + u32 vc; + u32 stream; }; =20 struct ti_csi2rx_dev { @@ -134,6 +138,7 @@ struct ti_csi2rx_dev { dma_addr_t paddr; size_t len; } drain; + bool vc_cached; }; =20 static inline struct ti_csi2rx_dev *to_csi2rx_dev(struct v4l2_subdev *sd) @@ -614,6 +619,7 @@ static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx *= ctx) } =20 reg |=3D FIELD_PREP(SHIM_DMACNTX_SIZE, fmt->size); + reg |=3D FIELD_PREP(SHIM_DMACNTX_VC, ctx->vc); =20 writel(reg, csi->shim + SHIM_DMACNTX(ctx->idx)); =20 @@ -887,6 +893,83 @@ static void ti_csi2rx_buffer_queue(struct vb2_buffer *= vb) } } =20 +static int ti_csi2rx_get_route(struct ti_csi2rx_ctx *ctx) +{ + struct ti_csi2rx_dev *csi =3D ctx->csi; + struct media_pad *pad; + struct v4l2_subdev_state *state; + struct v4l2_subdev_route *r; + + /* Get the source pad connected to this ctx */ + pad =3D media_entity_remote_source_pad_unique(ctx->pad.entity); + if (!pad) { + dev_err(csi->dev, "No pad connected to ctx %d\n", ctx->idx); + v4l2_subdev_unlock_state(state); + return -ENODEV; + } + + state =3D v4l2_subdev_lock_and_get_active_state(&csi->subdev); + + for_each_active_route(&state->routing, r) { + if (!(r->flags & V4L2_SUBDEV_ROUTE_FL_ACTIVE)) + continue; + if (r->source_pad !=3D pad->index) + continue; + + ctx->route =3D r; + } + + v4l2_subdev_unlock_state(state); + + if (!ctx->route) + return -ENODEV; + + return 0; +} + +static int ti_csi2rx_get_vc(struct ti_csi2rx_ctx *ctx) +{ + struct ti_csi2rx_dev *csi =3D ctx->csi; + struct ti_csi2rx_ctx *curr_ctx; + struct v4l2_mbus_frame_desc fd; + struct media_pad *source_pad; + struct v4l2_subdev_route *curr_route; + int ret; + unsigned int i, j; + + /* Get the frame desc form source */ + source_pad =3D media_entity_remote_pad_unique(&csi->subdev.entity, MEDIA_= PAD_FL_SOURCE); + if (!source_pad) + return -ENODEV; + + ret =3D v4l2_subdev_call(csi->source, pad, get_frame_desc, source_pad->in= dex, &fd); + if (ret) + return ret; + + if (fd.type !=3D V4L2_MBUS_FRAME_DESC_TYPE_CSI2) + return -EINVAL; + + for (i =3D 0; i < csi->num_ctx; i++) { + curr_ctx =3D &csi->ctx[i]; + + /* Capture VC 0 by default */ + curr_ctx->vc =3D 0; + + ret =3D ti_csi2rx_get_route(curr_ctx); + if (ret) + continue; + + curr_route =3D curr_ctx->route; + curr_ctx->stream =3D curr_route->sink_stream; + + for (j =3D 0; j < fd.num_entries; j++) + if (curr_ctx->stream =3D=3D fd.entry[j].stream) + curr_ctx->vc =3D fd.entry[j].bus.csi2.vc; + } + + return 0; +} + static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int co= unt) { struct ti_csi2rx_ctx *ctx =3D vb2_get_drv_priv(vq); @@ -907,6 +990,25 @@ static int ti_csi2rx_start_streaming(struct vb2_queue = *vq, unsigned int count) if (ret) goto err; =20 + /* If no stream is routed to this ctx, exit early */ + ret =3D ti_csi2rx_get_route(ctx); + if (ret) + goto err; + + /* Get the VC for all enabled ctx on first stream start */ + mutex_lock(&csi->mutex); + if (!csi->vc_cached) { + ret =3D ti_csi2rx_get_vc(ctx); + if (ret =3D=3D -ENOIOCTLCMD) { + ctx->vc =3D 0; + } else if (ret < 0) { + mutex_unlock(&csi->mutex); + goto err; + } + csi->vc_cached =3D true; + } + mutex_unlock(&csi->mutex); + ti_csi2rx_setup_shim(ctx); =20 ctx->sequence =3D 0; @@ -953,6 +1055,10 @@ static void ti_csi2rx_stop_streaming(struct vb2_queue= *vq) writel(0, csi->shim + SHIM_CNTL); writel(0, csi->shim + SHIM_DMACNTX(ctx->idx)); =20 + mutex_lock(&csi->mutex); + csi->vc_cached =3D false; + mutex_unlock(&csi->mutex); + ret =3D v4l2_subdev_call(&csi->subdev, video, s_stream, 0); if (ret) dev_err(csi->dev, "Failed to stop subdev stream\n"); @@ -1306,6 +1412,8 @@ static int ti_csi2rx_init_ctx(struct ti_csi2rx_ctx *c= tx) =20 ti_csi2rx_fill_fmt(fmt, &ctx->v_fmt); =20 + ctx->route =3D NULL; + ctx->pad.flags =3D MEDIA_PAD_FL_SINK; vdev->entity.ops =3D &ti_csi2rx_video_entity_ops; ret =3D media_entity_pads_init(&ctx->vdev.entity, 1, &ctx->pad); --=20 2.34.1 From nobody Fri Oct 3 20:26:50 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3C32301036; 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Mon, 25 Aug 2025 09:26:31 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 25 Aug 2025 09:26:31 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 25 Aug 2025 09:26:31 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN3x3747540; Mon, 25 Aug 2025 09:26:25 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 10/14] media: cadence: csi2rx: add multistream support Date: Mon, 25 Aug 2025 19:55:18 +0530 Message-ID: <20250825142522.1826188-11-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra Cadence CSI-2 bridge IP supports capturing multiple virtual "streams" of data over the same physical interface using MIPI Virtual Channels. While the hardware IP supports usecases where streams coming in the sink pad can be broadcasted to multiple source pads, the driver will need significant re-architecture to make that possible. The two users of this IP in mainline linux are TI Shim and StarFive JH7110 CAMSS, and both have only integrated the first source pad i.e stream0 of this IP. So for now keep it simple and only allow 1-to-1 mapping of streams from sink to source, without any broadcasting. The enable_streams() API in v4l2 supports passing a bitmask to enable each pad/stream combination individually on any media subdev. Use this API instead of s_stream() API. Implement the enable_stream and disable_stream hooks in place of the stream-unaware s_stream hook. Implement a fallback s_stream hook that internally calls enable_stream on each source pad, for consumer drivers that don't use multi-stream APIs to still work. The helper function v4l2_subdev_s_stream_helper() form the v4l2 framework is not used here as it is meant only for the subedvs that have a single source pad and this hardware IP supports having multiple source pads. Signed-off-by: Jai Luthra Reviewed-by: Changhuang Liang Reviewed-by: Yemike Abhilash Chandra Co-developed-by: Rishikesh Donadkar Signed-off-by: Rishikesh Donadkar --- drivers/media/platform/cadence/cdns-csi2rx.c | 352 +++++++++++++++---- 1 file changed, 275 insertions(+), 77 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/p= latform/cadence/cdns-csi2rx.c index 3c99de56c095..11b73c79adff 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -141,6 +141,7 @@ struct csi2rx_priv { struct phy *dphy; =20 u8 num_pixels[CSI2RX_STREAMS_MAX]; + u32 vc_select[CSI2RX_STREAMS_MAX]; u8 lanes[CSI2RX_LANES_MAX]; u8 num_lanes; u8 max_lanes; @@ -279,29 +280,43 @@ static void csi2rx_reset(struct csi2rx_priv *csi2rx) =20 static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx) { - struct media_pad *src_pad =3D - &csi2rx->source_subdev->entity.pads[csi2rx->source_pad]; union phy_configure_opts opts =3D { }; struct phy_configure_opts_mipi_dphy *cfg =3D &opts.mipi_dphy; - struct v4l2_subdev_format sd_fmt =3D { - .which =3D V4L2_SUBDEV_FORMAT_ACTIVE, - .pad =3D CSI2RX_PAD_SINK, - }; + struct v4l2_mbus_framefmt *framefmt; + struct v4l2_subdev_state *state; const struct csi2rx_fmt *fmt; + int source_pad =3D csi2rx->source_pad; + struct media_pad *pad =3D &csi2rx->source_subdev->entity.pads[source_pad]; s64 link_freq; int ret; + u32 bpp; =20 - ret =3D v4l2_subdev_call_state_active(&csi2rx->subdev, pad, get_fmt, - &sd_fmt); - if (ret < 0) - return ret; + state =3D v4l2_subdev_get_locked_active_state(&csi2rx->subdev); =20 - fmt =3D csi2rx_get_fmt_by_code(sd_fmt.format.code); + /* + * For multi-stream transmitters there is no single pixel rate. + * + * In multistream usecase pass bpp as 0 so that v4l2_get_link_freq() + * returns an error if it falls back to V4L2_CID_PIXEL_RATE. + */ + if (state->routing.num_routes > 1) { + bpp =3D 0; + } else { + framefmt =3D v4l2_subdev_state_get_format(state, CSI2RX_PAD_SINK, 0); + if (!framefmt) { + dev_err(csi2rx->dev, "Did not find active sink format\n"); + return -EINVAL; + } + + fmt =3D csi2rx_get_fmt_by_code(framefmt->code); + bpp =3D fmt->bpp; + } =20 - link_freq =3D v4l2_get_link_freq(src_pad, - fmt->bpp, 2 * csi2rx->num_lanes); - if (link_freq < 0) + link_freq =3D v4l2_get_link_freq(pad, bpp, 2 * csi2rx->num_lanes); + if (link_freq < 0) { + dev_err(csi2rx->dev, "Unable to calculate link frequency\n"); return link_freq; + } =20 ret =3D phy_mipi_dphy_get_default_config_for_hsclk(link_freq, csi2rx->num_lanes, cfg); @@ -399,11 +414,7 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) csi2rx->num_pixels[i]), csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); =20 - /* - * Enable one virtual channel. When multiple virtual channels - * are supported this will have to be changed. - */ - writel(CSI2RX_STREAM_DATA_CFG_VC_SELECT(0), + writel(csi2rx->vc_select[i], csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i)); =20 writel(CSI2RX_STREAM_CTRL_START, @@ -416,16 +427,10 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) =20 reset_control_deassert(csi2rx->sys_rst); =20 - ret =3D v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, true); - if (ret) - goto err_disable_sysclk; - clk_disable_unprepare(csi2rx->p_clk); =20 return 0; =20 -err_disable_sysclk: - clk_disable_unprepare(csi2rx->sys_clk); err_disable_pixclk: for (; i > 0; i--) { reset_control_assert(csi2rx->pixel_rst[i - 1]); @@ -474,9 +479,6 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx) reset_control_assert(csi2rx->p_rst); clk_disable_unprepare(csi2rx->p_clk); =20 - if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false)) - dev_warn(csi2rx->dev, "Couldn't disable our subdev\n"); - if (csi2rx->dphy) { writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); =20 @@ -500,37 +502,134 @@ static int csi2rx_log_status(struct v4l2_subdev *sd) return 0; } =20 -static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable) +static void csi2rx_update_vc_select(struct csi2rx_priv *csi2rx, + struct v4l2_subdev_state *state) { - struct csi2rx_priv *csi2rx =3D v4l2_subdev_to_csi2rx(subdev); - int ret =3D 0; - - mutex_lock(&csi2rx->lock); - - if (enable) { - /* - * If we're not the first users, there's no need to - * enable the whole controller. - */ - if (!csi2rx->count) { - ret =3D csi2rx_start(csi2rx); - if (ret) - goto out; + struct v4l2_mbus_frame_desc fd =3D {0}; + struct v4l2_subdev_route *route; + unsigned int i; + int ret; + + /* Capture VC=3D0 by default */ + for (i =3D 0; i < CSI2RX_STREAMS_MAX; i++) + csi2rx->vc_select[i] =3D CSI2RX_STREAM_DATA_CFG_VC_SELECT(0); + + ret =3D csi2rx_get_frame_desc_from_source(csi2rx, &fd); + if (ret || fd.type !=3D V4L2_MBUS_FRAME_DESC_TYPE_CSI2) { + dev_dbg(csi2rx->dev, + "Failed to get source frame desc, allowing only VC=3D0\n"); + return; + } + + /* If source provides per-stream VC info, use it to filter by VC */ + memset(csi2rx->vc_select, 0, sizeof(csi2rx->vc_select)); + + for_each_active_route(&state->routing, route) { + u32 cdns_stream =3D route->source_pad - CSI2RX_PAD_SOURCE_STREAM0; + + for (i =3D 0; i < fd.num_entries; i++) { + if (fd.entry[i].stream !=3D route->sink_stream) + continue; + + csi2rx->vc_select[cdns_stream] |=3D + CSI2RX_STREAM_DATA_CFG_VC_SELECT(fd.entry[i].bus.csi2.vc); } + } +} =20 - csi2rx->count++; - } else { - csi2rx->count--; +static int csi2rx_enable_streams(struct v4l2_subdev *subdev, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct csi2rx_priv *csi2rx =3D v4l2_subdev_to_csi2rx(subdev); + u64 sink_streams; + int ret; + + sink_streams =3D v4l2_subdev_state_xlate_streams(state, pad, + CSI2RX_PAD_SINK, + &streams_mask); + + guard(mutex)(&csi2rx->lock); + /* + * If we're not the first users, there's no need to + * enable the whole controller. + */ + if (!csi2rx->count) { + csi2rx_update_vc_select(csi2rx, state); + ret =3D csi2rx_start(csi2rx); + if (ret) + return ret; + } =20 - /* - * Let the last user turn off the lights. - */ + /* Start streaming on the source */ + ret =3D v4l2_subdev_enable_streams(csi2rx->source_subdev, csi2rx->source_= pad, + sink_streams); + if (ret) { + dev_err(csi2rx->dev, + "Failed to start streams %#llx on subdev\n", + sink_streams); if (!csi2rx->count) csi2rx_stop(csi2rx); + return ret; + } + + csi2rx->count++; + return 0; +} + +static int csi2rx_disable_streams(struct v4l2_subdev *subdev, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct csi2rx_priv *csi2rx =3D v4l2_subdev_to_csi2rx(subdev); + u64 sink_streams; + + sink_streams =3D v4l2_subdev_state_xlate_streams(state, pad, + CSI2RX_PAD_SINK, + &streams_mask); + + if (v4l2_subdev_disable_streams(csi2rx->source_subdev, + csi2rx->source_pad, sink_streams)) { + dev_err(csi2rx->dev, "Couldn't disable our subdev\n"); + } + + guard(mutex)(&csi2rx->lock); + csi2rx->count--; + + /* Let the last user turn off the lights. */ + if (!csi2rx->count) + csi2rx_stop(csi2rx); + + return 0; +} + +static int csi2rx_s_stream_fallback(struct v4l2_subdev *sd, int enable) +{ + struct v4l2_subdev_state *state; + struct v4l2_subdev_route *route; + u64 mask[CSI2RX_PAD_MAX] =3D {0}; + int i, ret; + + /* Find the stream mask on all source pads */ + state =3D v4l2_subdev_lock_and_get_active_state(sd); + for (i =3D CSI2RX_PAD_SOURCE_STREAM0; i < CSI2RX_PAD_MAX; i++) { + for_each_active_route(&state->routing, route) { + if (route->source_pad =3D=3D i) + mask[i] |=3D BIT_ULL(route->source_stream); + } + } + v4l2_subdev_unlock_state(state); + + /* Start streaming on each pad */ + for (i =3D CSI2RX_PAD_SOURCE_STREAM0; i < CSI2RX_PAD_MAX; i++) { + if (enable) + ret =3D v4l2_subdev_enable_streams(sd, i, mask[i]); + else + ret =3D v4l2_subdev_disable_streams(sd, i, mask[i]); + if (ret) + return ret; } =20 -out: - mutex_unlock(&csi2rx->lock); return ret; } =20 @@ -546,12 +645,56 @@ static int csi2rx_enum_mbus_code(struct v4l2_subdev *= subdev, return 0; } =20 +static int _csi2rx_set_routing(struct v4l2_subdev *subdev, + struct v4l2_subdev_state *state, + struct v4l2_subdev_krouting *routing) +{ + static const struct v4l2_mbus_framefmt format =3D { + .width =3D 640, + .height =3D 480, + .code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_SRGB, + .ycbcr_enc =3D V4L2_YCBCR_ENC_601, + .quantization =3D V4L2_QUANTIZATION_LIM_RANGE, + .xfer_func =3D V4L2_XFER_FUNC_SRGB, + }; + int ret; + + if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX) + return -EINVAL; + + ret =3D v4l2_subdev_routing_validate(subdev, routing, + V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); + if (ret) + return ret; + + return v4l2_subdev_set_routing_with_fmt(subdev, state, routing, &format); +} + +static int csi2rx_set_routing(struct v4l2_subdev *subdev, + struct v4l2_subdev_state *state, + enum v4l2_subdev_format_whence which, + struct v4l2_subdev_krouting *routing) +{ + struct csi2rx_priv *csi2rx =3D v4l2_subdev_to_csi2rx(subdev); + int ret; + + if (which =3D=3D V4L2_SUBDEV_FORMAT_ACTIVE && csi2rx->count) + return -EBUSY; + + ret =3D _csi2rx_set_routing(subdev, state, routing); + if (ret) + return ret; + + return 0; +} + static int csi2rx_set_fmt(struct v4l2_subdev *subdev, struct v4l2_subdev_state *state, struct v4l2_subdev_format *format) { struct v4l2_mbus_framefmt *fmt; - unsigned int i; =20 /* No transcoding, source and sink formats must match. */ if (format->pad !=3D CSI2RX_PAD_SINK) @@ -563,14 +706,16 @@ static int csi2rx_set_fmt(struct v4l2_subdev *subdev, format->format.field =3D V4L2_FIELD_NONE; =20 /* Set sink format */ - fmt =3D v4l2_subdev_state_get_format(state, format->pad); + fmt =3D v4l2_subdev_state_get_format(state, format->pad, format->stream); *fmt =3D format->format; =20 - /* Propagate to source formats */ - for (i =3D CSI2RX_PAD_SOURCE_STREAM0; i < CSI2RX_PAD_MAX; i++) { - fmt =3D v4l2_subdev_state_get_format(state, i); - *fmt =3D format->format; - } + /* Propagate to source format */ + fmt =3D v4l2_subdev_state_get_opposite_stream_format(state, format->pad, + format->stream); + if (!fmt) + return -EINVAL; + + *fmt =3D format->format; =20 return 0; } @@ -578,21 +723,22 @@ static int csi2rx_set_fmt(struct v4l2_subdev *subdev, static int csi2rx_init_state(struct v4l2_subdev *subdev, struct v4l2_subdev_state *state) { - struct v4l2_subdev_format format =3D { - .pad =3D CSI2RX_PAD_SINK, - .format =3D { - .width =3D 640, - .height =3D 480, - .code =3D MEDIA_BUS_FMT_UYVY8_1X16, - .field =3D V4L2_FIELD_NONE, - .colorspace =3D V4L2_COLORSPACE_SRGB, - .ycbcr_enc =3D V4L2_YCBCR_ENC_601, - .quantization =3D V4L2_QUANTIZATION_LIM_RANGE, - .xfer_func =3D V4L2_XFER_FUNC_SRGB, + struct v4l2_subdev_route routes[] =3D { + { + .sink_pad =3D CSI2RX_PAD_SINK, + .sink_stream =3D 0, + .source_pad =3D CSI2RX_PAD_SOURCE_STREAM0, + .source_stream =3D 0, + .flags =3D V4L2_SUBDEV_ROUTE_FL_ACTIVE, }, }; =20 - return csi2rx_set_fmt(subdev, state, &format); + struct v4l2_subdev_krouting routing =3D { + .num_routes =3D ARRAY_SIZE(routes), + .routes =3D routes, + }; + + return _csi2rx_set_routing(subdev, state, &routing); } =20 int cdns_csi2rx_negotiate_ppc(struct v4l2_subdev *subdev, unsigned int pad, @@ -626,19 +772,70 @@ static int csi2rx_get_frame_desc(struct v4l2_subdev *= subdev, unsigned int pad, struct v4l2_mbus_frame_desc *fd) { struct csi2rx_priv *csi2rx =3D v4l2_subdev_to_csi2rx(subdev); + struct v4l2_mbus_frame_desc source_fd =3D {0}; + struct v4l2_subdev_route *route; + struct v4l2_subdev_state *state; + int ret; =20 - return csi2rx_get_frame_desc_from_source(csi2rx, fd); + ret =3D csi2rx_get_frame_desc_from_source(csi2rx, &source_fd); + if (ret) + return ret; + + fd->type =3D V4L2_MBUS_FRAME_DESC_TYPE_CSI2; + + state =3D v4l2_subdev_lock_and_get_active_state(subdev); + + for_each_active_route(&state->routing, route) { + struct v4l2_mbus_frame_desc_entry *source_entry =3D NULL; + unsigned int i; + + if (route->source_pad !=3D pad) + continue; + + for (i =3D 0; i < source_fd.num_entries; i++) { + if (source_fd.entry[i].stream =3D=3D route->sink_stream) { + source_entry =3D &source_fd.entry[i]; + break; + } + } + + if (!source_entry) { + dev_err(csi2rx->dev, + "Failed to find stream from source frame desc\n"); + ret =3D -EPIPE; + goto err_missing_stream; + } + + fd->entry[fd->num_entries].stream =3D route->source_stream; + fd->entry[fd->num_entries].flags =3D source_entry->flags; + fd->entry[fd->num_entries].length =3D source_entry->length; + fd->entry[fd->num_entries].pixelcode =3D source_entry->pixelcode; + fd->entry[fd->num_entries].bus.csi2.vc =3D + source_entry->bus.csi2.vc; + fd->entry[fd->num_entries].bus.csi2.dt =3D + source_entry->bus.csi2.dt; + + fd->num_entries++; + } + +err_missing_stream: + v4l2_subdev_unlock_state(state); + + return ret; } =20 static const struct v4l2_subdev_pad_ops csi2rx_pad_ops =3D { - .enum_mbus_code =3D csi2rx_enum_mbus_code, - .get_fmt =3D v4l2_subdev_get_fmt, - .set_fmt =3D csi2rx_set_fmt, - .get_frame_desc =3D csi2rx_get_frame_desc, + .enum_mbus_code =3D csi2rx_enum_mbus_code, + .get_fmt =3D v4l2_subdev_get_fmt, + .set_fmt =3D csi2rx_set_fmt, + .get_frame_desc =3D csi2rx_get_frame_desc, + .set_routing =3D csi2rx_set_routing, + .enable_streams =3D csi2rx_enable_streams, + .disable_streams =3D csi2rx_disable_streams, }; =20 static const struct v4l2_subdev_video_ops csi2rx_video_ops =3D { - .s_stream =3D csi2rx_s_stream, + .s_stream =3D csi2rx_s_stream_fallback, }; =20 static const struct v4l2_subdev_core_ops csi2rx_core_ops =3D { @@ -876,7 +1073,8 @@ static int csi2rx_probe(struct platform_device *pdev) csi2rx->pads[CSI2RX_PAD_SINK].flags =3D MEDIA_PAD_FL_SINK; for (i =3D CSI2RX_PAD_SOURCE_STREAM0; i < CSI2RX_PAD_MAX; i++) csi2rx->pads[i].flags =3D MEDIA_PAD_FL_SOURCE; - csi2rx->subdev.flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE; + csi2rx->subdev.flags =3D V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_STREAMS; csi2rx->subdev.entity.ops =3D &csi2rx_media_ops; =20 ret =3D media_entity_pads_init(&csi2rx->subdev.entity, CSI2RX_PAD_MAX, --=20 2.34.1 From nobody Fri Oct 3 20:26:50 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A7A93019A3; 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Mon, 25 Aug 2025 09:26:37 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 25 Aug 2025 09:26:37 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 25 Aug 2025 09:26:37 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN403747540; Mon, 25 Aug 2025 09:26:31 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 11/14] media: ti: j721e-csi2rx: add multistream support Date: Mon, 25 Aug 2025 19:55:19 +0530 Message-ID: <20250825142522.1826188-12-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra Each CSI2 stream can be multiplexed into 4 independent streams, each identified by its virtual channel number. To capture this multiplexed stream, the application needs to tell the driver how it wants to route the data. It needs to specify which context should process which stream. This is done via the new routing APIs. Add ioctls to accept routing information from the application and save that in the driver. This can be used when starting streaming on a context to determine which route and consequently which virtual channel it should process. Support the new enable_stream()/disable_stream() APIs in the subdev instead of s_stream() hook. De-assert the pixel interface reset on first start_streaming() and assert it on the last stop_streaming(). Reviewed-by: Yemike Abhilash Chandra Co-developed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav Signed-off-by: Jai Luthra Co-developed-by: Rishikesh Donadkar Signed-off-by: Rishikesh Donadkar --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 194 ++++++++++++------ 1 file changed, 136 insertions(+), 58 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 45e9001fa35b..0d3b10a0e3fa 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -146,17 +146,6 @@ static inline struct ti_csi2rx_dev *to_csi2rx_dev(stru= ct v4l2_subdev *sd) return container_of(sd, struct ti_csi2rx_dev, subdev); } =20 -static const struct v4l2_mbus_framefmt ti_csi2rx_default_fmt =3D { - .width =3D 640, - .height =3D 480, - .code =3D MEDIA_BUS_FMT_UYVY8_1X16, - .field =3D V4L2_FIELD_NONE, - .colorspace =3D V4L2_COLORSPACE_SRGB, - .ycbcr_enc =3D V4L2_YCBCR_ENC_601, - .quantization =3D V4L2_QUANTIZATION_LIM_RANGE, - .xfer_func =3D V4L2_XFER_FUNC_SRGB, -}; - static const struct ti_csi2rx_fmt ti_csi2rx_formats[] =3D { { .fourcc =3D V4L2_PIX_FMT_YUYV, @@ -572,8 +561,10 @@ static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx = *ctx) fmt =3D find_format_by_fourcc(ctx->v_fmt.fmt.pix.pixelformat); =20 /* De-assert the pixel interface reset. */ - reg =3D SHIM_CNTL_PIX_RST; - writel(reg, csi->shim + SHIM_CNTL); + if (!csi->enable_count) { + reg =3D SHIM_CNTL_PIX_RST; + writel(reg, csi->shim + SHIM_CNTL); + } =20 /* Negotiate pixel count from the source */ ti_csi2rx_request_max_ppc(csi); @@ -1027,7 +1018,10 @@ static int ti_csi2rx_start_streaming(struct vb2_queu= e *vq, unsigned int count) dma->state =3D TI_CSI2RX_DMA_ACTIVE; spin_unlock_irqrestore(&dma->lock, flags); =20 - ret =3D v4l2_subdev_call(&csi->subdev, video, s_stream, 1); + /* Start stream 0, we don't allow multiple streams on the source pad */ + ret =3D v4l2_subdev_enable_streams(&csi->subdev, + TI_CSI2RX_PAD_FIRST_SOURCE + ctx->idx, + BIT(0)); if (ret) goto err_dma; =20 @@ -1050,19 +1044,26 @@ static void ti_csi2rx_stop_streaming(struct vb2_que= ue *vq) struct ti_csi2rx_dev *csi =3D ctx->csi; int ret; =20 - video_device_pipeline_stop(&ctx->vdev); + mutex_lock(&csi->mutex); =20 - writel(0, csi->shim + SHIM_CNTL); writel(0, csi->shim + SHIM_DMACNTX(ctx->idx)); =20 - mutex_lock(&csi->mutex); - csi->vc_cached =3D false; - mutex_unlock(&csi->mutex); + /* assert pixel reset to prevent stale data */ + if (csi->enable_count =3D=3D 1) { + writel(0, csi->shim + SHIM_CNTL); + csi->vc_cached =3D false; + } =20 - ret =3D v4l2_subdev_call(&csi->subdev, video, s_stream, 0); + video_device_pipeline_stop(&ctx->vdev); + + ret =3D v4l2_subdev_disable_streams(&csi->subdev, + TI_CSI2RX_PAD_FIRST_SOURCE + ctx->idx, + BIT(0)); if (ret) dev_err(csi->dev, "Failed to stop subdev stream\n"); =20 + mutex_unlock(&csi->mutex); + ti_csi2rx_stop_dma(ctx); ti_csi2rx_cleanup_buffers(ctx, VB2_BUF_STATE_ERROR); } @@ -1105,74 +1106,151 @@ static int ti_csi2rx_sd_set_fmt(struct v4l2_subdev= *sd, fmt =3D v4l2_subdev_state_get_format(state, format->pad, format->stream); *fmt =3D format->format; =20 - fmt =3D v4l2_subdev_state_get_format(state, TI_CSI2RX_PAD_FIRST_SOURCE, - format->stream); + fmt =3D v4l2_subdev_state_get_opposite_stream_format(state, format->pad, + format->stream); + if (!fmt) + return -EINVAL; + *fmt =3D format->format; =20 return 0; } =20 -static int ti_csi2rx_sd_init_state(struct v4l2_subdev *sd, - struct v4l2_subdev_state *state) +static int _ti_csi2rx_sd_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_krouting *routing) { - struct v4l2_mbus_framefmt *fmt; + int ret; =20 - fmt =3D v4l2_subdev_state_get_format(state, TI_CSI2RX_PAD_SINK); - *fmt =3D ti_csi2rx_default_fmt; + const struct v4l2_mbus_framefmt format =3D { + .width =3D 640, + .height =3D 480, + .code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_SRGB, + .ycbcr_enc =3D V4L2_YCBCR_ENC_601, + .quantization =3D V4L2_QUANTIZATION_LIM_RANGE, + .xfer_func =3D V4L2_XFER_FUNC_SRGB, + }; =20 - fmt =3D v4l2_subdev_state_get_format(state, TI_CSI2RX_PAD_FIRST_SOURCE); - *fmt =3D ti_csi2rx_default_fmt; + ret =3D v4l2_subdev_routing_validate(sd, routing, + V4L2_SUBDEV_ROUTING_ONLY_1_TO_1 | + V4L2_SUBDEV_ROUTING_NO_SOURCE_MULTIPLEXING); =20 - return 0; + if (ret) + return ret; + + /* Only stream ID 0 allowed on source pads */ + for (unsigned int i =3D 0; i < routing->num_routes; ++i) { + const struct v4l2_subdev_route *route =3D &routing->routes[i]; + + if (route->source_stream !=3D 0) + return -EINVAL; + } + + ret =3D v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format); + + return ret; +} + +static int ti_csi2rx_sd_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + enum v4l2_subdev_format_whence which, + struct v4l2_subdev_krouting *routing) +{ + struct ti_csi2rx_dev *csi =3D to_csi2rx_dev(sd); + + if (csi->enable_count > 0) + return -EBUSY; + + return _ti_csi2rx_sd_set_routing(sd, state, routing); +} + +static int ti_csi2rx_sd_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct v4l2_subdev_route routes[] =3D { { + .sink_pad =3D 0, + .sink_stream =3D 0, + .source_pad =3D TI_CSI2RX_PAD_FIRST_SOURCE, + .source_stream =3D 0, + .flags =3D V4L2_SUBDEV_ROUTE_FL_ACTIVE, + } }; + + struct v4l2_subdev_krouting routing =3D { + .num_routes =3D 1, + .routes =3D routes, + }; + + /* Initialize routing to single route to the fist source pad */ + return _ti_csi2rx_sd_set_routing(sd, state, &routing); } =20 -static int ti_csi2rx_sd_s_stream(struct v4l2_subdev *sd, int enable) +static int ti_csi2rx_sd_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + u32 pad, u64 streams_mask) { struct ti_csi2rx_dev *csi =3D to_csi2rx_dev(sd); + struct media_pad *remote_pad; + u64 sink_streams; int ret =3D 0; =20 + remote_pad =3D media_entity_remote_source_pad_unique(&csi->subdev.entity); + if (!remote_pad) + return -ENODEV; + sink_streams =3D v4l2_subdev_state_xlate_streams(state, pad, + TI_CSI2RX_PAD_SINK, + &streams_mask); + + ret =3D v4l2_subdev_enable_streams(csi->source, remote_pad->index, + sink_streams); + if (ret) + return ret; + mutex_lock(&csi->mutex); + csi->enable_count++; + mutex_unlock(&csi->mutex); =20 - if (enable) { - if (csi->enable_count > 0) { - csi->enable_count++; - goto out; - } + return 0; +} =20 - ret =3D v4l2_subdev_call(csi->source, video, s_stream, 1); - if (ret) - goto out; +static int ti_csi2rx_sd_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + u32 pad, u64 streams_mask) +{ + struct ti_csi2rx_dev *csi =3D to_csi2rx_dev(sd); + struct media_pad *remote_pad; + u64 sink_streams; + int ret =3D 0; =20 - csi->enable_count++; - } else { - if (csi->enable_count =3D=3D 0) { - ret =3D -EINVAL; - goto out; - } + remote_pad =3D media_entity_remote_source_pad_unique(&csi->subdev.entity); + if (!remote_pad) + return -ENODEV; + sink_streams =3D v4l2_subdev_state_xlate_streams(state, pad, + TI_CSI2RX_PAD_SINK, + &streams_mask); =20 - if (--csi->enable_count > 0) - goto out; + if (csi->enable_count =3D=3D 0) + return -EINVAL; =20 - ret =3D v4l2_subdev_call(csi->source, video, s_stream, 0); - } + ret =3D v4l2_subdev_disable_streams(csi->source, remote_pad->index, + sink_streams); + if (!ret) + --csi->enable_count; =20 -out: - mutex_unlock(&csi->mutex); - return ret; + return 0; } =20 static const struct v4l2_subdev_pad_ops ti_csi2rx_subdev_pad_ops =3D { .enum_mbus_code =3D ti_csi2rx_enum_mbus_code, + .set_routing =3D ti_csi2rx_sd_set_routing, .get_fmt =3D v4l2_subdev_get_fmt, .set_fmt =3D ti_csi2rx_sd_set_fmt, -}; - -static const struct v4l2_subdev_video_ops ti_csi2rx_subdev_video_ops =3D { - .s_stream =3D ti_csi2rx_sd_s_stream, + .enable_streams =3D ti_csi2rx_sd_enable_streams, + .disable_streams =3D ti_csi2rx_sd_disable_streams, }; =20 static const struct v4l2_subdev_ops ti_csi2rx_subdev_ops =3D { - .video =3D &ti_csi2rx_subdev_video_ops, .pad =3D &ti_csi2rx_subdev_pad_ops, }; =20 @@ -1349,7 +1427,7 @@ static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev *= csi) v4l2_subdev_init(sd, &ti_csi2rx_subdev_ops); sd->internal_ops =3D &ti_csi2rx_internal_ops; sd->entity.function =3D MEDIA_ENT_F_VID_IF_BRIDGE; - sd->flags =3D V4L2_SUBDEV_FL_HAS_DEVNODE; + sd->flags =3D V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS; strscpy(sd->name, dev_name(csi->dev), sizeof(sd->name)); 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Mon, 25 Aug 2025 09:26:37 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 12/14] media: ti: j721e-csi2rx: Submit all available buffers Date: Mon, 25 Aug 2025 19:55:20 +0530 Message-ID: <20250825142522.1826188-13-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra We already make sure to submit all available buffers to DMA in each DMA completion callback. Move that logic in a separate function, and use it during stream start as well, as most application queue all their buffers before stream on. Signed-off-by: Jai Luthra Reviewed-by: Tomi Valkeinen Reviewed-by: Yemike Abhilash Chandra Co-developed-by: Rishikesh Donadkar Signed-off-by: Rishikesh Donadkar --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 44 +++++++++++-------- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 0d3b10a0e3fa..ba8f476fe779 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -676,6 +676,28 @@ static int ti_csi2rx_drain_dma(struct ti_csi2rx_ctx *c= tx) return ret; } =20 +static int ti_csi2rx_dma_submit_pending(struct ti_csi2rx_ctx *ctx) +{ + struct ti_csi2rx_dma *dma =3D &ctx->dma; + struct ti_csi2rx_buffer *buf; + int ret =3D 0; + + /* If there are more buffers to process then start their transfer. */ + while (!list_empty(&dma->queue)) { + buf =3D list_entry(dma->queue.next, struct ti_csi2rx_buffer, list); + ret =3D ti_csi2rx_start_dma(ctx, buf); + if (ret) { + dev_err(ctx->csi->dev, + "Failed to queue the next buffer for DMA\n"); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + list_del(&buf->list); + } else { + list_move_tail(&buf->list, &dma->submitted); + } + } + return ret; +} + static void ti_csi2rx_dma_callback(void *param) { struct ti_csi2rx_buffer *buf =3D param; @@ -696,18 +718,7 @@ static void ti_csi2rx_dma_callback(void *param) vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); list_del(&buf->list); =20 - /* If there are more buffers to process then start their transfer. */ - while (!list_empty(&dma->queue)) { - buf =3D list_entry(dma->queue.next, struct ti_csi2rx_buffer, list); - - if (ti_csi2rx_start_dma(csi, buf)) { - dev_err(csi->dev, "Failed to queue the next buffer for DMA\n"); - list_del(&buf->list); - vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - } else { - list_move_tail(&buf->list, &dma->submitted); - } - } + ti_csi2rx_dma_submit_pending(ctx); =20 if (list_empty(&dma->submitted)) dma->state =3D TI_CSI2RX_DMA_IDLE; @@ -966,7 +977,6 @@ static int ti_csi2rx_start_streaming(struct vb2_queue *= vq, unsigned int count) struct ti_csi2rx_ctx *ctx =3D vb2_get_drv_priv(vq); struct ti_csi2rx_dev *csi =3D ctx->csi; struct ti_csi2rx_dma *dma =3D &ctx->dma; - struct ti_csi2rx_buffer *buf; unsigned long flags; int ret =3D 0; =20 @@ -1005,16 +1015,13 @@ static int ti_csi2rx_start_streaming(struct vb2_que= ue *vq, unsigned int count) ctx->sequence =3D 0; =20 spin_lock_irqsave(&dma->lock, flags); - buf =3D list_entry(dma->queue.next, struct ti_csi2rx_buffer, list); =20 - ret =3D ti_csi2rx_start_dma(ctx, buf); + ret =3D ti_csi2rx_dma_submit_pending(ctx); if (ret) { - dev_err(csi->dev, "Failed to start DMA: %d\n", ret); spin_unlock_irqrestore(&dma->lock, flags); - goto err_pipeline; + goto err_dma; } =20 - list_move_tail(&buf->list, &dma->submitted); dma->state =3D TI_CSI2RX_DMA_ACTIVE; spin_unlock_irqrestore(&dma->lock, flags); =20 @@ -1029,7 +1036,6 @@ static int ti_csi2rx_start_streaming(struct vb2_queue= *vq, unsigned int count) =20 err_dma: ti_csi2rx_stop_dma(ctx); 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Mon, 25 Aug 2025 09:26:43 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 13/14] media: ti: j721e-csi2rx: Change the drain architecture for multistream Date: Mon, 25 Aug 2025 19:55:21 +0530 Message-ID: <20250825142522.1826188-14-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" On buffer starvation the DMA is marked IDLE, and the stale data in the internal FIFOs gets drained only on the next VIDIOC_QBUF call from the userspace. This approach works fine for a single stream case. But in multistream scenarios, buffer starvation for one stream i.e. one virtual channel, can block the shared HW FIFO of the CSI2RX IP. This can stall the pipeline for all other virtual channels, even if buffers are available for them. This patch introduces a new architecture, that continuously drains data from the shared HW FIFO into a small (32KiB) buffer if no buffers are made available to the driver from the userspace. This ensures independence between different streams, where a slower downstream element for one camera does not block streaming for other cameras. Additionally, after a drain is done for a VC, the next frame will be a partial frame, as a portion of its data will have already been drained before a valid buffer is queued by user space to the driver. Reviewed-by: Jai Luthra Reviewed-by: Yemike Abhilash Chandra Signed-off-by: Rishikesh Donadkar --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 99 +++++++------------ 1 file changed, 36 insertions(+), 63 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index ba8f476fe779..4ac6a76b9409 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -61,7 +61,6 @@ #define TI_CSI2RX_MAX_SOURCE_PADS TI_CSI2RX_MAX_CTX #define TI_CSI2RX_MAX_PADS (1 + TI_CSI2RX_MAX_SOURCE_PADS) =20 -#define DRAIN_TIMEOUT_MS 50 #define DRAIN_BUFFER_SIZE SZ_32K =20 #define CSI2RX_BRIDGE_SOURCE_PAD 1 @@ -83,7 +82,6 @@ struct ti_csi2rx_buffer { =20 enum ti_csi2rx_dma_state { TI_CSI2RX_DMA_STOPPED, /* Streaming not started yet. */ - TI_CSI2RX_DMA_IDLE, /* Streaming but no pending DMA operation. */ TI_CSI2RX_DMA_ACTIVE, /* Streaming and pending DMA operation. */ }; =20 @@ -252,6 +250,10 @@ static const struct ti_csi2rx_fmt ti_csi2rx_formats[] = =3D { static int ti_csi2rx_start_dma(struct ti_csi2rx_ctx *ctx, struct ti_csi2rx_buffer *buf); =20 +/* Forward declarations needed by ti_csi2rx_drain_callback. */ +static int ti_csi2rx_drain_dma(struct ti_csi2rx_ctx *ctx); +static int ti_csi2rx_dma_submit_pending(struct ti_csi2rx_ctx *ctx); + static const struct ti_csi2rx_fmt *find_format_by_fourcc(u32 pixelformat) { unsigned int i; @@ -621,9 +623,31 @@ static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx = *ctx) =20 static void ti_csi2rx_drain_callback(void *param) { - struct completion *drain_complete =3D param; + struct ti_csi2rx_ctx *ctx =3D param; + struct ti_csi2rx_dma *dma =3D &ctx->dma; + unsigned long flags; =20 - complete(drain_complete); + spin_lock_irqsave(&dma->lock, flags); + + if (dma->state =3D=3D TI_CSI2RX_DMA_STOPPED) { + spin_unlock_irqrestore(&dma->lock, flags); + return; + } + + /* + * If dma->queue is empty, it indicates that no buffer has been + * provided by user space. In this case, initiate a transactions + * to drain the DMA. Since one drain of size DRAIN_BUFFER_SIZE + * will be done here, the subsequent frame will be a + * partial frame, with a size of frame_size - DRAIN_BUFFER_SIZE + */ + if (list_empty(&dma->queue)) { + if (ti_csi2rx_drain_dma(ctx)) + dev_warn(ctx->csi->dev, "DMA drain failed\n"); + } else { + ti_csi2rx_dma_submit_pending(ctx); + } + spin_unlock_irqrestore(&dma->lock, flags); } =20 /* @@ -641,12 +665,9 @@ static int ti_csi2rx_drain_dma(struct ti_csi2rx_ctx *c= tx) { struct ti_csi2rx_dev *csi =3D ctx->csi; struct dma_async_tx_descriptor *desc; - struct completion drain_complete; dma_cookie_t cookie; int ret; =20 - init_completion(&drain_complete); - desc =3D dmaengine_prep_slave_single(ctx->dma.chan, csi->drain.paddr, csi->drain.len, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); @@ -656,7 +677,7 @@ static int ti_csi2rx_drain_dma(struct ti_csi2rx_ctx *ct= x) } =20 desc->callback =3D ti_csi2rx_drain_callback; - desc->callback_param =3D &drain_complete; + desc->callback_param =3D ctx; =20 cookie =3D dmaengine_submit(desc); ret =3D dma_submit_error(cookie); @@ -665,13 +686,6 @@ static int ti_csi2rx_drain_dma(struct ti_csi2rx_ctx *c= tx) =20 dma_async_issue_pending(ctx->dma.chan); =20 - if (!wait_for_completion_timeout(&drain_complete, - msecs_to_jiffies(DRAIN_TIMEOUT_MS))) { - dmaengine_terminate_sync(ctx->dma.chan); - dev_dbg(csi->dev, "DMA transfer timed out for drain buffer\n"); - ret =3D -ETIMEDOUT; - goto out; - } out: return ret; } @@ -720,9 +734,11 @@ static void ti_csi2rx_dma_callback(void *param) =20 ti_csi2rx_dma_submit_pending(ctx); =20 - if (list_empty(&dma->submitted)) - dma->state =3D TI_CSI2RX_DMA_IDLE; - + if (list_empty(&dma->submitted)) { + if (ti_csi2rx_drain_dma(ctx)) + dev_warn(ctx->csi->dev, + "DMA drain failed on one of the transactions\n"); + } spin_unlock_irqrestore(&dma->lock, flags); } =20 @@ -775,7 +791,7 @@ static void ti_csi2rx_stop_dma(struct ti_csi2rx_ctx *ct= x) * enforced before terminating DMA. */ ret =3D ti_csi2rx_drain_dma(ctx); - if (ret && ret !=3D -ETIMEDOUT) + if (ret) dev_warn(ctx->csi->dev, "Failed to drain DMA. Next frame might be bogus\n"); } @@ -842,57 +858,14 @@ static void ti_csi2rx_buffer_queue(struct vb2_buffer = *vb) struct ti_csi2rx_ctx *ctx =3D vb2_get_drv_priv(vb->vb2_queue); struct ti_csi2rx_buffer *buf; struct ti_csi2rx_dma *dma =3D &ctx->dma; - bool restart_dma =3D false; unsigned long flags =3D 0; - int ret; =20 buf =3D container_of(vb, struct ti_csi2rx_buffer, vb.vb2_buf); buf->ctx =3D ctx; =20 spin_lock_irqsave(&dma->lock, flags); - /* - * Usually the DMA callback takes care of queueing the pending buffers. - * But if DMA has stalled due to lack of buffers, restart it now. - */ - if (dma->state =3D=3D TI_CSI2RX_DMA_IDLE) { - /* - * Do not restart DMA with the lock held because - * ti_csi2rx_drain_dma() might block for completion. - * There won't be a race on queueing DMA anyway since the - * callback is not being fired. - */ - restart_dma =3D true; - dma->state =3D TI_CSI2RX_DMA_ACTIVE; - } else { - list_add_tail(&buf->list, &dma->queue); - } + list_add_tail(&buf->list, &dma->queue); spin_unlock_irqrestore(&dma->lock, flags); - - if (restart_dma) { - /* - * Once frames start dropping, some data gets stuck in the DMA - * pipeline somewhere. So the first DMA transfer after frame - * drops gives a partial frame. This is obviously not useful to - * the application and will only confuse it. Issue a DMA - * transaction to drain that up. - */ - ret =3D ti_csi2rx_drain_dma(ctx); - if (ret && ret !=3D -ETIMEDOUT) - dev_warn(ctx->csi->dev, - "Failed to drain DMA. Next frame might be bogus\n"); - - spin_lock_irqsave(&dma->lock, flags); - ret =3D ti_csi2rx_start_dma(ctx, buf); - if (ret) { - vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - dma->state =3D TI_CSI2RX_DMA_IDLE; - spin_unlock_irqrestore(&dma->lock, flags); - dev_err(ctx->csi->dev, "Failed to start DMA: %d\n", ret); - } else { - list_add_tail(&buf->list, &dma->submitted); - spin_unlock_irqrestore(&dma->lock, flags); - } - } } =20 static int ti_csi2rx_get_route(struct ti_csi2rx_ctx *ctx) --=20 2.34.1 From nobody Fri Oct 3 20:26:50 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D8122FC88C; Mon, 25 Aug 2025 14:27:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132035; cv=none; b=Ym8vYgoQDgS5uwvx4Bk0MH7Lsfk1ClWoemjwPJchHOE6vMzJIgJKB0qcoUBzlpaYL66C3I8c7yBpNFQEQC5Kqd0f0dJ0Nu7qo/ply6jbwQIWm2CVeERo2QLSgewkazmMD1AHcltJ1jUCgLuSHbsn4aHbq9fgqn9Y/+/YVVis+u0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132035; c=relaxed/simple; bh=wnEwoAwOmaC9EtbLu07y6gkfUzdalMCzS41u8HyyAeQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HN+pK6JL+NU9wFnSGHmLelHS1eQ8Lt0+0Cf2R/sMIIBD5yWcOCPVLC1wFoDekzc1P29/6wFQSffa2zXmq8IrNsMQhof0IyC6GqeFn9/QT55s5Q2RYcN/buiL3dKhgA0fJMa9UvCdMumWs08MzKSeB2p367hBSl39wPAPSbHknSY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=uZVejJZA; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="uZVejJZA" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57PEQuuY1294958; Mon, 25 Aug 2025 09:26:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756132016; bh=h1zyU1evSKaxO4aYTSyZWEjNsFhfpDLHeNtlMXX9zq4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uZVejJZAuewUM17JPFF3XXEXpfhxX/ahO7M27zMyf9xVLZ8py8ftE3iMQnC+qN89F 66gxbjZe1aYjpSTNw/YzCXfC50n8D+r4RDFlCPXdlWOgTvK/cAV69vea6pV1zwf5AS 6jnwuV0z8wBDotk+Tkf2j93ByeJpZ2KxmC4IbPis= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57PEQu8n1236002 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 25 Aug 2025 09:26:56 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 25 Aug 2025 09:26:55 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 25 Aug 2025 09:26:55 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57PEPN433747540; Mon, 25 Aug 2025 09:26:50 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 14/14] media: ti: j721e-csi2rx: Wait for the last drain completion Date: Mon, 25 Aug 2025 19:55:22 +0530 Message-ID: <20250825142522.1826188-15-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250825142522.1826188-1-r-donadkar@ti.com> References: <20250825142522.1826188-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" dmaengine_terminate_sync() causes all activity for the DMA channel to be stopped, and may discard data in the DMA FIFO which hasn't been fully transferred. No callback functions will be called for any incomplete transfers[1]. In multistream use case, calling dmaengine_terminate_sync() immediately after issuing the last drain transaction will result in no callback for the last drain cycle. Implement complete callback for the last drain cycle to make sure that the last drain has completed properly, this will ensure that stale data is not left out in the HW FIFO. [1] : https://docs.kernel.org/driver-api/dmaengine/client.html Signed-off-by: Rishikesh Donadkar Reviewed-by: Yemike Abhilash Chandra --- drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 4ac6a76b9409..520ee05eb5b4 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -62,6 +62,7 @@ #define TI_CSI2RX_MAX_PADS (1 + TI_CSI2RX_MAX_SOURCE_PADS) =20 #define DRAIN_BUFFER_SIZE SZ_32K +#define DRAIN_TIMEOUT_MS 50 =20 #define CSI2RX_BRIDGE_SOURCE_PAD 1 =20 @@ -137,6 +138,7 @@ struct ti_csi2rx_dev { size_t len; } drain; bool vc_cached; + struct completion drain_complete; }; =20 static inline struct ti_csi2rx_dev *to_csi2rx_dev(struct v4l2_subdev *sd) @@ -624,12 +626,14 @@ static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx= *ctx) static void ti_csi2rx_drain_callback(void *param) { struct ti_csi2rx_ctx *ctx =3D param; + struct ti_csi2rx_dev *csi =3D ctx->csi; struct ti_csi2rx_dma *dma =3D &ctx->dma; unsigned long flags; =20 spin_lock_irqsave(&dma->lock, flags); =20 if (dma->state =3D=3D TI_CSI2RX_DMA_STOPPED) { + complete(&csi->drain_complete); spin_unlock_irqrestore(&dma->lock, flags); return; } @@ -774,6 +778,7 @@ static int ti_csi2rx_start_dma(struct ti_csi2rx_ctx *ct= x, static void ti_csi2rx_stop_dma(struct ti_csi2rx_ctx *ctx) { struct ti_csi2rx_dma *dma =3D &ctx->dma; + struct ti_csi2rx_dev *csi =3D ctx->csi; enum ti_csi2rx_dma_state state; unsigned long flags; int ret; @@ -783,6 +788,8 @@ static void ti_csi2rx_stop_dma(struct ti_csi2rx_ctx *ct= x) dma->state =3D TI_CSI2RX_DMA_STOPPED; spin_unlock_irqrestore(&dma->lock, flags); =20 + init_completion(&csi->drain_complete); + if (state !=3D TI_CSI2RX_DMA_STOPPED) { /* * Normal DMA termination does not clean up pending data on @@ -796,6 +803,10 @@ static void ti_csi2rx_stop_dma(struct ti_csi2rx_ctx *c= tx) "Failed to drain DMA. Next frame might be bogus\n"); } =20 + if (!wait_for_completion_timeout(&csi->drain_complete, + msecs_to_jiffies(DRAIN_TIMEOUT_MS))) + dev_dbg(csi->dev, "DMA transfer timed out for drain buffer\n"); + ret =3D dmaengine_terminate_sync(ctx->dma.chan); if (ret) dev_err(ctx->csi->dev, "Failed to stop DMA: %d\n", ret); --=20 2.34.1