From nobody Fri Oct 3 20:25:01 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DE191A83FB for ; Mon, 25 Aug 2025 13:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756128737; cv=none; b=cASVPrriLO+7W7ydEvp8y6ikgH9Ko87LKpRuHvozjy7JwauR1glBYN7yKFULhyryj881n1wuTwAcBJnu2VYdB38Oc99pno7MYaBMyMjQ+ntMLr665TUuejioZ4qwVL9yh34r2gWY9D3OiP0JV+26I11pYTCvVAdliFctt861mVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756128737; c=relaxed/simple; bh=v0lEeQ6YG0uRyAKZvd1MALN0/E2Te0j+nbh2M/5wLPk=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=oloJdrZOs5wh27FO5O3O6O9ZhYZhI1oWIlzTbhpKClsSl+ytLYw51PIbYKTIBBy7J+k+zU7n4kr9rRVfGK8kir7435DKiFO3268m0i5xzncrBNoN3Y4CLyBoy8s6TODdkrhx+bqp3k6fUPfgUfNQdyVrukdFZ93lhhdrAb3ysPk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=eZxm3CD9; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="eZxm3CD9" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57PDCIBW027573; Mon, 25 Aug 2025 15:31:50 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=selector1; bh=Eh5kA4z57YCWnp0H2BkHkl l7osoEmhb74s1I8zaGHUs=; b=eZxm3CD9MNInOp4ICb87YDtOpCMYWexIn8VCMT /ZygQI4qHnD3zrdegBsq1wANFc6nbRl5GQL3BBRm3PQTJj/hUMPfNLltj6438rLo K1kI2589taImdq0G5zeaaqdkRzSJdAvHn5OxkI0dM6H5aqJZ/hxbfBuQsk4Gk0q8 L2IgcddKVkRR7bhZWEzlsch/J+gseA0zBq9nYXd6r4qqM54uEiP4fgPMU77Tnoh0 Hrctmn7eLeEH7LiSk4zhw6Sdvbfb1AjdngUiZLjjWyVu3f5lSMjNbAiYzGSZ5Q37 iijNCJB3dwnDMrXNqn1PdPftnEcQTNDzFEDOAt3qxNTTdoqg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48q5xbektb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Aug 2025 15:31:49 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9B65240044; Mon, 25 Aug 2025 15:30:35 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7F1636C9827; Mon, 25 Aug 2025 15:30:02 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 25 Aug 2025 15:30:02 +0200 From: Raphael Gallais-Pou To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Maxime Coquelin , Alexandre Torgue CC: , , , Subject: [PATCH v2] drm/stm: ltdc: unify log system Date: Mon, 25 Aug 2025 15:29:51 +0200 Message-ID: <20250825132951.547899-1-raphael.gallais-pou@foss.st.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-25_06,2025-08-20_03,2025-03-28_01 Content-Type: text/plain; charset="utf-8" DRM_ERROR and similar are deprecated. Use drm_dev based logging. Link: https://lore.kernel.org/r/20250821130356.883553-1-raphael.gallais-pou= @foss.st.com Signed-off-by: Raphael Gallais-Pou Acked-by: Philippe Cornu Acked-by: Yannick Fertre --- Changes in v2: - Fix kernel test robot's warnings https://lore.kernel.org/all/202508250637.nLxtkS26-lkp@intel.com/ - Rebased onto latest drm-misc-next - Remove Yannick's acked-by since the patch changed --- drivers/gpu/drm/stm/ltdc.c | 139 +++++++++++++++++++------------------ 1 file changed, 70 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index ba315c66a04d..b9477fbec1c1 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -641,7 +641,7 @@ static inline void ltdc_set_ycbcr_config(struct drm_pla= ne *plane, u32 drm_pix_fm break; default: /* RGB or not a YCbCr supported format */ - DRM_ERROR("Unsupported pixel format: %u\n", drm_pix_fmt); + drm_err(plane->dev, "Unsupported pixel format: %u\n", drm_pix_fmt); return; } =20 @@ -664,18 +664,19 @@ static inline void ltdc_set_ycbcr_coeffs(struct drm_p= lane *plane) u32 lofs =3D plane->index * LAY_OFS; =20 if (enc !=3D DRM_COLOR_YCBCR_BT601 && enc !=3D DRM_COLOR_YCBCR_BT709) { - DRM_ERROR("color encoding %d not supported, use bt601 by default\n", enc= ); + drm_err(plane->dev, "color encoding %d not supported, use bt601 by defau= lt\n", enc); /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */ enc =3D DRM_COLOR_YCBCR_BT601; } =20 if (ran !=3D DRM_COLOR_YCBCR_LIMITED_RANGE && ran !=3D DRM_COLOR_YCBCR_FU= LL_RANGE) { - DRM_ERROR("color range %d not supported, use limited range by default\n"= , ran); + drm_err(plane->dev, + "color range %d not supported, use limited range by default\n", ran); /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */ ran =3D DRM_COLOR_YCBCR_LIMITED_RANGE; } =20 - DRM_DEBUG_DRIVER("Color encoding=3D%d, range=3D%d\n", enc, ran); + drm_err(plane->dev, "Color encoding=3D%d, range=3D%d\n", enc, ran); regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs, ltdc_ycbcr2rgb_coeffs[enc][ran][0]); regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs, @@ -774,7 +775,7 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *cr= tc, struct ltdc_device *ldev =3D crtc_to_ltdc(crtc); struct drm_device *ddev =3D crtc->dev; =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(crtc->dev, "\n"); =20 pm_runtime_get_sync(ddev->dev); =20 @@ -798,7 +799,7 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *c= rtc, struct drm_device *ddev =3D crtc->dev; int layer_index =3D 0; =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(crtc->dev, "\n"); =20 drm_crtc_vblank_off(crtc); =20 @@ -837,7 +838,7 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc, =20 result =3D clk_round_rate(ldev->pixel_clk, target); =20 - DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); + drm_dbg_driver(crtc->dev, "clk rate target %d, available %d\n", target, r= esult); =20 /* Filter modes according to the max frequency supported by the pads */ if (result > ldev->caps.pad_max_freq_hz) @@ -872,14 +873,14 @@ static bool ltdc_crtc_mode_fixup(struct drm_crtc *crt= c, int rate =3D mode->clock * 1000; =20 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { - DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); + drm_err(crtc->dev, "Cannot set rate (%dHz) for pixel clk\n", rate); return false; } =20 adjusted_mode->clock =3D clk_get_rate(ldev->pixel_clk) / 1000; =20 - DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", - mode->clock, adjusted_mode->clock); + drm_dbg_driver(crtc->dev, "requested clock %dkHz, adjusted clock %dkHz\n", + mode->clock, adjusted_mode->clock); =20 return true; } @@ -934,20 +935,20 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *= crtc) if (!pm_runtime_active(ddev->dev)) { ret =3D pm_runtime_get_sync(ddev->dev); if (ret) { - DRM_ERROR("Failed to set mode, cannot get sync\n"); + drm_err(crtc->dev, "Failed to set mode, cannot get sync\n"); return; } } =20 - DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); - DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay); - DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", - mode->hsync_start - mode->hdisplay, - mode->htotal - mode->hsync_end, - mode->hsync_end - mode->hsync_start, - mode->vsync_start - mode->vdisplay, - mode->vtotal - mode->vsync_end, - mode->vsync_end - mode->vsync_start); + drm_dbg_driver(crtc->dev, "CRTC:%d mode:%s\n", crtc->base.id, mode->name); + drm_dbg_driver(crtc->dev, "Video mode: %dx%d", mode->hdisplay, mode->vdis= play); + drm_dbg_driver(crtc->dev, " hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", + mode->hsync_start - mode->hdisplay, + mode->htotal - mode->hsync_end, + mode->hsync_end - mode->hsync_start, + mode->vsync_start - mode->vdisplay, + mode->vtotal - mode->vsync_end, + mode->vsync_end - mode->vsync_start); =20 /* Convert video timings to ltdc timings */ hsync =3D mode->hsync_end - mode->hsync_start - 1; @@ -1033,7 +1034,7 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *c= rtc, struct drm_device *ddev =3D crtc->dev; struct drm_pending_vblank_event *event =3D crtc->state->event; =20 - DRM_DEBUG_ATOMIC("\n"); + drm_dbg_atomic(crtc->dev, "\n"); =20 ltdc_crtc_update_clut(crtc); =20 @@ -1121,7 +1122,7 @@ static int ltdc_crtc_enable_vblank(struct drm_crtc *c= rtc) struct ltdc_device *ldev =3D crtc_to_ltdc(crtc); struct drm_crtc_state *state =3D crtc->state; =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(crtc->dev, "\n"); =20 if (state->enable) regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE); @@ -1135,7 +1136,7 @@ static void ltdc_crtc_disable_vblank(struct drm_crtc = *crtc) { struct ltdc_device *ldev =3D crtc_to_ltdc(crtc); =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(crtc->dev, "\n"); regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE); } =20 @@ -1144,11 +1145,11 @@ static int ltdc_crtc_set_crc_source(struct drm_crtc= *crtc, const char *source) struct ltdc_device *ldev; int ret; =20 - DRM_DEBUG_DRIVER("\n"); - if (!crtc) return -ENODEV; =20 + drm_dbg_driver(crtc->dev, "\n"); + ldev =3D crtc_to_ltdc(crtc); =20 if (source && strcmp(source, "auto") =3D=3D 0) { @@ -1168,14 +1169,14 @@ static int ltdc_crtc_set_crc_source(struct drm_crtc= *crtc, const char *source) static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source, size_t *values_cnt) { - DRM_DEBUG_DRIVER("\n"); - if (!crtc) return -ENODEV; =20 + drm_dbg_driver(crtc->dev, "\n"); + if (source && strcmp(source, "auto") !=3D 0) { - DRM_DEBUG_DRIVER("Unknown CRC source %s for %s\n", - source, crtc->name); + drm_dbg_driver(crtc->dev, "Unknown CRC source %s for %s\n", + source, crtc->name); return -EINVAL; } =20 @@ -1233,7 +1234,7 @@ static int ltdc_plane_atomic_check(struct drm_plane *= plane, struct drm_framebuffer *fb =3D new_plane_state->fb; u32 src_w, src_h; =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(plane->dev, "\n"); =20 if (!fb) return 0; @@ -1244,7 +1245,7 @@ static int ltdc_plane_atomic_check(struct drm_plane *= plane, =20 /* Reject scaling */ if (src_w !=3D new_plane_state->crtc_w || src_h !=3D new_plane_state->crt= c_h) { - DRM_DEBUG_DRIVER("Scaling is not supported"); + drm_dbg_driver(plane->dev, "Scaling is not supported"); =20 return -EINVAL; } @@ -1270,7 +1271,7 @@ static void ltdc_plane_atomic_update(struct drm_plane= *plane, enum ltdc_pix_fmt pf; =20 if (!newstate->crtc || !fb) { - DRM_DEBUG_DRIVER("fb or crtc NULL"); + drm_dbg_driver(plane->dev, "fb or crtc NULL"); return; } =20 @@ -1280,11 +1281,11 @@ static void ltdc_plane_atomic_update(struct drm_pla= ne *plane, src_w =3D newstate->src_w >> 16; src_h =3D newstate->src_h >> 16; =20 - DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", - plane->base.id, fb->base.id, - src_w, src_h, src_x, src_y, - newstate->crtc_w, newstate->crtc_h, - newstate->crtc_x, newstate->crtc_y); + drm_dbg_driver(plane->dev, "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d= ,%d)\n", + plane->base.id, fb->base.id, + src_w, src_h, src_x, src_y, + newstate->crtc_w, newstate->crtc_h, + newstate->crtc_x, newstate->crtc_y); =20 regmap_read(ldev->regmap, LTDC_BPCR, &bpcr); =20 @@ -1312,8 +1313,8 @@ static void ltdc_plane_atomic_update(struct drm_plane= *plane, val =3D ltdc_set_flexible_pixel_format(plane, pf); =20 if (val =3D=3D NB_PF) { - DRM_ERROR("Pixel format %.4s not supported\n", - (char *)&fb->format->format); + drm_err(fb->dev, "Pixel format %.4s not supported\n", + (char *)&fb->format->format); val =3D 0; /* set by default ARGB 32 bits */ } regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val); @@ -1350,7 +1351,7 @@ static void ltdc_plane_atomic_update(struct drm_plane= *plane, if (newstate->rotation & DRM_MODE_REFLECT_Y) paddr +=3D (fb->pitches[0] * (y1 - y0)); =20 - DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); + drm_dbg_driver(fb->dev, "fb: phys 0x%08x", paddr); regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr); =20 /* Configures the color frame buffer pitch in bytes & line length */ @@ -1517,8 +1518,8 @@ static void ltdc_plane_atomic_disable(struct drm_plan= e *plane, regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); =20 - DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", - oldstate->crtc->base.id, plane->base.id); + drm_dbg_driver(plane->dev, "CRTC:%d plane:%d\n", + oldstate->crtc->base.id, plane->base.id); } =20 static void ltdc_plane_atomic_print_state(struct drm_printer *p, @@ -1632,7 +1633,7 @@ static struct drm_plane *ltdc_plane_create(struct drm= _device *ddev, =20 drm_plane_create_alpha_property(plane); =20 - DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); + drm_dbg_driver(plane->dev, "plane:%d created\n", plane->base.id); =20 return plane; } @@ -1647,7 +1648,7 @@ static int ltdc_crtc_init(struct drm_device *ddev, st= ruct drm_crtc *crtc) =20 primary =3D ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0); if (!primary) { - DRM_ERROR("Can not create primary plane\n"); + drm_err(ddev, "Can not create primary plane\n"); return -EINVAL; } =20 @@ -1668,7 +1669,7 @@ static int ltdc_crtc_init(struct drm_device *ddev, st= ruct drm_crtc *crtc) ret =3D drmm_crtc_init_with_planes(ddev, crtc, primary, NULL, <dc_crtc_funcs, NULL); if (ret) { - DRM_ERROR("Can not initialize CRTC\n"); + drm_err(ddev, "Can not initialize CRTC\n"); return ret; } =20 @@ -1677,13 +1678,13 @@ static int ltdc_crtc_init(struct drm_device *ddev, = struct drm_crtc *crtc) drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); =20 - DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); + drm_dbg_driver(ddev, "CRTC:%d created\n", crtc->base.id); =20 /* Add planes. Note : the first layer is used by primary plane */ for (i =3D 1; i < ldev->caps.nb_layers; i++) { overlay =3D ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i); if (!overlay) { - DRM_ERROR("Can not create overlay plane %d\n", i); + drm_err(ddev, "Can not create overlay plane %d\n", i); return -ENOMEM; } if (ldev->caps.dynamic_zorder) @@ -1704,7 +1705,7 @@ static void ltdc_encoder_disable(struct drm_encoder *= encoder) struct drm_device *ddev =3D encoder->dev; struct ltdc_device *ldev =3D ddev->dev_private; =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(encoder->dev, "\n"); =20 /* Disable LTDC */ regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); @@ -1718,7 +1719,7 @@ static void ltdc_encoder_enable(struct drm_encoder *e= ncoder) struct drm_device *ddev =3D encoder->dev; struct ltdc_device *ldev =3D ddev->dev_private; =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(encoder->dev, "\n"); =20 /* set fifo underrun threshold register */ if (ldev->caps.fifo_threshold) @@ -1734,7 +1735,7 @@ static void ltdc_encoder_mode_set(struct drm_encoder = *encoder, { struct drm_device *ddev =3D encoder->dev; =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(encoder->dev, "\n"); =20 /* * Set to default state the pinctrl only with DPI type. @@ -1770,7 +1771,7 @@ static int ltdc_encoder_init(struct drm_device *ddev,= struct drm_bridge *bridge) if (ret) return ret; =20 - DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); + drm_dbg_driver(encoder->dev, "Bridge encoder:%d created\n", encoder->base= .id); =20 return 0; } @@ -1870,7 +1871,7 @@ void ltdc_suspend(struct drm_device *ddev) { struct ltdc_device *ldev =3D ddev->dev_private; =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(ddev, "\n"); clk_disable_unprepare(ldev->pixel_clk); } =20 @@ -1879,11 +1880,11 @@ int ltdc_resume(struct drm_device *ddev) struct ltdc_device *ldev =3D ddev->dev_private; int ret; =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(ddev, "\n"); =20 ret =3D clk_prepare_enable(ldev->pixel_clk); if (ret) { - DRM_ERROR("failed to enable pixel clock (%d)\n", ret); + drm_err(ddev, "failed to enable pixel clock (%d)\n", ret); return ret; } =20 @@ -1903,7 +1904,7 @@ int ltdc_load(struct drm_device *ddev) int irq, i, nb_endpoints; int ret =3D -ENODEV; =20 - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(ddev, "\n"); =20 /* Get number of endpoints */ nb_endpoints =3D of_graph_get_endpoint_count(np); @@ -1913,12 +1914,12 @@ int ltdc_load(struct drm_device *ddev) ldev->pixel_clk =3D devm_clk_get(dev, "lcd"); if (IS_ERR(ldev->pixel_clk)) { if (PTR_ERR(ldev->pixel_clk) !=3D -EPROBE_DEFER) - DRM_ERROR("Unable to get lcd clock\n"); + drm_err(ddev, "Unable to get lcd clock\n"); return PTR_ERR(ldev->pixel_clk); } =20 if (clk_prepare_enable(ldev->pixel_clk)) { - DRM_ERROR("Unable to prepare pixel clock\n"); + drm_err(ddev, "Unable to prepare pixel clock\n"); return -ENODEV; } =20 @@ -1939,7 +1940,7 @@ int ltdc_load(struct drm_device *ddev) if (panel) { bridge =3D drmm_panel_bridge_add(ddev, panel); if (IS_ERR(bridge)) { - DRM_ERROR("panel-bridge endpoint %d\n", i); + drm_err(ddev, "panel-bridge endpoint %d\n", i); ret =3D PTR_ERR(bridge); goto err; } @@ -1949,7 +1950,7 @@ int ltdc_load(struct drm_device *ddev) ret =3D ltdc_encoder_init(ddev, bridge); if (ret) { if (ret !=3D -EPROBE_DEFER) - DRM_ERROR("init encoder endpoint %d\n", i); + drm_err(ddev, "init encoder endpoint %d\n", i); goto err; } } @@ -1967,29 +1968,29 @@ int ltdc_load(struct drm_device *ddev) =20 ldev->regs =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(ldev->regs)) { - DRM_ERROR("Unable to get ltdc registers\n"); + drm_err(ddev, "Unable to get ltdc registers\n"); ret =3D PTR_ERR(ldev->regs); goto err; } =20 ldev->regmap =3D devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltd= c_regmap_cfg); if (IS_ERR(ldev->regmap)) { - DRM_ERROR("Unable to regmap ltdc registers\n"); + drm_err(ddev, "Unable to regmap ltdc registers\n"); ret =3D PTR_ERR(ldev->regmap); goto err; } =20 ret =3D ltdc_get_caps(ddev); if (ret) { - DRM_ERROR("hardware identifier (0x%08x) not supported!\n", - ldev->caps.hw_version); + drm_err(ddev, "hardware identifier (0x%08x) not supported!\n", + ldev->caps.hw_version); goto err; } =20 /* Disable all interrupts */ regmap_clear_bits(ldev->regmap, LTDC_IER, IER_MASK); =20 - DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); + drm_dbg_driver(ddev, "ltdc hw version 0x%08x\n", ldev->caps.hw_version); =20 /* initialize default value for fifo underrun threshold & clear interrupt= error counters */ ldev->transfer_err =3D 0; @@ -2008,27 +2009,27 @@ int ltdc_load(struct drm_device *ddev) ltdc_irq_thread, IRQF_ONESHOT, dev_name(dev), ddev); if (ret) { - DRM_ERROR("Failed to register LTDC interrupt\n"); + drm_err(ddev, "Failed to register LTDC interrupt\n"); goto err; } } =20 crtc =3D drmm_kzalloc(ddev, sizeof(*crtc), GFP_KERNEL); if (!crtc) { - DRM_ERROR("Failed to allocate crtc\n"); + drm_err(ddev, "Failed to allocate crtc\n"); ret =3D -ENOMEM; goto err; } =20 ret =3D ltdc_crtc_init(ddev, crtc); if (ret) { - DRM_ERROR("Failed to init crtc\n"); + drm_err(ddev, "Failed to init crtc\n"); goto err; } =20 ret =3D drm_vblank_init(ddev, NB_CRTC); if (ret) { - DRM_ERROR("Failed calling drm_vblank_init()\n"); + drm_err(ddev, "Failed calling drm_vblank_init()\n"); goto err; } =20 @@ -2047,7 +2048,7 @@ int ltdc_load(struct drm_device *ddev) =20 void ltdc_unload(struct drm_device *ddev) { - DRM_DEBUG_DRIVER("\n"); + drm_dbg_driver(ddev, "\n"); =20 pm_runtime_disable(ddev->dev); } --=20 2.25.1