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With the new parsing flow introduced in commit f7fb3b2dd92c ("x86/cpu: Provide an AMD/HYGON specific topology parser"), parse_8000_001e() now unconditionally overwrites the "initial_apicid" already parsed during cpu_parse_topology_ext(). Although this has not been a problem on baremetal platforms, on virtualized AMD guests that feature more than 255 cores, QEMU 0's out the CPUID leaf 0x8000001e on CPUs with "CoreID" > 255 to prevent collision of these IDs in EBX[7:0] which can only represent a maximum of 255 cores [1]. This results in the following FW_BUG being logged when booting a guest with more than 255 cores: [Firmware Bug]: CPU 512: APIC ID mismatch. CPUID: 0x0000 APIC: 0x0200 AMD64 Architecture Programmer's Manual Volume 2: System Programming Pub. 24593 Rev. 3.42 [2] Section 16.12 "x2APIC_ID" mentions the Extended Enumeration leaf 0x8000001e (which was later superseded by the extended leaf 0x80000026) provides the full x2APIC ID under all circumstances unlike the one reported by CPUID leaf 0x8000001e EAX which depends on the mode in which APIC is configured. Rely on the APIC ID parsed during cpu_parse_topology_ext() from CPUID leaf 0x80000026 or 0xb and only use the APIC ID from leaf 0x8000001e if cpu_parse_topology_ext() failed (has_topoext is false). On platforms that support the 0xb leaf (Zen2 or later, AMD guests on QEMU) or the extended leaf 0x80000026 (Zen4 or later), the "initial_apicid" is now set to the value parsed from EDX[31:0]. On older AMD/Hygon platforms that does not support the 0xb leaf but supports the TOPOEXT extension (Fam 0x15, 0x16, 0x17[Zen1], and Hygon), the current behavior is retained where "initial_apicid" is set using the 0x8000001e leaf. Cc: stable@vger.kernel.org Link: https://github.com/qemu/qemu/commit/35ac5dfbcaa4b [1] Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 [2] Debugged-by: Naveen N Rao (AMD) Debugged-by: Sairaj Kodilkar Fixes: c749ce393b8f ("x86/cpu: Use common topology code for AMD") Suggested-by: Thomas Gleixner Tested-by: Naveen N Rao (AMD) Signed-off-by: K Prateek Nayak --- Changelog v3..v4: o Refreshed the diff based on Thomas' suggestion. The tags have been retained since there are no functional changes - only comments around the code has changed. o Quoted relevant section of APM justifying the changes. o Moved this patch up ahead. o Cc'd stable. --- arch/x86/kernel/cpu/topology_amd.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index 843b1655ab45..827dd0dbb6e9 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -81,20 +81,25 @@ static bool parse_8000_001e(struct topo_scan *tscan, bo= ol has_topoext) =20 cpuid_leaf(0x8000001e, &leaf); =20 - tscan->c->topo.initial_apicid =3D leaf.ext_apic_id; - /* - * If leaf 0xb is available, then the domain shifts are set - * already and nothing to do here. Only valid for family >=3D 0x17. + * If leaf 0xb/0x26 is available, then the APIC ID and the domain + * shifts are set already. */ - if (!has_topoext && tscan->c->x86 >=3D 0x17) { + if (!has_topoext) { + tscan->c->topo.initial_apicid =3D leaf.ext_apic_id; + /* - * Leaf 0x80000008 set the CORE domain shift already. - * Update the SMT domain, but do not propagate it. + * Leaf 0x8000008 sets the CORE domain shift but not the + * SMT domain shift. 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Shenoy" , Babu Moger , Suravee Suthikulpanit , K Prateek Nayak , Naveen N Rao , Subject: [PATCH v4 2/4] x86/cpu/topology: Always try cpu_parse_topology_ext() on AMD/Hygon Date: Mon, 25 Aug 2025 07:57:30 +0000 Message-ID: <20250825075732.10694-3-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250825075732.10694-1-kprateek.nayak@amd.com> References: <20250825075732.10694-1-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE9:EE_|CH3PR12MB7619:EE_ X-MS-Office365-Filtering-Correlation-Id: 246f030a-015a-4f5f-d055-08dde3ad3634 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?wphEsZ3Llq7OtS+BPr189DAV1YGFcijvoLP6KeLi4/XxDAavNq21yFO1fgTR?= =?us-ascii?Q?zn6Cj6mLdCGUGRUeuMrm3wJOb7IS6Au0jiAhSAP8Fn0JrsdN7LOp89A2+5gW?= =?us-ascii?Q?0xch/MGqHHO2AzeXttJXsGrRpPT1n/z4CO6s652OGsR6NO0/xbRCJMASKX4U?= =?us-ascii?Q?Of1jGdsfRTXeJ4H1iFUx2FUUZ1gNjAV8HXORSNYnY/xmFNbWXTyEFJZ7d5Jm?= =?us-ascii?Q?mTBMpfsSJSNTHU1CUp41NGIcw9eamXHLHjT/bjZYy0BJtMliG7ReaCEvNChk?= =?us-ascii?Q?gHxehdMHuVVHp9cpZR62g9BTienteUI9C3YmODSBzR6rVFpfaIZYDX9YGoeJ?= =?us-ascii?Q?A+WiHEAt6DFm2B+qrFMRVCdwZFVUWBBxQlwv38TwZyYUDrTgaT3syhYbCb5q?= =?us-ascii?Q?4oWhU/7wnzoftOo74RlQ4Yb9RU3QdsNiW+NiQni1ayxoZ5kJWS0M6lpWntQj?= =?us-ascii?Q?BxEmE08ioYjQaQNoBlkXFa2AvhRhaKf8lrxSOqGAYzYqHYRAd5iY6XIUo+BN?= =?us-ascii?Q?dxamZVVfU9RbSg6HkxFGltD7rWN807bSA61znpun2xw6ubCgA5w9HeQ8thyW?= =?us-ascii?Q?zo0IUU+uTcpoTMxtER7o7WM6MRe8CLdbX/Az6LS4m6sYbnyx4RYdU0zXqKSW?= =?us-ascii?Q?x8KfPew1v5QF+2kSgTHFGtnlHBXLvYQpGzRKagQrpGIwAPIxNeKiHVnAFnw8?= =?us-ascii?Q?KTsxjGZoWif4f2hb7RFRu8p1zcnjZYnBtPsG3hMyn5VhjA2AXvsu15STz8bL?= =?us-ascii?Q?js18il+B9iYRJk8hoZ87lRtQ0TV5CgLQ+xyv3tGvaXKJ8J9NyWcQLQb0kdrM?= =?us-ascii?Q?E4SeA5PoVAdygLAr5/F1YMHcZTtGL0725zbrhtIgZDr+qaQIwPveK6uRMcfb?= =?us-ascii?Q?rgWEW3+qVuG9uiD+aDi8m6n1erqOmM01vFUwvzbE+jSOqGTVwOzQoS28BjdB?= =?us-ascii?Q?BEhRt1tDMTa3vqoQR5YrBhehGWsvCGzPSHAcvPmpuqbJWYjJoeinLFwS9lKc?= =?us-ascii?Q?BwBWxCISsvX1pkVjzZK/J0OfbUGbnN5NDwFTEeg1FrXwdo5qgbN7liSYnyYT?= =?us-ascii?Q?KeSyzP1Ki+qqc74F3wooZla0CXoov5uISQJZ1dnNB1ms5POO5HfRuMjmmaaF?= =?us-ascii?Q?s+ra/mc/QMEPzO1lYJ7gqdu7NfGwVReIXWCNPkKsBipQVwfCvtRZZcOWUCxj?= =?us-ascii?Q?SAzDCQDLiAEKZ0RXJqXX/pFfHUQxseFriPSmDSkY12zlBkXdEc8UijCPKjQN?= =?us-ascii?Q?b78eIA2tkkDXO9u8lwcgaOEPIBs8pRyLAUAAR/e/dnMBrOjUoF53eNDaUlqh?= =?us-ascii?Q?wqwmFzHSP3fhDei0uTaF+hVDpbRnDa2DKyefFJtTEwe+BPZUe9oDLyNFuQbp?= =?us-ascii?Q?4SdYQvnXgn0kGjxh/X9h+ps6v51Iwn0G60ymmQ5YzIIVKueNgA9hzHiKxF6m?= =?us-ascii?Q?tWqmE7C+mi/wfuKx7HWGfWZRdF1+QdRqAOf2TVdPaFNimVfGta903j1tgr+R?= =?us-ascii?Q?9KIiS/O6U48cPtcg7GXWV2dMyA/Tic3DZc1nMYWuLXXbdkTWJo7WGQdB3g?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Aug 2025 07:58:43.4020 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 246f030a-015a-4f5f-d055-08dde3ad3634 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7619 Content-Type: text/plain; charset="utf-8" Support for parsing the topology on AMD/Hygon processors using CPUID leaf 0xb was added in commit 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when available"). In an effort to keep all the topology parsing bits in one place, this commit also introduced a pseudo dependency on the TOPOEXT feature to parse the CPUID leaf 0xb. TOPOEXT feature (CPUID 0x80000001 ECX[22]) advertises the support for Cache Properties leaf 0x8000001d and the CPUID leaf 0x8000001e EAX for "Extended APIC ID" however support for 0xb was introduced alongside the x2APIC support not only on AMD [1], but also historically on x86 [2]. Similar to 0xb, the support for extended CPU topology leaf 0x80000026 too does not depend on the TOPOEXT feature. The support for these leaves is expected to be confirmed by ensuring "leaf <=3D {extended_}cpuid_level" and then parsing the level 0 of the respective leaf to confirm EBX[15:0] (LogProcAtThisLevel) is non-zero as stated in the definition of "CPUID_Fn0000000B_EAX_x00 [Extended Topology Enumeration] (Core::X86::Cpuid::ExtTopEnumEax0)" in Processor Programming Reference (PPR) for AMD Family 19h Model 01h Rev B1 Vol1 [3] Sec. 2.1.15.1 "CPUID Instruction Functions". This has not been a problem on baremetal platforms since support for TOPOEXT (Fam 0x15 and later) predates the support for CPUID leaf 0xb (Fam 0x17[Zen2] and later), however, for AMD guests on QEMU, "x2apic" feature can be enabled independent of the "topoext" feature where QEMU expects topology and the initial APICID to be parsed using the CPUID leaf 0xb (especially when number of cores > 255) which is populated independent of the "topoext" feature flag. Unconditionally call cpu_parse_topology_ext() on AMD and Hygon processors to first parse the topology using the XTOPOLOGY leaves (0x80000026 / 0xb) before using the TOPOEXT leaf (0x8000001e). Cc: stable@vger.kernel.org # Only v6.9 and above Link: https://lore.kernel.org/lkml/1529686927-7665-1-git-send-email-suravee= .suthikulpanit@amd.com/ [1] Link: https://lore.kernel.org/lkml/20080818181435.523309000@linux-os.sc.int= el.com/ [2] Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 [3] Suggested-by: Naveen N Rao (AMD) Fixes: 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function = 0xB when available") Signed-off-by: K Prateek Nayak --- Changelog v3..v4: o Quoted relevant section of the PPR justifying the changes. o Moved this patch up ahead. o Cc'd stable and made a note that backports should target v6.9 and above since this depends on the x86 topology rewrite. --- arch/x86/kernel/cpu/topology_amd.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index 827dd0dbb6e9..4e3134a5550c 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -175,18 +175,14 @@ static void topoext_fixup(struct topo_scan *tscan) =20 static void parse_topology_amd(struct topo_scan *tscan) { - bool has_topoext =3D false; - /* - * If the extended topology leaf 0x8000_001e is available - * try to get SMT, CORE, TILE, and DIE shifts from extended + * Try to get SMT, CORE, TILE, and DIE shifts from extended * CPUID leaf 0x8000_0026 on supported processors first. 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Shenoy" , Babu Moger , Suravee Suthikulpanit , K Prateek Nayak , Naveen N Rao Subject: [PATCH v4 3/4] x86/cpu/topology: Check for X86_FEATURE_XTOPOLOGY instead of passing has_topoext Date: Mon, 25 Aug 2025 07:57:31 +0000 Message-ID: <20250825075732.10694-4-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250825075732.10694-1-kprateek.nayak@amd.com> References: <20250825075732.10694-1-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE7:EE_|BY1PR12MB8448:EE_ X-MS-Office365-Filtering-Correlation-Id: 1d78a4e7-aa71-4ab8-a14f-08dde3ad44ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?vDYOGE73Tb+Q41C8aURhMZfdv2FZyQYfkETUFbqW7XNYjkJgbwMHUU1v92vN?= =?us-ascii?Q?jhNHpW6vpDNTnqIsK2WbslF2sVbvWh8ArMaRgoCtfPRqRPgqVF9+DlazTWMD?= =?us-ascii?Q?kPdCLSFtbLCPlKifCucED7xyrXUSJWCJNFajRHteEpg+sujNrAucE8286CzS?= =?us-ascii?Q?8xfBkVo/+mMIa7HNEiDBeKvWe/Ixm5GgJF9ddOt0hwwB9mB9+n1kofemTGK7?= =?us-ascii?Q?5WOeO2LVqxySquTAdTfv9m3lPWP1KRvkJI/RfKEzyAplkSG+AWsrPEFf0C5w?= =?us-ascii?Q?80H3R0ZEVbk0MHxLtYr+q62hUvtceFv+iE4VI/66H72eJsrow55J5mh8HvPa?= =?us-ascii?Q?SScTHJE5SYriZ8e9xndmtGan2UxKK08b/W+R6g0OfwxUCSjsF+gTIaBoKHrJ?= =?us-ascii?Q?X3ohF0egLfsYOyyT73mN3O8YxaoDoIaSINBTL4hW0rLmgk97NrgmCxeixn3l?= =?us-ascii?Q?JpWDi882Zn+Q+BXnJsFC8sMIlWptwGTd9/vpvPoZo28GkjlPZvhYUBrfDGT6?= =?us-ascii?Q?sA+y6mMFr+JCRQhkXQNVj3ITOC4QXwrj3XWLFO/VppyQ7Q2Y9ZOkpbaN1Ldn?= =?us-ascii?Q?G8qGzwiqyg8JlcUajLchNtDU40k4YyOIlElsCsMHpu3Ya4xDmeEym9gzr/we?= =?us-ascii?Q?O9EhLsxlEEFpaDudEk3g8nLIDZswN455Tr+q9GtAPXB70DKWsUeX1zlvwBxu?= =?us-ascii?Q?qIrTOw0BDGnLMYu/8G3k6sxV5jWlIl0+ItkaD23CncOgTLSFvUCkbSkyJthy?= =?us-ascii?Q?eq4QmXpnpLYh19ZPjksa30bWO6VkS9Xm2BnzTRIjF7szSIcMHzmj/nWN4RDd?= =?us-ascii?Q?h2pPBL0/1bAhYwPSlnZZxoAswRLKyguJGWk2oxYTVEz+DXaN0Mz+BWRjhx+K?= =?us-ascii?Q?bSC2/DCKvq7dljiDB8RtolQtf1abr35soNSvFh17BwBYzvqgwh4OMkf/GZz1?= =?us-ascii?Q?5BoyZV5BWSLHdE7mnkhbM6AkCRFDjAx+EWoEopkJQHeclNl4MUkfsWxWmKvs?= =?us-ascii?Q?Mrr0NRgVI2g9B/Jc9ng62eBXRA7gWD/PohO2o8eA8WhA2TWtxz+jgzrElZX/?= =?us-ascii?Q?GH4uVI4kJy5h3t0v/3NddEYpzU3iy/MSdxSkJB7q2gqKLj7RNbDi4BsKSYUh?= =?us-ascii?Q?Yz4TeCHmdfPf/9Bc8FXunPpkD/u+WdQQQ6SOg2bVNBZvnGCD938xsboDXlAI?= =?us-ascii?Q?9aGhvIDdis2nVk1ed/XJ2N2puoygxYFLHtBPYI/Be/p18e5mGqAGxZU86AHd?= =?us-ascii?Q?lbRTOLLqXfSusobq2ACQurCBPMjUU9DW0oXCwWf0XAoiP9adudw0L5Rzl5FU?= =?us-ascii?Q?c55brWQIZYTkyU7qTKGRuPVrGUZkAmcQ3of88PzPKW2tSiQQeT9NBDP0wd7A?= =?us-ascii?Q?3rlstjNQnGOU5Y4SO/hp/KEq36awMPa1SNfZx7k+XMztyFGE07yGjTDnAhUZ?= =?us-ascii?Q?iaGhpb4NOVNllU0v3C3qhn20ry+NNC8G8gJTbE/mwc8HIXvHHpNSDwcHuAAo?= =?us-ascii?Q?PKjvYaaszqVAgN3d9AZZLzBTSo+4oyOnJqXV?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Aug 2025 07:59:07.8787 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d78a4e7-aa71-4ab8-a14f-08dde3ad44ca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR12MB8448 Content-Type: text/plain; charset="utf-8" cpu_parse_topology_ext() sets X86_FEATURE_XTOPOLOGY before returning true if any of the XTOPOLOGY leaf (0x80000026 / 0xb) could be parsed successfully. Instead of storing and passing around this return value using "has_topoext" in parse_topology_amd(), check for X86_FEATURE_XTOPOLOGY instead in parse_8000_001e() to simplify the flow. No functional changes intended. Signed-off-by: K Prateek Nayak --- Changelog v3..v4: o Moved this to Patch 3. No changes to diff. --- arch/x86/kernel/cpu/topology_amd.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index 4e3134a5550c..12ece07b407b 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -59,7 +59,7 @@ static void store_node(struct topo_scan *tscan, u16 nr_no= des, u16 node_id) tscan->amd_node_id =3D node_id; } =20 -static bool parse_8000_001e(struct topo_scan *tscan, bool has_topoext) +static bool parse_8000_001e(struct topo_scan *tscan) { struct { // eax @@ -85,7 +85,7 @@ static bool parse_8000_001e(struct topo_scan *tscan, bool= has_topoext) * If leaf 0xb/0x26 is available, then the APIC ID and the domain * shifts are set already. */ - if (!has_topoext) { + if (!cpu_feature_enabled(X86_FEATURE_XTOPOLOGY)) { tscan->c->topo.initial_apicid =3D leaf.ext_apic_id; =20 /* @@ -175,6 +175,9 @@ static void topoext_fixup(struct topo_scan *tscan) =20 static void parse_topology_amd(struct topo_scan *tscan) { + if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) + tscan->c->topo.cpu_type =3D cpuid_ebx(0x80000026); + /* * Try to get SMT, CORE, TILE, and DIE shifts from extended * CPUID leaf 0x8000_0026 on supported processors first. If @@ -182,16 +185,11 @@ static void parse_topology_amd(struct topo_scan *tsca= n) * get SMT and CORE shift from leaf 0xb first, then try to * get the CORE shift from leaf 0x8000_0008. */ - bool has_topoext =3D cpu_parse_topology_ext(tscan); - - if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) - tscan->c->topo.cpu_type =3D cpuid_ebx(0x80000026); - - if (!has_topoext && !parse_8000_0008(tscan)) + if (!cpu_parse_topology_ext(tscan) && !parse_8000_0008(tscan)) return; =20 /* Prefer leaf 0x8000001e if available */ - if (parse_8000_001e(tscan, has_topoext)) + if (parse_8000_001e(tscan)) return; =20 /* Try the NODEID MSR */ --=20 2.34.1 From nobody Fri Oct 3 20:56:11 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2040.outbound.protection.outlook.com [40.107.244.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA2EB2882CC; Mon, 25 Aug 2025 07:59:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 25 Aug 2025 02:59:22 -0500 From: K Prateek Nayak To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Sean Christopherson , Paolo Bonzini , CC: Naveen rao , Sairaj Kodilkar , "H. Peter Anvin" , "Peter Zijlstra (Intel)" , "Xin Li (Intel)" , Pawan Gupta , Tom Lendacky , , , Mario Limonciello , "Gautham R. Shenoy" , Babu Moger , Suravee Suthikulpanit , K Prateek Nayak , Naveen N Rao Subject: [PATCH v4 4/4] x86/msr-index: Define AMD64_CPUID_FN_EXT MSR Date: Mon, 25 Aug 2025 07:57:32 +0000 Message-ID: <20250825075732.10694-5-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250825075732.10694-1-kprateek.nayak@amd.com> References: <20250825075732.10694-1-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE8:EE_|CY1PR12MB9699:EE_ X-MS-Office365-Filtering-Correlation-Id: f9e534c2-de57-45f0-5a50-08dde3ad5248 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?d1V4cRtTZRS2nDBSf4z+5Mql97o+1fOpWd4ARWsAccYDrG64VwH65mXJlm0+?= =?us-ascii?Q?cBVxSj+MXmw0kJrRmlowNI0mQwezeTH55gyWJbYSBAgOKg0UNNnf8kViFLN5?= =?us-ascii?Q?YaULu4atDUA9CqflA8V27cmi7dcokvm8qE0h0aOTeew3vRg9/ux7knfDG4Yk?= =?us-ascii?Q?NqOkURz6yh+8H9Fp+Df0V+nJa6sP9CA9ooNX9xp/JhOgRgX670qgDI+/5Qei?= =?us-ascii?Q?yPYicp9VAXDaabKmbQyFzaJ/Uzq4QmCdokokerPaIcIOATcO6wqs5w/G+3Xh?= =?us-ascii?Q?E12ssIAi1MawWZbSpO24fgk7QG4eyIQDrg6ibb5QmzWxdjKNBFXJYCSziE8B?= =?us-ascii?Q?PfDkFD8yokr4Fo5kUb6TORydz6JsNvyYUaYz8UM/4TpWRCB02Ed9Mey2Ijzu?= =?us-ascii?Q?/5PnOT3GWnosJmCREKjcOz2zew3epYTwd1bw6Tb1DcE0aUxSPwJgxaIqnLlS?= =?us-ascii?Q?wFPYFSke26e5QkULY+8i6RD197gbpkF4nwkBT0H/anAgdoiHeRsFDs8S5h7K?= =?us-ascii?Q?QVr5Tw88kHKm9/19kaWNlJ4DJVL7shc3s0ocyUYN888wB4nOtCdVt3PS/gHj?= =?us-ascii?Q?bbVs1ph9ElDDrqb+yhdysXUL06ejqVo7vEPFd5HllPzOe40KUC5oVfIq61s4?= =?us-ascii?Q?ozo6IP7I/W6erg/h42lr/SLNxqWs6GQfA/FWeIVwZnJtIJNEqpKtkH83fMRJ?= =?us-ascii?Q?gJtPCVATATakV/QjJkcVtJhj7uQj7+aXcvmeZQ9AInzoP1+7wqrEzOMa19YC?= =?us-ascii?Q?XKGCS+qsAxKId4JCw3JzEzEuhuVTwgb3qIUgBYwwOkYo6OmKKs+/GaD9OySf?= =?us-ascii?Q?gu4pfjpi8dGeFzZYj/MI0HgGqifMUNVkhVdvAylDpY1j8Y2ytja63RdP7CbJ?= =?us-ascii?Q?RM9dTCc/cK0RsjZxPPKF//48sFPzQo5+AXTt8W0/6IrDD7xrNquwz7xSSN9Y?= =?us-ascii?Q?duj4e1RBWaM0rtfq6Ju2XpbApDOPA6Hp5LF6gYGQYDbzYnRLJ3WNSXCk9/0F?= =?us-ascii?Q?mxQIq7D4HN+eCGuwO27WxZsoYTGmiYzS3XJnJTfGnBuRGq9ge0C9uhJQa7lO?= =?us-ascii?Q?qFivrCj5yIMHtns31KwqIQyPL7AijqRQWcbCCD2Np04M/JdjVrd3+WqRnPUn?= =?us-ascii?Q?TyN8ZZ6bHCUmgrAyiv9L22PyLYeM9WjM2S9+jv9btAE2n1Jqt8M8SgODF8aP?= =?us-ascii?Q?a3IKF/VbtSk45pH9MctMWiXqy0QlE7VyhqaQzG5Ih22qe/C8q46T3fBv+PxB?= =?us-ascii?Q?PWZ7udLXBfFNgp39M/tpLn358QnAM4+hdA1QRX61pL+XgQcZmsmtchckw/Mh?= =?us-ascii?Q?1tqyoYVZemNSPkZeFaOtspvDyeswZQjwPXvF5ujm1s/nmqHYPt/Xl5LHZtCK?= =?us-ascii?Q?vyVvzEEdFAsAAetsSxaK79BCPCA4m/G9VRToGwdLfBIShLKrVIbfMOdbfmQr?= =?us-ascii?Q?1dFWOfm0WHjlUYtcOYArWyE85IBajPAtCs4XCdsN7uc3l2YniqAfwu1rU980?= =?us-ascii?Q?HEZQkkC69/HbtfOFQekgOBRYHbhJe34cc7UA?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Aug 2025 07:59:30.5098 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9e534c2-de57-45f0-5a50-08dde3ad5248 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9699 Content-Type: text/plain; charset="utf-8" Explicitly define the AMD64_CPUID_FN_EXT MSR used to toggle the extended features. Also define and use the bits necessary for an old TOPOEXT fixup on AMD Family 0x15 processors. No functional changes intended. Signed-off-by: K Prateek Nayak --- Changelog v3..v4: o Moved this to Patch 4. No changes to diff. --- arch/x86/include/asm/msr-index.h | 5 +++++ arch/x86/kernel/cpu/topology_amd.c | 7 ++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index b65c3ba5fa14..e194287177db 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -631,6 +631,11 @@ #define MSR_AMD_PPIN 0xc00102f1 #define MSR_AMD64_CPUID_FN_7 0xc0011002 #define MSR_AMD64_CPUID_FN_1 0xc0011004 + +#define MSR_AMD64_CPUID_FN_EXT 0xc0011005 +#define MSR_AMD64_CPUID_FN_EXT_TOPOEXT_ENABLED_BIT 54 +#define MSR_AMD64_CPUID_FN_EXT_TOPOEXT_ENABLED BIT_ULL(MSR_AMD64_CPUID_FN= _EXT_TOPOEXT_ENABLED_BIT) + #define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_DC_CFG 0xc0011022 #define MSR_AMD64_TW_CFG 0xc0011023 diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index 12ece07b407b..6e8186f05cde 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -163,11 +163,12 @@ static void topoext_fixup(struct topo_scan *tscan) c->x86 !=3D 0x15 || c->x86_model < 0x10 || c->x86_model > 0x6f) return; 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Mon, 1 Sep 2025 03:11:50 -0700 From: K Prateek Nayak To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Sean Christopherson , Paolo Bonzini , CC: Naveen rao , Sairaj Kodilkar , "H. Peter Anvin" , "Peter Zijlstra (Intel)" , "Xin Li (Intel)" , Pawan Gupta , , , Mario Limonciello , "Gautham R. Shenoy" , Babu Moger , Suravee Suthikulpanit , Naveen N Rao , K Prateek Nayak Subject: [RFC PATCH v4 5/4] Documentation/x86/topology: Detail CPUID leaves used for topology enumeration Date: Mon, 1 Sep 2025 10:11:30 +0000 Message-ID: <20250901101130.3661-1-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250825075732.10694-1-kprateek.nayak@amd.com> References: <20250825075732.10694-1-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To satlexmb09.amd.com (10.181.42.218) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003441:EE_|SJ0PR12MB7036:EE_ X-MS-Office365-Filtering-Correlation-Id: 40cca47c-fbb5-4c88-e85a-08dde93ffb96 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?EFKBcY5l0vEkuzHE9Yn15z/gV3wh9m2CQWIDNCahH9lgWKEGKXqbhXdGTbn3?= =?us-ascii?Q?hvgKzjo+Fva1hfTZhfaFfd7mgvUq03ouphZgsV8f4lhcarQeIt0r9xIeVFcT?= =?us-ascii?Q?V2yfK4vNWZ3I5DGmV5kqR1xS2SXsffd09sKbXkAvfIlY9xwf6x6aOsOJfgBY?= =?us-ascii?Q?8dBy3FpJiprm54uNT67CieWRcH58gQEwSoe1WTP+CJvUH8ug6bSBrJlPCCq1?= =?us-ascii?Q?5Z4gki5yzVjpLXbX3/GM5HCFnmIM9So67ohfYXBQACn6GorMrcXQc4QuN16g?= =?us-ascii?Q?YxTdZ8V2ge1CYQJwALuv+W44u12GY+b99gf/1VsDot3dplIqZ51DZZHKddi9?= =?us-ascii?Q?Wah+c643oIC6AqX6jd4kVHFeh0dIKENFrRVX9wp01oJb5AYOuCtBqtmwmHLl?= =?us-ascii?Q?m8XNJJypSOQ5kb4iuyg6JEOM308PizjzFUXtV2KnVTH5hdJ56cRMZJbgJxqZ?= =?us-ascii?Q?EQ2G5hoeyVcZwdSvunfbm32tB255Vg4y1OjLptsQ0BrEjCg36vlAE0UyPljZ?= =?us-ascii?Q?s4Xds0gMWEJfHVPubvHl2VURMXyh0lmpPvpCrJldbn1pPo+3tu1nI06AOzvc?= =?us-ascii?Q?6Iz9nrm4b6hZtyNQwcg3WO45bPxWtm71cZSCXMtEQWjUuFsYeyepe4hHl1+e?= =?us-ascii?Q?wD+v4XbTZhISFmPa78Lwu/vKnF5CibS0pzq9vNI6F+nBBocZ3eGZ5QMtWBpy?= =?us-ascii?Q?g014fDmKelxssGwEzm7ZyCuDIm9HUdyr7bDSGsRNtY9b2kKxohhagbGhvXn5?= =?us-ascii?Q?jjye09uthEIQW9Adb1pcRHXh/L2chO8Aq3hgTvOgbViIm4lDW2RaSjC7MmCk?= =?us-ascii?Q?EfqiYSsLSwoYuO/HFyJ0E7MKaPRAVVLskJVb1HZUSo4pqS0p+5lPMoyrXE/b?= =?us-ascii?Q?GWMlyV6gFKoB69vEBznje2XHTSNrw4mhtJwYUL+ZW5sKp7tkebr8PWaXbwSm?= =?us-ascii?Q?F8RzUrzWt7y0DbhaZBKDIy9TiMC5gGRKI6ciY5jPRaVMAEem49hUeqa9N4Br?= =?us-ascii?Q?6uvgT1fznRVy7bh+udHYbt3ogWygCH0GDwb/chaDWuBv7L1Hq0b/0ONv6k5N?= =?us-ascii?Q?W+HYhGYFFXdcOjdsV5cWZxEU+P7uG1wxurHtAyJIIF3rdgjS/ltFEmXrtWWd?= =?us-ascii?Q?nTBzhgLfs7jnwieBXHS5qhGqpzUvG94TAWKPVc+Et2wv3DecalMfyrPkEOh7?= =?us-ascii?Q?GrJkESUStYyJtAC2WzXsL+ZZ7pSwhdx1YwH2kR4DtHxm1kjXo1aF4Vs87ZwH?= =?us-ascii?Q?xJWKnZKY50B/segmw9mAuo1YfFkjNCNggrH1Bj0Hb+Q0BXBvJAiVwkeemkeh?= =?us-ascii?Q?WOH6E2O+hO18zD7605tf+K94lWG3/pM8hRywnk00OedS+7cdHMTNwd49UKjH?= =?us-ascii?Q?BW7Nd+wyNFXmQgWBG3e5o/OqOIDCL1CrUU5XloZh3E8Y+ppUMVkHQMOx0QEu?= =?us-ascii?Q?d3tOYpD81g3UpEba53gC0g50bCxf+w8zq23H1iwBoRmx6YQoS1kCdxBWgBNJ?= =?us-ascii?Q?a5gFFjBTu9Tx8L8yLFxegJ0QDPyvJ8FTAFhZ?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2025 10:11:56.8854 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40cca47c-fbb5-4c88-e85a-08dde93ffb96 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003441.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7036 Content-Type: text/plain; charset="utf-8" Add a new section describing the different CPUID leaves and fields used to parse topology on x86 systems. Suggested-by: Borislav Petkov Signed-off-by: K Prateek Nayak --- Sending this as an RFC patch first to squash out the amount of details required in topology.rst. Once clarified, I'll include this formally in v5. --- Documentation/arch/x86/topology.rst | 194 ++++++++++++++++++++++++++++ 1 file changed, 194 insertions(+) diff --git a/Documentation/arch/x86/topology.rst b/Documentation/arch/x86/t= opology.rst index c12837e61bda..fd9903aab6b5 100644 --- a/Documentation/arch/x86/topology.rst +++ b/Documentation/arch/x86/topology.rst @@ -141,6 +141,200 @@ Thread-related topology information in the kernel: =20 =20 =20 +System topology enumeration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D +The topology on x86 systems can be discovered using a combination of vendor +specific CPUID leaves introduced specifically to enumerate the processor +topology and the cache hierarchy. + +The CPUID leaves in their preferred order of parsing for each x86 vendor i= s as +follows: + +1) AMD and Hygon + + On AMD and Hygon platforms, the CPUID leaves that enumerate the process= or + topology are as follows: + + 1) CPUID leaf 0x80000026 [Extended CPU Topology] (Core::X86::Cpuid::ExC= puTopology) + + The extended CPUID leaf 0x80000026 is the extension of the CPUID lea= f 0xB + and provides the topology information of Core, Complex, CCD(Die), and + Socket in each level. + + The support for the leaf is expected to be discovered by checking if= the + supported extended CPUID level is >=3D 0x80000026 and then checking = if + `LogProcAtThisLevel` in `EBX[15:0]` at a particular level (starting = from + 0) is non-zero. + + The `LevelType` in `ECX[15:8]` at the level provides the detail of t= he + topology domain that the level describes - Core, Complex, CCD(Die), = or + the Socket. + + The kernel uses the `CoreMaskWidth` from `EAX[4:0]` to discover the + number of bits that need to be right shifted from the + `ExtendedLocalApicId` in `EDX[31:0]` to get a unique Topology ID for + the topology level. CPUs with the same Topology ID share the resourc= es + at that level. + + CPUID leaf 0x80000026 also provides more information regarding the + power and efficiency rankings, and about the core type on AMD + processors with heterogeneous characteristics. + + If CPUID leaf 0x80000026 is supported, further parsing is not requir= ed. + + + 2) CPUID leaf 0x0000000B [Extended Topology Enumeration] (Core::X86::Cp= uid::ExtTopEnum) + + The extended CPUID leaf 0x0000000B is the predecessor on the extended + CPUID leaf 0x80000026 and only describes the core, and the socket do= mains + of the processor topology. + + The support for the leaf is expected to be discovered by checking if= the + supported CPUID level is >=3D 0xB and then checking if `EBX[31:0]` a= t a + particular level (starting from 0) is non-zero. + + The `LevelType` in `ECX[15:8]` at the level provides the detail of t= he + topology domain that the level describes - Thread, or Processor (Soc= ket). + + The kernel uses the `CoreMaskWidth` from `EAX[4:0]` to discover the + number of bits that need to be right shifted from the + `ExtendedLocalApicId` in `EDX[31:0]` to get a unique Topology ID for + that topology level. CPUs sharing the Topology ID share the resources + at that level. + + If CPUID leaf 0xB is supported, further parsing is not required. + + + 3) CPUID leaf 0x80000008 ECX [Size Identifiers] (Core::X86::Cpuid::Size= Id) + + If neither the CPUID leaf 0x80000026 or CPUID leaf 0xB is supported,= the + number of CPUs on the package is detected using the Size Identifier = leaf + 0x80000008 ECX. + + The support for the leaf is expected to be discovered by checking if= the + supported extended CPUID level is >=3D 0x80000008. + + The shifts from the APIC ID for the Socket ID is calculated from the + `ApicIdSize` field in `ECX[15:12]` if it is non-zero. + + If `ApicIdSize` is reported to be zero, the shift is calculated as t= he + order of the `number of threads` calculated from `NC` field in + `ECX[7:0]` which describes the `number of threads - 1` on the packag= e. + + Unless Extended APIC ID is supported, the APIC ID used to find the + Socket ID is from the `LocalApicId` field of CPUID leaf 0x00000001 + `EBX[31:24]`. + + The topology parsing continues to detect if Extended APIC ID is + supported or not. + + + 4) CPUID leaf 0x8000001E [Extended APIC ID, Core Identifiers, Node Iden= tifiers] + (Core::X86::Cpuid::{ExtApicId,CoreId,NodeId}) + + The support for Extended APIC ID can be detected by checking for the + presence of `TopologyExtensions` in `EXC[22]` of CPUID leaf 0x800000= 01 + [Feature Identifiers] (Core::X86::Cpuid::FeatureExtIdEcx). + + If Topology Extensions is supported, the APIC ID from `ExtendedApicI= d` + from CPUID leaf 0x8000001E `EAX[31:0]` should be preferred over that= from + `LocalApicId` field of CPUID leaf 0x00000001 `EBX[31:24]` for topolo= gy + enumeration. + + On processors of Family 0x17 and above that do not support CPUID leaf + 0x80000026 or CPUID leaf 0xB, the shifts from the APIC ID for the Co= re + ID is calculated using the order of `number of threads per core` + calculated using the `ThreadsPerCore` field in `EBX[15:8]` which + describes `number of threads per core - 1`. + + On Processors of Family 0x15, the Core ID from `EBX[7:0]` is used as= the + `cu_id` (Compute Unit ID) to detect CPUs that share the compute unit= s. + + + All AMD and Hygon processors that support the `TopologyExtensions` feat= ure + stores the `NodeId` from the `ECX[7:0]` of CPUID leaf 0x8000001E + (Core::X86::Cpuid::NodeId) as the per-CPU `node_id`. + + +2) Intel + + On Intel platforms, the CPUID leaves that enumerate the processor + topology are as follows: + + 1) CPUID leaf 0x1F (V2 Extended Topology Enumeration Leaf) + + The CPUID leaf 0x1F is the extension of the CPUID leaf 0xB and provi= des + the topology information of Core, Module, Tile, Die, DieGrp, and Soc= ket + in each level. + + The support for the leaf is expected to be discovered by checking if + the supported CPUID level is >=3D 0x1F and then `EBX[31:0]` at a + particular level (starting from 0) is non-zero. + + The `Domain Type` in `ECX[15:8]` of the sub-leaf provides the detail= of + the topology domain that the level describes - Core, Module, Tile, D= ie, + DieGrp, and Socket. + + The kernel uses the value from `EAX[4:0]` to discover the number of + bits that need to be right shifted from the `x2APIC ID` in `EDX[31:0= ]` + to get a unique Topology ID for the topology level. CPUs with the sa= me + Topology ID share the resources at that level. + + If CPUID leaf 0x1F is supported, further parsing is not required. + + + 2) CPUID leaf 0x0000000B (Extended Topology Enumeration Leaf) + + The extended CPUID leaf 0x0000000B is the predecessor of the V2 Exte= nded + Topology Enumeration Leaf 0x1F and only describes the core, and the + socket domains of the processor topology. + + The support for the leaf is expected to be discovered by checking if= the + supported CPUID level is >=3D 0xB and then checking if `EBX[31:0]` a= t a + particular level (starting from 0) is non-zero. + + CPUID leaf 0x0000000B shares the same layout as CPUID leaf 0x1F and + should be enumerated in a similar manner. + + If CPUID leaf 0xB is supported, further parsing is not required. + + + 3) CPUID leaf 0x00000004 (Deterministic Cache Parameters Leaf) + + On Intel processors that support neither CPUID leaf 0x1F, nor CPUID = leaf + 0xB, the shifts for the SMT domains is calculated using the number of + CPUs sharing the L1 cache. + + Processors that feature Hyper-Threading is detected using `EDX[28]` = of + CPUID leaf 0x1 (Basic CPUID Information). + + The order of `Maximum number of addressable IDs for logical processo= rs + sharing this cache` from `EAX[25:14]` of level-0 of CPUID 0x4 provid= es + the shifts from the APIC ID required to compute the Core ID. + + The APIC ID and Package information is computed using the data from + CPUID leaf 0x1. + + + 4) CPUID leaf 0x00000001 (Basic CPUID Information) + + The mask and shifts to derive the Physical Package (socket) ID is + computed using the `Maximum number of addressable IDs for logical + processors in this physical package` from `EBX[23:16]` of CPUID leaf + 0x1. + + The APIC ID on the legacy platforms is derived from the `Initial APIC + ID` field from `EBX[31:24]` of CPUID leaf 0x1. + + +3) Centaur and Zhaoxin + + Similar to Intel, Centaur and Zhaoxin use a combination of CPUID leaf + 0x00000004 (Deterministic Cache Parameters Leaf) and CPUID leaf 0x00000= 001 + (Basic CPUID Information) to derive the topology information. + + + System topology examples =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 --=20 2.34.1