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Sun, 24 Aug 2025 23:53:48 -0700 (PDT) From: Anand Moon To: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v2 08/11] arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC Date: Mon, 25 Aug 2025 12:21:48 +0530 Message-ID: <20250825065240.22577-9-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250825065240.22577-1-linux.amoon@gmail.com> References: <20250825065240.22577-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per C3 datasheet add missing cache information to the Amlogic C3 SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 23 +++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-c3.dtsi index cb9ea3ca6ee0..ee0b1ffa947e 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -23,6 +23,13 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a35"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2>; }; =20 cpu1: cpu@1 { @@ -30,6 +37,22 @@ cpu1: cpu@1 { compatible =3D "arm,cortex-a35"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x7d000>; /* L2. 512 KB */ + cache-line-size =3D <64>; + cache-sets =3D <512>; }; }; =20 --=20 2.50.1