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Sun, 24 Aug 2025 23:54:11 -0700 (PDT) From: Anand Moon To: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v2 11/11] arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC Date: Mon, 25 Aug 2025 12:21:51 +0530 Message-ID: <20250825065240.22577-12-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250825065240.22577-1-linux.amoon@gmail.com> References: <20250825065240.22577-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per T7 datasheet add missing cache information to the Amlogic T7 SoC. - Each Cortex-A53 core has 32 KB of instruction cache and 32 KB of L1 data cache available. - Each Cortex-A73 core has 64 KB of L1 instruction cache and 64 KB of L1 data cache available. - The little (A53) cluster has 256 KB of unified L2 cache available. - The big (A73) cluster has 1 MB of unified L2 cache available. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 74 +++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-t7.dtsi index ec743cad57db..6510068bcff9 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -53,6 +53,13 @@ cpu100: cpu@100 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x100>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; }; =20 cpu101: cpu@101 { @@ -60,6 +67,13 @@ cpu101: cpu@101 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x101>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; }; =20 cpu102: cpu@102 { @@ -67,6 +81,13 @@ cpu102: cpu@102 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x102>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; }; =20 cpu103: cpu@103 { @@ -74,6 +95,13 @@ cpu103: cpu@103 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x103>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; }; =20 cpu0: cpu@0 { @@ -81,6 +109,13 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a73"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-line-size =3D <64>; + d-cache-size =3D <0x10000>; + d-cache-sets =3D <64>; + i-cache-line-size =3D <64>; + i-cache-size =3D <0x10000>; + i-cache-sets =3D <64>; + next-level-cache =3D <&l2_cache_b>; }; =20 cpu1: cpu@1 { @@ -88,6 +123,13 @@ cpu1: cpu@1 { compatible =3D "arm,cortex-a73"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-line-size =3D <64>; + d-cache-size =3D <0x10000>; + d-cache-sets =3D <64>; + i-cache-line-size =3D <64>; + i-cache-size =3D <0x10000>; + i-cache-sets =3D <64>; + next-level-cache =3D <&l2_cache_b>; }; =20 cpu2: cpu@2 { @@ -95,6 +137,13 @@ cpu2: cpu@2 { compatible =3D "arm,cortex-a73"; reg =3D <0x0 0x2>; enable-method =3D "psci"; + d-cache-line-size =3D <64>; + d-cache-size =3D <0x10000>; + d-cache-sets =3D <64>; + i-cache-line-size =3D <64>; + i-cache-size =3D <0x10000>; + i-cache-sets =3D <64>; + next-level-cache =3D <&l2_cache_b>; }; =20 cpu3: cpu@3 { @@ -102,6 +151,31 @@ cpu3: cpu@3 { compatible =3D "arm,cortex-a73"; reg =3D <0x0 0x3>; enable-method =3D "psci"; + d-cache-line-size =3D <64>; + d-cache-size =3D <0x10000>; + d-cache-sets =3D <64>; + i-cache-line-size =3D <64>; + i-cache-size =3D <0x10000>; + i-cache-sets =3D <64>; + next-level-cache =3D <&l2_cache_b>; + }; + + l2_cache_l: l2-cache-cluster0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x40000>; /* L2. 256 KB */ + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x100000>; /* L2. 1 Mb */ + cache-line-size =3D <64>; + cache-sets =3D <512>; }; }; =20 --=20 2.50.1