From nobody Fri Oct 3 20:55:17 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E36AD27A92B; Mon, 25 Aug 2025 04:37:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756096630; cv=none; b=cfmj5AP/H9qNygGxGnhz+jy8rJOK2HxMV6qmKOc9FfBNZ854bRpiKQgV64fZt0poSIZvfygB3k135C2RR0Wg7JIEC3MOkk5B1YlJFrBRu0WuLZF8ZNdkQfTkjtLnOH/TOKOAs9TTg/VaL76XegqOYIR6l1yfxr4AHgDS+s12ziw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756096630; c=relaxed/simple; bh=b4w+gwqwtw8jaVjIT5NkaB1GvAbcqViIx0JJSp73DWw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YEAh2jORlBCErUKuQngWJRiux25cuTJHRAn8Mg0bon4ZvMIck1qZ7YAQWVweMMhZZRnApKWacgy8eo/wrjusRPzcSMsWIlvcSLMsc1XYC+LErR/pHCyyFeXLQX5CfCkjJGvzxJxIleHmC/H5URGVsHcZQ3uQNharchUTfyG2Y8o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=trkMII5O; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="trkMII5O" Received: by smtp.kernel.org (Postfix) with ESMTPS id 82547C113D0; Mon, 25 Aug 2025 04:37:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756096629; bh=b4w+gwqwtw8jaVjIT5NkaB1GvAbcqViIx0JJSp73DWw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=trkMII5Ox6ZMf98mpbWOjxcCgnICVtL7N7s3U+2Z9/JtRKSJqs/dBcMOjZCBCD/F6 /8Pfz6Bv5REcPCXnWoaMhu0GpkzYbjgftQSQ7CIQN+6dLviae06OWysOohpkEJzWSA kij/zppIxoXxfESLLbCUZfzkctG3/IIwSCfDXAnrettSjCcx0bxdPjYpRH5XO/xcgF JkJbeOah71cQtoDq+FOLW8B2m/zBmTwTh0jSsRW00lW/rcks9U51hBhA4haXoLOBog i2AiMnS8dMl5Ei5lJP02GA6xXpupbnBelSWszKnQHkitoxBnQZ9x0OTIGnojTtwk1H MV86hFyIo6+Tw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 724A2CA0EFA; Mon, 25 Aug 2025 04:37:09 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Mon, 25 Aug 2025 12:36:52 +0800 Subject: [PATCH net v3 1/3] net: stmmac: xgmac: Do not enable RX FIFO Overflow interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-xgmac-minor-fixes-v3-1-c225fe4444c0@altera.com> References: <20250825-xgmac-minor-fixes-v3-0-c225fe4444c0@altera.com> In-Reply-To: <20250825-xgmac-minor-fixes-v3-0-c225fe4444c0@altera.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jose Abreu , Romain Gantois , Serge Semin , Ong Boon Leong Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas , Matthew Gerlach , Andrew Lunn X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756096627; l=1566; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=QWGQxxx04QXnQVil1cRXWyuv2Z+9ky3b4DH7/yCcKX0=; b=lAlkVhkfrhzBmqbrKeG2Aj0G77WLpZ7k4Q+AxbjaChtv/bWAEDBNs7o1YjbwUYcylK5QXM+ED tWB10lZn9OCBvxoTRXIWXq/r0mmjy2pWtC1nZqKvacI6pG7ch993pUQ X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Enabling RX FIFO Overflow interrupts is counterproductive and causes an interrupt storm when RX FIFO overflows. Disabling this interrupt has no side effect and eliminates interrupt storms when the RX FIFO overflows. Commit 8a7cb245cf28 ("net: stmmac: Do not enable RX FIFO overflow interrupts") disables RX FIFO overflow interrupts for DWMAC4 IP and removes the corresponding handling of this interrupt. This patch is doing the same thing for XGMAC IP. Fixes: 2142754f8b9c ("net: stmmac: Add MAC related callbacks for XGMAC2") Signed-off-by: Rohan G Thomas Reviewed-by: Matthew Gerlach Reviewed-by: Andrew Lunn --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/n= et/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 5dcc95bc0ad28b756accf9670c5fa00aa94fcfe3..7201a38842651a865493fce0cef= e757d6ae9bafa 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -203,10 +203,6 @@ static void dwxgmac2_dma_rx_mode(struct stmmac_priv *p= riv, void __iomem *ioaddr, } =20 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); - - /* Enable MTL RX overflow */ - value =3D readl(ioaddr + XGMAC_MTL_QINTEN(channel)); - writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); } =20 static void dwxgmac2_dma_tx_mode(struct stmmac_priv *priv, void __iomem *i= oaddr, --=20 2.25.1 From nobody Fri Oct 3 20:55:17 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E374D281508; Mon, 25 Aug 2025 04:37:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756096630; cv=none; b=s/CrRjchCRUG8qcQYhYfd9kGb4D1hsYH49M7WMynkXkyF2Wf7Scy3yFnSjpWLxWaGFINAo9ewL4jvqgaHRZGtnRvoJES9Cm+dZpjuarS0DiijuCIog5ncpuRO5piH4DJwB+PCdiT7FJU09KKX/OaCmB45uEFZRDB080LNaMM8FM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756096630; c=relaxed/simple; bh=ybvae2Us24QQdhHAuMB8pyUUuzHIpPAy3rGRBQp46KE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qsbnO3tDAZHPvlqCtH+4HApgqHHmPEHtaXLKOz72L5ZgniHeP6pCZ2GFuze/6IUhsVJ0GJCN0XVUjudvEBHuTrjTDOo5HChHHUMxqUdoIfFAgFxwKmh7Xssu3fvq4K8+BE0ohi8YtKvgvzSSrHuXA4OkAhh/Bw2zik/tSVOQB1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VXmmoFxU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VXmmoFxU" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8ED3BC16AAE; Mon, 25 Aug 2025 04:37:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756096629; bh=ybvae2Us24QQdhHAuMB8pyUUuzHIpPAy3rGRBQp46KE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VXmmoFxUvmN/RKP8X0WxHWlcHErhqkKv1nEW0RhAykBgxI0mfX5y/4/yrzC8jx6r/ NGjh1mMo0BnMceW1Ijx9w10M2wwRS1IjO+ju5Vt4fB40qTApKQst4itHEpLbkdjDuc 6pg129cnxGr6dJ1mUWoFbdxolbiGsOw/CmfHoOc1m45iQ6SsilfwFmp6weQKN1rt7z F/uybpcGCZfeMxcQAb8cQ8cdrQmn+JnHO5GTldhbK8rAPz5fEB1bgR189JZofHS9cV G4d9CPDzeHJwi+IhG0SVaEdyNpud2EgYNp4ylTXfRZzcCsHlFZkijd0BpOEkcmwShm djo6xk0NAsRYw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FCB7CA0FE7; Mon, 25 Aug 2025 04:37:09 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Mon, 25 Aug 2025 12:36:53 +0800 Subject: [PATCH net v3 2/3] net: stmmac: xgmac: Correct supported speed modes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-xgmac-minor-fixes-v3-2-c225fe4444c0@altera.com> References: <20250825-xgmac-minor-fixes-v3-0-c225fe4444c0@altera.com> In-Reply-To: <20250825-xgmac-minor-fixes-v3-0-c225fe4444c0@altera.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jose Abreu , Romain Gantois , Serge Semin , Ong Boon Leong Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756096627; l=3721; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=v7jKKlpJKKZxKVJEECl3l+uzpfLCSrlkjiiQ+9FsT98=; b=1bxAqjx4gTVyMo0s/j495nV6T5gag2LNSexWze59UHl5vLoX4KlIumiId0x8JibbHqsJtRdZ5 2jaVP0lehYnAkmbx4ZPsC1O8IjeVED7mxH1hrxVI63HkBrcp54lrKpk X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Correct supported speed modes as per the XGMAC databook. Commit 9cb54af214a7 ("net: stmmac: Fix IP-cores specific MAC capabilities") removes support for 10M, 100M and 1000HD. 1000HD is not supported by XGMAC IP, but it does support 10M and 100M FD mode for XGMAC version >=3D 2_20, and it also supports 10M and 100M HD mode if the HDSEL bit is set in the MAC_HW_FEATURE0 reg. This commit enables support for 10M and 100M speed modes for XGMAC IP based on XGMAC version and MAC capabilities. Fixes: 9cb54af214a7 ("net: stmmac: Fix IP-cores specific MAC capabilities") Signed-off-by: Rohan G Thomas Reviewed-by: Matthew Gerlach --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 13 +++++++++++-- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 5 +++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 6cadf8de4fdfdb18af1a112b883b3d33a53da638..00e929bf280baec7aa8d2a75fc5= ceea4a52c9979 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -49,6 +49,14 @@ static void dwxgmac2_core_init(struct mac_device_info *h= w, writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN); } =20 +static void dwxgmac2_update_caps(struct stmmac_priv *priv) +{ + if (!priv->dma_cap.mbps_10_100) + priv->hw->link.caps &=3D ~(MAC_10 | MAC_100); + else if (!priv->dma_cap.half_duplex) + priv->hw->link.caps &=3D ~(MAC_10HD | MAC_100HD); +} + static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable) { u32 tx =3D readl(ioaddr + XGMAC_TX_CONFIG); @@ -1424,6 +1432,7 @@ static void dwxgmac2_set_arp_offload(struct mac_devic= e_info *hw, bool en, =20 const struct stmmac_ops dwxgmac210_ops =3D { .core_init =3D dwxgmac2_core_init, + .update_caps =3D dwxgmac2_update_caps, .set_mac =3D dwxgmac2_set_mac, .rx_ipc =3D dwxgmac2_rx_ipc, .rx_queue_enable =3D dwxgmac2_rx_queue_enable, @@ -1532,8 +1541,8 @@ int dwxgmac2_setup(struct stmmac_priv *priv) mac->mcast_bits_log2 =3D ilog2(mac->multicast_filter_bins); =20 mac->link.caps =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | - MAC_1000FD | MAC_2500FD | MAC_5000FD | - MAC_10000FD; + MAC_10 | MAC_100 | MAC_1000FD | + MAC_2500FD | MAC_5000FD | MAC_10000FD; mac->link.duplex =3D 0; mac->link.speed10 =3D XGMAC_CONFIG_SS_10_MII; mac->link.speed100 =3D XGMAC_CONFIG_SS_100_MII; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/n= et/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 7201a38842651a865493fce0cefe757d6ae9bafa..4d6bb995d8d84cd31b8c552036a= 647281de06fbb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -382,8 +382,11 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *= priv, static int dwxgmac2_get_hw_feature(void __iomem *ioaddr, struct dma_features *dma_cap) { + struct stmmac_priv *priv; u32 hw_cap; =20 + priv =3D container_of(dma_cap, struct stmmac_priv, dma_cap); + /* MAC HW feature 0 */ hw_cap =3D readl(ioaddr + XGMAC_HW_FEATURE0); dma_cap->edma =3D (hw_cap & XGMAC_HWFEAT_EDMA) >> 31; @@ -406,6 +409,8 @@ static int dwxgmac2_get_hw_feature(void __iomem *ioaddr, dma_cap->vlhash =3D (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4; dma_cap->half_duplex =3D (hw_cap & XGMAC_HWFEAT_HDSEL) >> 3; dma_cap->mbps_1000 =3D (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1; + if (dma_cap->mbps_1000 && priv->synopsys_id >=3D DWXGMAC_CORE_2_20) + dma_cap->mbps_10_100 =3D 1; =20 /* MAC HW feature 1 */ hw_cap =3D readl(ioaddr + XGMAC_HW_FEATURE1); --=20 2.25.1 From nobody Fri Oct 3 20:55:17 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10B5028151E; Mon, 25 Aug 2025 04:37:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 25 Aug 2025 04:37:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756096629; bh=wwBDo6blRSFBdQltLRz6YF2EM5a8biOLLNX0om5ESo8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ingqzI70i6HXHgnFLwoVGatOuF3KLFBApNL2jOz7nyXw3URUo7qLEAapFvxs7HezL UobJM/jjX1HbxOwIZHqs9VoIPGy7RkNqUw8szQwDGBtXnDvP1ySSO1BQa7MymOSbfu gasDZdY50aT3n951/cf2YTgfQq91vIev3QpgUKDoDSOrRezbE6TUC+dlvcorn0vmWM CMYyzuyyNzSIFzHMmvtwnCUof8uveJPsvx7BzJuvCfr4cDddG7BsOMDrP6HPO3o7Dh cCjH+0mjuOdCFsMOEzLWkWlpWWo3i57Nqb1nWCKpTzBJOxRVDsV/G0yngMRJW1e9Nd q2ypFskKkk5pA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C3E6CA0EED; Mon, 25 Aug 2025 04:37:09 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Mon, 25 Aug 2025 12:36:54 +0800 Subject: [PATCH net v3 3/3] net: stmmac: Set CIC bit only for TX queues with COE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-xgmac-minor-fixes-v3-3-c225fe4444c0@altera.com> References: <20250825-xgmac-minor-fixes-v3-0-c225fe4444c0@altera.com> In-Reply-To: <20250825-xgmac-minor-fixes-v3-0-c225fe4444c0@altera.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jose Abreu , Romain Gantois , Serge Semin , Ong Boon Leong Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756096627; l=2589; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=ufHiTveJv2qBm24xiMB0gFsw0pu0zMd7hgFCJ9lPQkI=; b=J9xTvnesrv2sisMNAGCxcdrQoTHV2SLh3+3iW7faARF6ra+9ADLML6lJxH36GguS6UndD/PB5 eTShfFdRmoiBgCrCLRf6pVPz270nXnPUja344HDqgLcK5teGx39zsAD X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Currently, in the AF_XDP transmit paths, the CIC bit of TX Desc3 is set for all packets. Setting this bit for packets transmitting through queues that don't support checksum offloading causes the TX DMA to get stuck after transmitting some packets. This patch ensures the CIC bit of TX Desc3 is set only if the TX queue supports checksum offloading. Fixes: 132c32ee5bc0 ("net: stmmac: Add TX via XDP zero-copy socket") Signed-off-by: Rohan G Thomas Reviewed-by: Matthew Gerlach --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index fa3d26c285025d01c72cef51add534fc722552b8..143e68639548f390e97b5a8dd09= f3f4af12cec43 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2585,6 +2585,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *pr= iv, u32 queue, u32 budget) struct netdev_queue *nq =3D netdev_get_tx_queue(priv->dev, queue); struct stmmac_tx_queue *tx_q =3D &priv->dma_conf.tx_queue[queue]; struct stmmac_txq_stats *txq_stats =3D &priv->xstats.txq_stats[queue]; + bool csum =3D !priv->plat->tx_queues_cfg[queue].coe_unsupported; struct xsk_buff_pool *pool =3D tx_q->xsk_pool; unsigned int entry =3D tx_q->cur_tx; struct dma_desc *tx_desc =3D NULL; @@ -2672,7 +2673,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *pr= iv, u32 queue, u32 budget) } =20 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, - true, priv->mode, true, true, + csum, priv->mode, true, true, xdp_desc.len); =20 stmmac_enable_dma_transmission(priv, priv->ioaddr, queue); @@ -4987,6 +4988,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *p= riv, int queue, { struct stmmac_txq_stats *txq_stats =3D &priv->xstats.txq_stats[queue]; struct stmmac_tx_queue *tx_q =3D &priv->dma_conf.tx_queue[queue]; + bool csum =3D !priv->plat->tx_queues_cfg[queue].coe_unsupported; unsigned int entry =3D tx_q->cur_tx; struct dma_desc *tx_desc; dma_addr_t dma_addr; @@ -5038,7 +5040,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *p= riv, int queue, stmmac_set_desc_addr(priv, tx_desc, dma_addr); =20 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, - true, priv->mode, true, true, + csum, priv->mode, true, true, xdpf->len); =20 tx_q->tx_count_frames++; --=20 2.25.1