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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF00026369.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.9052.8 via Frontend Transport; Mon, 25 Aug 2025 17:33:41 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 25 Aug 2025 12:33:36 -0500 From: Yazen Ghannam Date: Mon, 25 Aug 2025 17:33:00 +0000 Subject: [PATCH v5 03/20] x86/mce/amd: Remove smca_banks_map Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-wip-mca-updates-v5-3-865768a2eef8@amd.com> References: <20250825-wip-mca-updates-v5-0-865768a2eef8@amd.com> In-Reply-To: <20250825-wip-mca-updates-v5-0-865768a2eef8@amd.com> To: , Tony Luck , "Rafael J. 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In this way, an implementation-specific number of registers can be discovered at runtime. The MCAX/SMCA register space simplifies this by always including the MCx_MISC[1-4] registers. The MCx_MISC0[BlkPtr] field is used to indicate (true/false) whether any MCx_MISC[1-4] registers are present. Currently, MCx_MISC0[BlkPtr] is checked early and cached to be used during sysfs init later. This is unnecessary as the MCx_MISC0 register is read again later anyway. Remove the smca_banks_map variable as it is effectively redundant, and use a direct register/bit check instead. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250624-wip-mca-updates-v4-7-236dd74f645f@am= d.com =20 v4->v5: * Keep MCx_MISC0[BlkPtr] check to be compliant with uarch. =20 v3->v4: * No change. =20 v2->v3: * Minor edit in commit message. * Added tags from Qiuxu and Tony. =20 v1->v2: * New in v2. arch/x86/kernel/cpu/mce/amd.c | 34 +++------------------------------- 1 file changed, 3 insertions(+), 31 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index f429451cafc8..580682af432d 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -252,9 +252,6 @@ static DEFINE_PER_CPU(struct threshold_bank **, thresho= ld_banks); */ static DEFINE_PER_CPU(u64, bank_map); =20 -/* Map of banks that have more than MCA_MISC0 available. */ -static DEFINE_PER_CPU(u64, smca_misc_banks_map); - static void amd_threshold_interrupt(void); static void amd_deferred_error_interrupt(void); =20 @@ -264,28 +261,6 @@ static void default_deferred_error_interrupt(void) } void (*deferred_error_int_vector)(void) =3D default_deferred_error_interru= pt; =20 -static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) -{ - u32 low, high; - - /* - * For SMCA enabled processors, BLKPTR field of the first MISC register - * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). - */ - if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) - return; - - if (!(low & MCI_CONFIG_MCAX)) - return; - - if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) - return; - - if (low & MASK_BLKPTR_LO) - per_cpu(smca_misc_banks_map, cpu) |=3D BIT_ULL(bank); - -} - static void smca_configure(unsigned int bank, unsigned int cpu) { u8 *bank_counts =3D this_cpu_ptr(smca_bank_counts); @@ -326,8 +301,6 @@ static void smca_configure(unsigned int bank, unsigned = int cpu) wrmsr(smca_config, low, high); } =20 - smca_set_misc_banks_map(bank, cpu); - if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { pr_warn("Failed to read MCA_IPID for bank %d\n", bank); return; @@ -525,13 +498,12 @@ static void deferred_error_interrupt_enable(struct cp= uinfo_x86 *c) wrmsr(MSR_CU_DEF_ERR, low, high); } =20 -static u32 smca_get_block_address(unsigned int bank, unsigned int block, - unsigned int cpu) +static u32 smca_get_block_address(unsigned int bank, unsigned int block, u= 32 low) { if (!block) return MSR_AMD64_SMCA_MCx_MISC(bank); =20 - if (!(per_cpu(smca_misc_banks_map, cpu) & BIT_ULL(bank))) + if (!(low & MASK_BLKPTR_LO)) return 0; =20 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); @@ -547,7 +519,7 @@ static u32 get_block_address(u32 current_addr, u32 low,= u32 high, return addr; =20 if (mce_flags.smca) - return smca_get_block_address(bank, block, cpu); + return smca_get_block_address(bank, block, low); =20 /* Fall back to method we used for older processors: */ switch (block) { --=20 2.51.0