From nobody Fri Oct 3 20:29:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B1D13594F; Mon, 25 Aug 2025 12:32:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756125162; cv=none; b=XGYjtNDgEiJiY3Oery2DoAD/lAXj3ftCmPH/s6niD7iyDcNk+Dvyvq7v25eihp2ogiGy3ifHz6PwGkLHgllDpsuvKX1joFZdzVip7dElzpCFtaWaFwDKCmCyiyY7wnp9olOYa0x2Ras74/qZcVo8Nac4ah0E2HQ2y9cF3XdXXnw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756125162; c=relaxed/simple; bh=P/UDeMbttcPSVyBfhR/SlfF0HWH/j0Dfq4acB/iaDFs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jsko0+QiXZaQyxoFCtVe4truAdQZehYEdqYsrXFJhoFYuXbQoCO9YjXTV0MKgDsCuVIJP8H/ZVVoP4UKQUsVdisznIoIL1hyk6lFsVw9HEw7UMvgMkYfz13MoPWpVUgANk3GVV5blT4Q+PRzLXdT1+s0VSOC+D5Vs1jVm8U91Ig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SYKnRMoz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SYKnRMoz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1BE57C116C6; Mon, 25 Aug 2025 12:32:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756125162; bh=P/UDeMbttcPSVyBfhR/SlfF0HWH/j0Dfq4acB/iaDFs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SYKnRMozwSTs9BhHL0+crl9G5HlDXFTAHExBjKcfZISl5kKOln2BUBIL8oBRzQfl2 tevQw7gxIJHZ7LKvDMhaaYMHmHfakA0ZSyLkk3gle8SsW30GrkMdvXvmJniE9viwgx MtyjAjbZpfLsm4l28taBY1CUAyvtEopIOq0trxRF/gBf6EUCYCuIu49Er6UbxtfZZ6 5TkH/ZARX4/lqV7bAR7dChu07HVGGEn8xq7etlGdkgZ2X4U7w8xEcicmzGRs0hkyce lJWQvfy/aH1W3wqv4IrOYbecfsdSPIOzErVqSUff95UO4JEESv0cXCPwtt7vvw+8rP VNJN5tMtJ6slQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED652CA0FE9; Mon, 25 Aug 2025 12:32:41 +0000 (UTC) From: Nickolay Goppen via B4 Relay Date: Mon, 25 Aug 2025 15:32:28 +0300 Subject: [PATCH v3 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-sdm660-lpass-lpi-v3-1-65d4a4db298e@yandex.ru> References: <20250825-sdm660-lpass-lpi-v3-0-65d4a4db298e@yandex.ru> In-Reply-To: <20250825-sdm660-lpass-lpi-v3-0-65d4a4db298e@yandex.ru> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nickolay Goppen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756125160; l=2711; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=JXoM3miyeg5XfaW9RV8i7oWQ6FTIiwpKlwfmyKxAlDw=; b=FYawZWsVh/I4+POXMh4WtPpuOBsqAOadAxCDc7xg66BNRj8/zgcbhRtuW/jkUoznfI8gihU28 4EWLH8v3AIQCdcaNVEu5huCywip/atLGEDQpkPXJwB1sHx0OUS/dQWF X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= X-Endpoint-Received: by B4 Relay for setotau@yandex.ru/20250815 with auth_id=492 X-Original-From: Nickolay Goppen Reply-To: setotau@yandex.ru From: Nickolay Goppen By default pin_offset is calculated by formula: LPI_TLMM_REG_OFFSET * pin_i= d. However not all platforms are using this pin_offset formula (e.g. SDM660 LP= ASS LPI uses a predefined array of offsets [1]), so add a callback to the defau= lt pin_offset function to add an ability for some platforms to use their own q= uirky pin_offset functions and add callbacks to pin_offset_default function for o= ther platforms. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-0= 7400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Signed-off-by: Nickolay Goppen Reviewed-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 18 ++++++++++++++++-- drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 7 +++++++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 57fefeb603f0e2502fccd14ba3982ae3cb591978..aa307088b0eedd3f2fe86045c1d= 71ab8a855858f 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -41,13 +41,27 @@ struct lpi_pinctrl { static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) { - return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + u32 pin_offset; + + if (!state->data->pin_offset) + pin_offset =3D lpi_pinctrl_pin_offset_default(pin); + else + pin_offset =3D state->data->pin_offset(pin); + + return ioread32(state->tlmm_base + pin_offset + addr); } =20 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { - iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + u32 pin_offset; + + if (!state->data->pin_offset) + pin_offset =3D lpi_pinctrl_pin_offset_default(pin); + else + pin_offset =3D state->data->pin_offset(pin); + + iowrite32(val, state->tlmm_base + pin_offset + addr); =20 return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.h index a9b2f65c1ebe0f8fb5d7814f8ef8b723c617c85b..bfb85d438a02a5041c4d0218fd6= 4bb68324b5881 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -85,9 +85,16 @@ struct lpi_pinctrl_variant_data { const struct lpi_function *functions; int nfunctions; unsigned int flags; + u32 (*pin_offset)(int pin_id); }; =20 int lpi_pinctrl_probe(struct platform_device *pdev); void lpi_pinctrl_remove(struct platform_device *pdev); =20 +static inline u32 lpi_pinctrl_pin_offset_default(int pin_id) +{ + return LPI_TLMM_REG_OFFSET * pin_id; +} + + #endif /*__PINCTRL_LPASS_LPI_H__*/ --=20 2.51.0 From nobody Fri Oct 3 20:29:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B23135965; Mon, 25 Aug 2025 12:32:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756125162; cv=none; b=Bh3NUcV/tjZiUy0MI+T938Myvs3Gsrgr5D6PE5V2xWs7BpiwF4PrmujiDHJSDj3mMXhUFdTQOdnLp5xnWWsQY5GIH6yzEyYb3Y+xccQrNROo+QpSthKMB5nr73x9lfLbNaH7xOHYmDKB0fWL4IqCRUwaIAAbq/pMCf3OxZ017EI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756125162; c=relaxed/simple; bh=FiS7jd5aADRgPn/gVSL2fBEPfJMjQCFYti3lIUvrhJM=; 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Mon, 25 Aug 2025 12:32:42 +0000 (UTC) From: Nickolay Goppen via B4 Relay Date: Mon, 25 Aug 2025 15:32:29 +0300 Subject: [PATCH v3 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-sdm660-lpass-lpi-v3-2-65d4a4db298e@yandex.ru> References: <20250825-sdm660-lpass-lpi-v3-0-65d4a4db298e@yandex.ru> In-Reply-To: <20250825-sdm660-lpass-lpi-v3-0-65d4a4db298e@yandex.ru> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nickolay Goppen , Richard Acayan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756125160; l=2866; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=lw+wkCHuwJi81P9r9kd3s9iM9l26tF2/jGo2tCXg0SE=; b=XQ1QJj3KCvVQxp/xhTtuvKLdPuN6D990inQAjITepFMYg9rVxxp0doz6HP6zCKR/f/ORUySig ShInPV+uZcSA/62pccmDdmqip42ueV91FAVcO/tY16ecLflff47BX0J X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= X-Endpoint-Received: by B4 Relay for setotau@yandex.ru/20250815 with auth_id=492 X-Original-From: Nickolay Goppen Reply-To: setotau@yandex.ru From: Nickolay Goppen Add bindings for pin controller in SDM660 Low Power Audio SubSystem (LPASS). Co-developed-by: Richard Acayan Signed-off-by: Richard Acayan Signed-off-by: Nickolay Goppen --- .../pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml | 74 ++++++++++++++++++= ++++ 1 file changed, 74 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lp= i-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpas= s-lpi-pinctrl.yaml new file mode 100644 index 0000000000000000000000000000000000000000..6b930a5b914bc79a00dbaead411= 89efc525c2eb2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinct= rl.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM660 SoC LPASS LPI TLMM + +maintainers: + - Nickolay Goppen + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSyst= em + (LPASS) Low Power Island (LPI) of Qualcomm SDM660 SoC. + +properties: + compatible: + const: qcom,sdm660-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm660-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm660-lpass-state" + additionalProperties: false + +$defs: + qcom-sdm660-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-6])$" + + function: + enum: [ gpio, comp_rx, dmic12, dmic34, mclk0, pdm_2_gpios, + pdm_clk, pdm_rx, pdm_sync ] + description: + Specify the alternative function to be configured for the specif= ied + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + lpi_tlmm: pinctrl@15070000 { + compatible =3D "qcom,sdm660-lpass-lpi-pinctrl"; + reg =3D <0x15070000 0x20000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpi_tlmm 0 0 32>; + }; --=20 2.51.0 From nobody Fri Oct 3 20:29:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8987138FB9; Mon, 25 Aug 2025 12:32:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756125162; cv=none; b=dHcu+bVC0fzRj6Pv9k4j4upo1k56dySrCkPp8wtvplb95e4hz2PegvU0XzGafKmkGyXk0huV+bn0AdwyNAk1dk4/KloPEevfTG4SLaIdpfwOCzoZFxHC1FLVQTmFtQBn/WOSSxPHPAYkXHdmJIOpTFWRvnTTT0ilAoEUD/7qENs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756125162; c=relaxed/simple; bh=27oRDKloyLag3j/Hytskw7lR0SKMLd5HrK4AzkisHrA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Mon, 25 Aug 2025 12:32:42 +0000 (UTC) From: Nickolay Goppen via B4 Relay Date: Mon, 25 Aug 2025 15:32:30 +0300 Subject: [PATCH v3 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-sdm660-lpass-lpi-v3-3-65d4a4db298e@yandex.ru> References: <20250825-sdm660-lpass-lpi-v3-0-65d4a4db298e@yandex.ru> In-Reply-To: <20250825-sdm660-lpass-lpi-v3-0-65d4a4db298e@yandex.ru> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nickolay Goppen , Richard Acayan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756125160; l=8821; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=2FkNa+Pkw2vKfrl0HjWMBEMkTikG2zyE3vuQ7SqMbw4=; b=Zrg7Ns2UH8gSN/qbonS0VBITA1ilSh+M4Oacbf3nlYXqdyiACnNamiTYlz28CQIqk+g2QubSA 5xGLa9WfQBMAYnQISh/lAeCQ2NXtaOWPwPlJ9Di/RGht3V5RqZ9rsAp X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= X-Endpoint-Received: by B4 Relay for setotau@yandex.ru/20250815 with auth_id=492 X-Original-From: Nickolay Goppen Reply-To: setotau@yandex.ru From: Richard Acayan The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring pins related to audio. Add the driver for this. Also, this driver uses it's own quirky pin_offset function like downstream driver does [1]. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-0= 7400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Signed-off-by: Richard Acayan Co-developed-by: Nickolay Goppen Signed-off-by: Nickolay Goppen Reviewed-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/Kconfig | 10 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 196 ++++++++++++++++++++= ++++ 3 files changed, 207 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index dd9bbe8f3e11c37418d2143b33c21eeea10d456b..ef42520115f461302098d878cb7= 6c6f25e55b5e4 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,16 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platfo= rm. =20 +config PINCTRL_SDM660_LPASS_LPI + tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller drive= r" + depends on GPIOLIB + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platfo= rm. + config PINCTRL_SM4250_LPASS_LPI tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller drive= r" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 954f5291cc37242baffc021e3c68d850aabd57cd..cea8617ac650ecfc75c2a0c745a= 53d6a1b829842 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) +=3D pinctrl-sc728= 0-lpass-lpi.o obj-$(CONFIG_PINCTRL_SC8180X) +=3D pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SC8280XP) +=3D pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) +=3D pinctrl-sdm660.o +obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) +=3D pinctrl-sdm660-lpass-lpi.o obj-$(CONFIG_PINCTRL_SDM670) +=3D pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_SDM845) +=3D pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) +=3D pinctrl-sdx55.o diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sdm660-lpass-lpi.c new file mode 100644 index 0000000000000000000000000000000000000000..36fba93fda1160ad51a979996f8= 007393555f222 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * This driver is solely based on the limited information in downstream co= de. + * Any verification with schematics would be greatly appreciated. + * + * Copyright (c) 2023, Richard Acayan. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_comp_rx, + LPI_MUX_dmic12, + LPI_MUX_dmic34, + LPI_MUX_mclk0, + LPI_MUX_pdm_2_gpios, + LPI_MUX_pdm_clk, + LPI_MUX_pdm_rx, + LPI_MUX_pdm_sync, + + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const u32 sdm660_lpi_offset[] =3D { + 0x00000000, + 0x00001000, + 0x00002000, + 0x00002010, + 0x00003000, + 0x00003010, + 0x00004000, + 0x00004010, + 0x00005000, + 0x00005010, + 0x00005020, + 0x00005030, + 0x00006000, + 0x00006010, + 0x00007000, + 0x00007010, + 0x00005040, + 0x00005050, + 0x00008000, + 0x00008010, + 0x00008020, + 0x00008030, + 0x00008040, + 0x00008050, + 0x00008060, + 0x00008070, + 0x00009000, + 0x00009010, + 0x0000a000, + 0x0000a010, + 0x0000b000, + 0x0000b010, +}; + +static const struct pinctrl_pin_desc sdm660_lpi_pinctrl_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), +}; + +static const char * const comp_rx_groups[] =3D { "gpio22", "gpio24" }; +static const char * const dmic12_groups[] =3D { "gpio26", "gpio28" }; +static const char * const dmic34_groups[] =3D { "gpio27", "gpio29" }; +static const char * const mclk0_groups[] =3D { "gpio18" }; +static const char * const pdm_2_gpios_groups[] =3D { "gpio20" }; +static const char * const pdm_clk_groups[] =3D { "gpio18" }; +static const char * const pdm_rx_groups[] =3D { "gpio21", "gpio23", "gpio2= 5" }; +static const char * const pdm_sync_groups[] =3D { "gpio19" }; + +const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] =3D { + LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(11, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _), + + /* The function names of the PDM GPIOs are derived from SDM670 */ + LPI_PINGROUP(18, LPI_NO_SLEW, pdm_clk, mclk0, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, pdm_sync, _, _, _), + LPI_PINGROUP(20, LPI_NO_SLEW, pdm_2_gpios, _, _, _), + LPI_PINGROUP(21, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, comp_rx, _, _, _), + LPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _), + LPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(26, LPI_NO_SLEW, dmic12, _, _, _), + LPI_PINGROUP(27, LPI_NO_SLEW, dmic34, _, _, _), + LPI_PINGROUP(28, LPI_NO_SLEW, dmic12, _, _, _), + LPI_PINGROUP(29, LPI_NO_SLEW, dmic34, _, _, _), + + LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _), +}; + +const struct lpi_function sdm660_lpi_pinctrl_functions[] =3D { + LPI_FUNCTION(comp_rx), + LPI_FUNCTION(dmic12), + LPI_FUNCTION(dmic34), + LPI_FUNCTION(mclk0), + LPI_FUNCTION(pdm_2_gpios), + LPI_FUNCTION(pdm_clk), + LPI_FUNCTION(pdm_rx), + LPI_FUNCTION(pdm_sync), +}; + +static u32 lpi_pinctrl_pin_offset_sdm660(int pin_id) +{ + return sdm660_lpi_offset[pin_id]; +} + +static const struct lpi_pinctrl_variant_data sdm660_lpi_pinctrl_data =3D { + .pins =3D sdm660_lpi_pinctrl_pins, + .npins =3D ARRAY_SIZE(sdm660_lpi_pinctrl_pins), + .groups =3D sdm660_lpi_pinctrl_groups, + .ngroups =3D ARRAY_SIZE(sdm660_lpi_pinctrl_groups), + .functions =3D sdm660_lpi_pinctrl_functions, + .nfunctions =3D ARRAY_SIZE(sdm660_lpi_pinctrl_functions), + .flags =3D LPI_FLAG_SLEW_RATE_SAME_REG, + .pin_offset =3D lpi_pinctrl_pin_offset_sdm660, +}; + +static const struct of_device_id sdm660_lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,sdm660-lpass-lpi-pinctrl", + .data =3D &sdm660_lpi_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); + +static struct platform_driver sdm660_lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-sdm660-lpass-lpi-pinctrl", + .of_match_table =3D sdm660_lpi_pinctrl_of_match, + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; +module_platform_driver(sdm660_lpi_pinctrl_driver); + +MODULE_AUTHOR("Richard Acayan "); +MODULE_DESCRIPTION("QTI SDM660 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0