From nobody Fri Oct 3 21:42:32 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F7352BDC2F for ; Mon, 25 Aug 2025 08:57:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112236; cv=none; b=EytQfBPQRDNc/Tkn96N+F7a+ABlr+kRwBLuhrgODWguC04KZP3E9b+p8Rlevg89HbvWJfI1H61pdkATlmnVbx9SfyjhsRk+nE1r9wSIhF/1kO3l7phHtrVEkaM420zjUbTp2E57HRUO//hoDZKD2co7rvf3FJvNoEDAfHnhJfwY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112236; c=relaxed/simple; bh=7+Og7rUGyFk1HcTP8p4Uyc/PYhGejFb5kkEHeMTwBtE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=es57SdwQfeDSdmJF10EZsre0KTQtEii6JzjJ+OCTuu53+ivt/B72stlUPlFCV2oUvRIlzK7IQ5/+VNIK746KoBzf4r5NGfwPX4U0oMiUOYkhd6L9lw1/nNnY5Ha0yarrxcfbg0hddbqaIXiojPzuGeaJLVr2iKkf+feFeF3htU4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=e8t1tZDP; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="e8t1tZDP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756112232; bh=7+Og7rUGyFk1HcTP8p4Uyc/PYhGejFb5kkEHeMTwBtE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=e8t1tZDPcuW161VQWs4w0ue0FAugHx845eecL9ak/QF7jzENLXTW2i1NZ1kuPpOo3 QureLvkUvzB5b7fxs2ahRl3275k+M7fu/ByWkA3i0FVS58OFRshrBmv9Xx+8s1dZQ2 tvq8nGYXON2E0muImZxp1q+NkjOcH07rX9DExONsKx1coznAInXe1YJQv/pVBIc4aQ IUjjFdpj0HyPT0oUs9J7q2j5WcDmbe6KhrdwzYcilOPy722smVYgGYhze7hL06WdIj A+hj7gYWCleSVtkdIvrRVwRDuxfHrKY9g7uPolB7re9Kz5g1YPbNednZJWezpx8sQG 7lWCoUvLQKTcg== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 7752817E059E; Mon, 25 Aug 2025 10:57:12 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 25 Aug 2025 11:56:45 +0300 Subject: [PATCH v3 5/6] drm/rockchip: dw_hdmi_qp: Provide ref clock rate in dw_hdmi_qp_plat_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-rk3588-hdmi-cec-v3-5-95324fb22592@collabora.com> References: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> In-Reply-To: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 In order to support correct initialization of the timer base in the HDMI QP IP block, setup platform data to include the required reference clock rate. While at it, ensure plat_data is zero-initialized in dw_hdmi_qp_rockchip_bind(). Signed-off-by: Cristian Ciocaltea Reviewed-by: Daniel Stone --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 39b46327afd8e4753d96962fad66792d22b33402..5280383febe25cf579c306ec164= 2557600595e58 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -431,14 +431,15 @@ static int dw_hdmi_qp_rockchip_bind(struct device *de= v, struct device *master, void *data) { struct platform_device *pdev =3D to_platform_device(dev); + struct dw_hdmi_qp_plat_data plat_data =3D {}; const struct rockchip_hdmi_qp_cfg *cfg; - struct dw_hdmi_qp_plat_data plat_data; struct drm_device *drm =3D data; struct drm_connector *connector; struct drm_encoder *encoder; struct rockchip_hdmi_qp *hdmi; struct resource *res; struct clk_bulk_data *clks; + struct clk *ref_clk; int ret, irq, i; =20 if (!pdev->dev.of_node) @@ -508,6 +509,14 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, if (ret < 0) return dev_err_probe(hdmi->dev, ret, "Failed to get clocks\n"); =20 + ref_clk =3D clk_get(hdmi->dev, "ref"); + if (IS_ERR(ref_clk)) + return dev_err_probe(hdmi->dev, PTR_ERR(ref_clk), + "Failed to get ref clock\n"); + + plat_data.ref_clk_rate =3D clk_get_rate(ref_clk); + clk_put(ref_clk); + hdmi->enable_gpio =3D devm_gpiod_get_optional(hdmi->dev, "enable", GPIOD_OUT_HIGH); if (IS_ERR(hdmi->enable_gpio)) --=20 2.50.1